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Wed, 13 Mar 2024 11:20:58 -0700 (PDT) From: Himanshu Chauhan To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v5 3/3] target/riscv: Enable sdtrig for Ventana's Veyron CPUs Date: Wed, 13 Mar 2024 23:50:09 +0530 Message-Id: <20240313182009.608685-4-hchauhan@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240313182009.608685-1-hchauhan@ventanamicro.com> References: <20240313182009.608685-1-hchauhan@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=hchauhan@ventanamicro.com; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1710354112611100003 Content-Type: text/plain; charset="utf-8" Ventana's Veyron CPUs support sdtrig ISA extension. By default, enable the sdtrig extension and disable the debug property for these CPUs. Signed-off-by: Himanshu Chauhan --- target/riscv/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index e0710010f5..a7ea66c7fa 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -568,7 +568,9 @@ static void rv64_veyron_v1_cpu_init(Object *obj) cpu->cfg.ext_zicbom =3D true; cpu->cfg.cbom_blocksize =3D 64; cpu->cfg.cboz_blocksize =3D 64; + cpu->cfg.debug =3D false; cpu->cfg.ext_zicboz =3D true; + cpu->cfg.ext_sdtrig =3D true; cpu->cfg.ext_smaia =3D true; cpu->cfg.ext_ssaia =3D true; cpu->cfg.ext_sscofpmf =3D true; --=20 2.34.1