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Wed, 13 Mar 2024 11:20:55 -0700 (PDT) From: Himanshu Chauhan To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v5 1/3] target/riscv: Enable mcontrol6 triggers only when sdtrig is selected Date: Wed, 13 Mar 2024 23:50:07 +0530 Message-Id: <20240313182009.608685-2-hchauhan@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240313182009.608685-1-hchauhan@ventanamicro.com> References: <20240313182009.608685-1-hchauhan@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=hchauhan@ventanamicro.com; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01, T_SPF_HELO_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1710354134673100001 Content-Type: text/plain; charset="utf-8" The mcontrol6 triggers are not defined in debug specification v0.13 These triggers are defined in sdtrig ISA extension. This patch: * Adds ext_sdtrig capability which is used to select mcontrol6 triggers * Keeps the debug property. All triggers that are defined in v0.13 are exposed. Signed-off-by: Himanshu Chauhan --- target/riscv/cpu.c | 4 +- target/riscv/cpu_cfg.h | 1 + target/riscv/csr.c | 2 +- target/riscv/debug.c | 90 +++++++++++++++++++++++++----------------- target/riscv/machine.c | 2 +- 5 files changed, 58 insertions(+), 41 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index c160b9216b..2602aae9f5 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1008,7 +1008,7 @@ static void riscv_cpu_reset_hold(Object *obj) set_default_nan_mode(1, &env->fp_status); =20 #ifndef CONFIG_USER_ONLY - if (cpu->cfg.debug) { + if (cpu->cfg.debug || cpu->cfg.ext_sdtrig) { riscv_trigger_reset_hold(env); } =20 @@ -1168,7 +1168,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error= **errp) riscv_cpu_register_gdb_regs_for_features(cs); =20 #ifndef CONFIG_USER_ONLY - if (cpu->cfg.debug) { + if (cpu->cfg.debug || cpu->cfg.ext_sdtrig) { riscv_trigger_realize(&cpu->env); } #endif diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index 2040b90da0..0c57e1acd4 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -114,6 +114,7 @@ struct RISCVCPUConfig { bool ext_zvfbfwma; bool ext_zvfh; bool ext_zvfhmin; + bool ext_sdtrig; bool ext_smaia; bool ext_ssaia; bool ext_sscofpmf; diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 726096444f..26623d3640 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -546,7 +546,7 @@ static RISCVException have_mseccfg(CPURISCVState *env, = int csrno) =20 static RISCVException debug(CPURISCVState *env, int csrno) { - if (riscv_cpu_cfg(env)->debug) { + if (riscv_cpu_cfg(env)->debug || riscv_cpu_cfg(env)->ext_sdtrig) { return RISCV_EXCP_NONE; } =20 diff --git a/target/riscv/debug.c b/target/riscv/debug.c index e30d99cc2f..674223e966 100644 --- a/target/riscv/debug.c +++ b/target/riscv/debug.c @@ -100,13 +100,15 @@ static trigger_action_t get_trigger_action(CPURISCVSt= ate *env, target_ulong tdata1 =3D env->tdata1[trigger_index]; int trigger_type =3D get_trigger_type(env, trigger_index); trigger_action_t action =3D DBG_ACTION_NONE; + const RISCVCPUConfig *cfg =3D riscv_cpu_cfg(env); =20 switch (trigger_type) { case TRIGGER_TYPE_AD_MATCH: action =3D (tdata1 & TYPE2_ACTION) >> 12; break; case TRIGGER_TYPE_AD_MATCH6: - action =3D (tdata1 & TYPE6_ACTION) >> 12; + if (cfg->ext_sdtrig) + action =3D (tdata1 & TYPE6_ACTION) >> 12; break; case TRIGGER_TYPE_INST_CNT: case TRIGGER_TYPE_INT: @@ -727,7 +729,12 @@ void tdata_csr_write(CPURISCVState *env, int tdata_ind= ex, target_ulong val) type2_reg_write(env, env->trigger_cur, tdata_index, val); break; case TRIGGER_TYPE_AD_MATCH6: - type6_reg_write(env, env->trigger_cur, tdata_index, val); + if (riscv_cpu_cfg(env)->ext_sdtrig) { + type6_reg_write(env, env->trigger_cur, tdata_index, val); + } else { + qemu_log_mask(LOG_UNIMP, "trigger type: %d is not supported\n", + trigger_type); + } break; case TRIGGER_TYPE_INST_CNT: itrigger_reg_write(env, env->trigger_cur, tdata_index, val); @@ -750,9 +757,14 @@ void tdata_csr_write(CPURISCVState *env, int tdata_ind= ex, target_ulong val) =20 target_ulong tinfo_csr_read(CPURISCVState *env) { - /* assume all triggers support the same types of triggers */ - return BIT(TRIGGER_TYPE_AD_MATCH) | - BIT(TRIGGER_TYPE_AD_MATCH6); + target_ulong ts =3D 0; + + ts =3D BIT(TRIGGER_TYPE_AD_MATCH); + + if (riscv_cpu_cfg(env)->ext_sdtrig) + ts |=3D BIT(TRIGGER_TYPE_AD_MATCH6); + + return ts; } =20 void riscv_cpu_debug_excp_handler(CPUState *cs) @@ -803,19 +815,21 @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs) } break; case TRIGGER_TYPE_AD_MATCH6: - ctrl =3D env->tdata1[i]; - pc =3D env->tdata2[i]; - - if ((ctrl & TYPE6_EXEC) && (bp->pc =3D=3D pc)) { - if (env->virt_enabled) { - /* check VU/VS bit against current privilege level= */ - if ((ctrl >> 23) & BIT(env->priv)) { - return true; - } - } else { - /* check U/S/M bit against current privilege level= */ - if ((ctrl >> 3) & BIT(env->priv)) { - return true; + if (cpu->cfg.ext_sdtrig) { + ctrl =3D env->tdata1[i]; + pc =3D env->tdata2[i]; + + if ((ctrl & TYPE6_EXEC) && (bp->pc =3D=3D pc)) { + if (env->virt_enabled) { + /* check VU/VS bit against current privilege l= evel */ + if ((ctrl >> 23) & BIT(env->priv)) { + return true; + } + } else { + /* check U/S/M bit against current privilege l= evel */ + if ((ctrl >> 3) & BIT(env->priv)) { + return true; + } } } } @@ -869,27 +883,29 @@ bool riscv_cpu_debug_check_watchpoint(CPUState *cs, C= PUWatchpoint *wp) } break; case TRIGGER_TYPE_AD_MATCH6: - ctrl =3D env->tdata1[i]; - addr =3D env->tdata2[i]; - flags =3D 0; + if (cpu->cfg.ext_sdtrig) { + ctrl =3D env->tdata1[i]; + addr =3D env->tdata2[i]; + flags =3D 0; =20 - if (ctrl & TYPE6_LOAD) { - flags |=3D BP_MEM_READ; - } - if (ctrl & TYPE6_STORE) { - flags |=3D BP_MEM_WRITE; - } + if (ctrl & TYPE6_LOAD) { + flags |=3D BP_MEM_READ; + } + if (ctrl & TYPE6_STORE) { + flags |=3D BP_MEM_WRITE; + } =20 - if ((wp->flags & flags) && (wp->vaddr =3D=3D addr)) { - if (env->virt_enabled) { - /* check VU/VS bit against current privilege level */ - if ((ctrl >> 23) & BIT(env->priv)) { - return true; - } - } else { - /* check U/S/M bit against current privilege level */ - if ((ctrl >> 3) & BIT(env->priv)) { - return true; + if ((wp->flags & flags) && (wp->vaddr =3D=3D addr)) { + if (env->virt_enabled) { + /* check VU/VS bit against current privilege level= */ + if ((ctrl >> 23) & BIT(env->priv)) { + return true; + } + } else { + /* check U/S/M bit against current privilege level= */ + if ((ctrl >> 3) & BIT(env->priv)) { + return true; + } } } } diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 76f2150f78..383151a4f8 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -230,7 +230,7 @@ static bool debug_needed(void *opaque) { RISCVCPU *cpu =3D opaque; =20 - return cpu->cfg.debug; + return cpu->cfg.debug || cpu->cfg.ext_sdtrig; } =20 static int debug_post_load(void *opaque, int version_id) --=20 2.34.1