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12 Mar 2024 06:53:18 -0700 Received: from wufei-optiplex-7090.sh.intel.com ([10.239.158.51]) by fmviesa004.fm.intel.com with ESMTP; 12 Mar 2024 06:53:12 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1710251600; x=1741787600; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=B7hUgrydAGNXirDIBSrhE+PD6xB63EP+VorsUIei5Yk=; b=MyUzAbwu35srSZCNygNebjPy/LWvMSJoO7sUWAwDlC681X91AYLzvezO 6vNQX2IKlUJaWshChoAS5old2ahbKSvvmCFTbnIZH3Xt2dFUmHCu0YL7U 7VwWCn2te7lt7jYOQsXukRWZBX9Y/Jg8fYZgLxYcF/FJG+Ozi69mxyTp+ iQbwJLO4C5xwt23rHoG0o921eyJkCcakZivHmwYkaAoRXRETRoqsRO+AS u4UvKj2LytyEdGo8zGj7ENjcP9avnJOGtUMxNSejuGoAekszSqc+Oegl1 fSQ0dqyYl7kOk/0xt6A++2hNNVXKe0GvfGc3uGdW66y+95pbsXad6lbZ7 g==; X-IronPort-AV: E=McAfee;i="6600,9927,11010"; a="4887940" X-IronPort-AV: E=Sophos;i="6.07,119,1708416000"; d="scan'208";a="4887940" X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,119,1708416000"; d="scan'208";a="16148592" From: Fei Wu To: pbonzini@redhat.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, liwei1518@gmail.com, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, qemu-devel@nongnu.org, qemu-riscv@nongnu.org, andrei.warkentin@intel.com, shaolin.xie@alibaba-inc.com, ved@rivosinc.com, sunilvl@ventanamicro.com, haibo1.xu@intel.com, evan.chai@intel.com, yin.wang@intel.com, tech-server-platform@lists.riscv.org, tech-server-soc@lists.riscv.org, atishp@rivosinc.com, ajones@ventanamicro.com, conor@kernel.org, heinrich.schuchardt@canonical.com, marcin.juszkiewicz@linaro.org Cc: Fei Wu Subject: [RFC v2 1/2] target/riscv: Add server platform reference cpu Date: Tue, 12 Mar 2024 21:52:20 +0800 Message-Id: <20240312135222.3187945-2-fei2.wu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240312135222.3187945-1-fei2.wu@intel.com> References: <20240312135222.3187945-1-fei2.wu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.21; envelope-from=fei2.wu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.687, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1710251680433100004 Content-Type: text/plain; charset="utf-8" The harts requirements of RISC-V server platform [1] require RVA23 ISA profile support, plus Sv48, Svadu, H, Sscofmpf etc. This patch provides a virt CPU type (rvsp-ref) as compliant as possible. [1] https://github.com/riscv-non-isa/riscv-server-platform/blob/main/server= _platform_requirements.adoc Signed-off-by: Fei Wu --- target/riscv/cpu-qom.h | 1 + target/riscv/cpu.c | 61 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 62 insertions(+) diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h index 3670cfe6d9..adb934d19e 100644 --- a/target/riscv/cpu-qom.h +++ b/target/riscv/cpu-qom.h @@ -49,6 +49,7 @@ #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") #define TYPE_RISCV_CPU_THEAD_C906 RISCV_CPU_TYPE_NAME("thead-c906") #define TYPE_RISCV_CPU_VEYRON_V1 RISCV_CPU_TYPE_NAME("veyron-v1") +#define TYPE_RISCV_CPU_RVSP_REF RISCV_CPU_TYPE_NAME("rvsp-ref") #define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host") =20 OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 5a48d30828..6685fe0c01 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -2312,6 +2312,66 @@ static void rva22s64_profile_cpu_init(Object *obj) =20 RVA22S64.enabled =3D true; } + +static void rv64_rvsp_ref_cpu_init(Object *obj) +{ + CPURISCVState *env =3D &RISCV_CPU(obj)->env; + RISCVCPU *cpu =3D RISCV_CPU(obj); + + riscv_cpu_set_misa_ext(env, RVG | RVC | RVS | RVU | RVH | RVV); + + /* FIXME: change to 1.13 */ + env->priv_ver =3D PRIV_VERSION_1_12_0; + + /* RVA22S64 */ + cpu->cfg.mmu =3D true; + cpu->cfg.ext_zifencei =3D true; + cpu->cfg.ext_zicsr =3D true; + cpu->cfg.ext_zicntr =3D true; + cpu->cfg.ext_zihpm =3D true; + cpu->cfg.ext_zihintpause =3D true; + cpu->cfg.ext_zba =3D true; + cpu->cfg.ext_zbb =3D true; + cpu->cfg.ext_zbs =3D true; + cpu->cfg.ext_zic64b =3D true; + cpu->cfg.ext_zicbom =3D true; + cpu->cfg.ext_zicbop =3D true; + cpu->cfg.ext_zicboz =3D true; + cpu->cfg.cbom_blocksize =3D 64; + cpu->cfg.cbop_blocksize =3D 64; + cpu->cfg.cboz_blocksize =3D 64; + cpu->cfg.ext_zfhmin =3D true; + cpu->cfg.ext_zkt =3D true; + cpu->cfg.ext_svade =3D true; + cpu->cfg.ext_svpbmt =3D true; + cpu->cfg.ext_svinval =3D true; + + /* RVA23U64 */ + cpu->cfg.ext_zvfhmin =3D true; + cpu->cfg.ext_zvbb =3D true; + cpu->cfg.ext_zvkt =3D true; + cpu->cfg.ext_zihintntl =3D true; + cpu->cfg.ext_zicond =3D true; + cpu->cfg.ext_zcb =3D true; + cpu->cfg.ext_zfa =3D true; + cpu->cfg.ext_zawrs =3D true; + + /* RVA23S64 */ + cpu->cfg.ext_svnapot =3D true; + cpu->cfg.ext_sstc =3D true; + cpu->cfg.ext_sscofpmf =3D true; + cpu->cfg.ext_smstateen =3D true; + + cpu->cfg.ext_smaia =3D true; + cpu->cfg.ext_ssaia =3D true; + + /* Server Platform */ +#ifndef CONFIG_USER_ONLY + set_satp_mode_max_supported(cpu, VM_1_10_SV48); +#endif + cpu->cfg.ext_svadu =3D true; + cpu->cfg.ext_zkr =3D true; +} #endif =20 static const gchar *riscv_gdb_arch_name(CPUState *cs) @@ -2577,6 +2637,7 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV64E, MXL_RV64, rv64e_bare_cpu= _init), DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22U64, MXL_RV64, rva22u64_profi= le_cpu_init), DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22S64, MXL_RV64, rva22s64_profi= le_cpu_init), + DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_RVSP_REF, MXL_RV64, rv64_rvsp_ref_= cpu_init), #endif }; =20 --=20 2.34.1