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Tue, 12 Mar 2024 01:22:49 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, qemu-arm@nongnu.org, qemu-block@nongnu.org, BALATON Zoltan , Markus Armbruster , Thomas Huth , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , John Snow Subject: [PULL 01/13] hw/ide/ahci: Rename ahci_internal.h to ahci-internal.h Date: Tue, 12 Mar 2024 09:22:26 +0100 Message-ID: <20240312082239.69696-2-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240312082239.69696-1-philmd@linaro.org> References: <20240312082239.69696-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=philmd@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1710231883193100009 From: BALATON Zoltan Other headers now use dash instead of underscore. Rename ahci_internal.h accordingly for consistency. Signed-off-by: BALATON Zoltan Reviewed-by: Markus Armbruster Reviewed-by: Thomas Huth Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-ID: <20240227131310.C24EB4E6005@zero.eik.bme.hu> Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/ide/{ahci_internal.h =3D> ahci-internal.h} | 0 hw/ide/ahci.c | 2 +- hw/ide/ich.c | 2 +- 3 files changed, 2 insertions(+), 2 deletions(-) rename hw/ide/{ahci_internal.h =3D> ahci-internal.h} (100%) diff --git a/hw/ide/ahci_internal.h b/hw/ide/ahci-internal.h similarity index 100% rename from hw/ide/ahci_internal.h rename to hw/ide/ahci-internal.h diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c index b8123bc73d..bfefad2965 100644 --- a/hw/ide/ahci.c +++ b/hw/ide/ahci.c @@ -37,7 +37,7 @@ #include "hw/ide/pci.h" #include "hw/ide/ahci-pci.h" #include "hw/ide/ahci-sysbus.h" -#include "ahci_internal.h" +#include "ahci-internal.h" #include "ide-internal.h" =20 #include "trace.h" diff --git a/hw/ide/ich.c b/hw/ide/ich.c index 3ea793d790..9b909c87f3 100644 --- a/hw/ide/ich.c +++ b/hw/ide/ich.c @@ -70,7 +70,7 @@ #include "sysemu/dma.h" #include "hw/ide/pci.h" #include "hw/ide/ahci-pci.h" -#include "ahci_internal.h" +#include "ahci-internal.h" =20 #define ICH9_MSI_CAP_OFFSET 0x80 #define ICH9_SATA_CAP_OFFSET 0xA8 --=20 2.41.0 From nobody Mon May 13 04:56:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Tue, 12 Mar 2024 01:22:55 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, qemu-arm@nongnu.org, qemu-block@nongnu.org, Vladimir Sementsov-Ogievskiy , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" , Marcel Apfelbaum Subject: [PULL 02/13] hw/pci: add some convenient trace-events for pcie and shpc hotplug Date: Tue, 12 Mar 2024 09:22:27 +0100 Message-ID: <20240312082239.69696-3-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240312082239.69696-1-philmd@linaro.org> References: <20240312082239.69696-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=philmd@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1710231883031100004 From: Vladimir Sementsov-Ogievskiy Add trace-events that may help to debug problems with hotplugging. Signed-off-by: Vladimir Sementsov-Ogievskiy Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-ID: <20240301154146.761531-2-vsementsov@yandex-team.ru> Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/pci/pcie.c | 56 +++++++++++++++++++++++++++++++++++++++++++++ hw/pci/shpc.c | 46 +++++++++++++++++++++++++++++++++++++ hw/pci/trace-events | 6 +++++ 3 files changed, 108 insertions(+) diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c index 6db0cf69cd..f56079acf5 100644 --- a/hw/pci/pcie.c +++ b/hw/pci/pcie.c @@ -28,6 +28,7 @@ #include "hw/pci/pcie_regs.h" #include "hw/pci/pcie_port.h" #include "qemu/range.h" +#include "trace.h" =20 //#define DEBUG_PCIE #ifdef DEBUG_PCIE @@ -45,6 +46,23 @@ static bool pcie_sltctl_powered_off(uint16_t sltctl) && (sltctl & PCI_EXP_SLTCTL_PIC) =3D=3D PCI_EXP_SLTCTL_PWR_IND_OFF; } =20 +static const char *pcie_led_state_to_str(uint16_t value) +{ + switch (value) { + case PCI_EXP_SLTCTL_PWR_IND_ON: + case PCI_EXP_SLTCTL_ATTN_IND_ON: + return "on"; + case PCI_EXP_SLTCTL_PWR_IND_BLINK: + case PCI_EXP_SLTCTL_ATTN_IND_BLINK: + return "blink"; + case PCI_EXP_SLTCTL_PWR_IND_OFF: + case PCI_EXP_SLTCTL_ATTN_IND_OFF: + return "off"; + default: + return "invalid"; + } +} + /*************************************************************************= ** * pci express capability helper functions */ @@ -735,6 +753,28 @@ void pcie_cap_slot_get(PCIDevice *dev, uint16_t *slt_c= tl, uint16_t *slt_sta) *slt_sta =3D pci_get_word(exp_cap + PCI_EXP_SLTSTA); } =20 +static void find_child_fn(PCIBus *bus, PCIDevice *dev, void *opaque) +{ + PCIDevice **child =3D opaque; + + if (!*child) { + *child =3D dev; + } +} + +/* + * Returns the plugged device or first function of multifunction plugged d= evice + */ +static PCIDevice *pcie_cap_slot_find_child(PCIDevice *dev) +{ + PCIBus *sec_bus =3D pci_bridge_get_sec_bus(PCI_BRIDGE(dev)); + PCIDevice *child =3D NULL; + + pci_for_each_device(sec_bus, pci_bus_num(sec_bus), find_child_fn, &chi= ld); + + return child; +} + void pcie_cap_slot_write_config(PCIDevice *dev, uint16_t old_slt_ctl, uint16_t old_slt_sta, uint32_t addr, uint32_t val, int len) @@ -779,6 +819,22 @@ void pcie_cap_slot_write_config(PCIDevice *dev, sltsta); } =20 + if (trace_event_get_state_backends(TRACE_PCIE_CAP_SLOT_WRITE_CONFIG)) { + DeviceState *parent =3D DEVICE(dev); + DeviceState *child =3D DEVICE(pcie_cap_slot_find_child(dev)); + + trace_pcie_cap_slot_write_config( + parent->canonical_path, + child ? child->canonical_path : "no-child", + (sltsta & PCI_EXP_SLTSTA_PDS) ? "present" : "not present", + pcie_led_state_to_str(old_slt_ctl & PCI_EXP_SLTCTL_PIC), + pcie_led_state_to_str(val & PCI_EXP_SLTCTL_PIC), + pcie_led_state_to_str(old_slt_ctl & PCI_EXP_SLTCTL_AIC), + pcie_led_state_to_str(val & PCI_EXP_SLTCTL_AIC), + (old_slt_ctl & PCI_EXP_SLTCTL_PWR_OFF) ? "off" : "on", + (val & PCI_EXP_SLTCTL_PWR_OFF) ? "off" : "on"); + } + /* * If the slot is populated, power indicator is off and power * controller is off, it is safe to detach the devices. diff --git a/hw/pci/shpc.c b/hw/pci/shpc.c index d2a5eea69e..aac6f2d034 100644 --- a/hw/pci/shpc.c +++ b/hw/pci/shpc.c @@ -8,6 +8,7 @@ #include "hw/pci/pci.h" #include "hw/pci/pci_bus.h" #include "hw/pci/msi.h" +#include "trace.h" =20 /* TODO: model power only and disabled slot states. */ /* TODO: handle SERR and wakeups */ @@ -123,6 +124,34 @@ #define SHPC_PCI_TO_IDX(pci_slot) ((pci_slot) - 1) #define SHPC_IDX_TO_PHYSICAL(slot) ((slot) + 1) =20 +static const char *shpc_led_state_to_str(uint8_t value) +{ + switch (value) { + case SHPC_LED_ON: + return "on"; + case SHPC_LED_BLINK: + return "blink"; + case SHPC_LED_OFF: + return "off"; + default: + return "invalid"; + } +} + +static const char *shpc_slot_state_to_str(uint8_t value) +{ + switch (value) { + case SHPC_STATE_PWRONLY: + return "power-only"; + case SHPC_STATE_ENABLED: + return "enabled"; + case SHPC_STATE_DISABLED: + return "disabled"; + default: + return "invalid"; + } +} + static uint8_t shpc_get_status(SHPCDevice *shpc, int slot, uint16_t msk) { uint8_t *status =3D shpc->config + SHPC_SLOT_STATUS(slot); @@ -302,6 +331,23 @@ static void shpc_slot_command(PCIDevice *d, uint8_t ta= rget, shpc_set_status(shpc, slot, state, SHPC_SLOT_STATE_MASK); } =20 + if (trace_event_get_state_backends(TRACE_SHPC_SLOT_COMMAND)) { + DeviceState *parent =3D DEVICE(d); + int pci_slot =3D SHPC_IDX_TO_PCI(slot); + DeviceState *child =3D + DEVICE(shpc->sec_bus->devices[PCI_DEVFN(pci_slot, 0)]); + + trace_shpc_slot_command( + parent->canonical_path, pci_slot, + child ? child->canonical_path : "no-child", + shpc_led_state_to_str(old_power), + shpc_led_state_to_str(power), + shpc_led_state_to_str(old_attn), + shpc_led_state_to_str(attn), + shpc_slot_state_to_str(old_state), + shpc_slot_state_to_str(state)); + } + if (!shpc_slot_is_off(old_state, old_power, old_attn) && shpc_slot_is_off(state, power, attn)) { diff --git a/hw/pci/trace-events b/hw/pci/trace-events index 42430869ce..19643aa8c6 100644 --- a/hw/pci/trace-events +++ b/hw/pci/trace-events @@ -16,3 +16,9 @@ msix_write_config(char *name, bool enabled, bool masked) = "dev %s enabled %d mask sriov_register_vfs(const char *name, int slot, int function, int num_vfs) = "%s %02x:%x: creating %d vf devs" sriov_unregister_vfs(const char *name, int slot, int function, int num_vfs= ) "%s %02x:%x: Unregistering %d vf devs" sriov_config_write(const char *name, int slot, int fun, uint32_t offset, u= int32_t val, uint32_t len) "%s %02x:%x: sriov offset 0x%x val 0x%x len %d" + +# pcie.c +pcie_cap_slot_write_config(const char *parent, const char *child, const ch= ar *pds, const char *old_pic, const char *new_pic, const char *old_aic, con= st char *new_aic, const char *old_power, const char *new_power) "%s > %s: p= ds: %s, pic: %s->%s, aic: %s->%s, power: %s->%s" + +# shpc.c +shpc_slot_command(const char *parent, int pci_slot, const char *child, con= st char *old_pic, const char *new_pic, const char *old_aic, const char *new= _aic, const char *old_state, const char *new_state) "%s[%d] > %s: pic: %s->= %s, aic: %s->%s, state: %s->%s" --=20 2.41.0 From nobody Mon May 13 04:56:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Tue, 12 Mar 2024 01:23:01 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, qemu-arm@nongnu.org, qemu-block@nongnu.org, BALATON Zoltan , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 03/13] hw/ppc/sam460ex: Support short options for adding drives Date: Tue, 12 Mar 2024 09:22:28 +0100 Message-ID: <20240312082239.69696-4-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240312082239.69696-1-philmd@linaro.org> References: <20240312082239.69696-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::133; envelope-from=philmd@linaro.org; helo=mail-lf1-x133.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1710231883239100011 From: BALATON Zoltan Having to use -drive if=3Dnone,... and -device ide-[cd,hd] is inconvenient. Add support for shorter convenience options such as -cdrom and -drive media=3Ddisk. Also adjust two nearby comments for code style. Signed-off-by: BALATON Zoltan Message-ID: <20240305225721.E9A404E6005@zero.eik.bme.hu> Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/ppc/sam460ex.c | 24 +++++++++++++++++++----- 1 file changed, 19 insertions(+), 5 deletions(-) diff --git a/hw/ppc/sam460ex.c b/hw/ppc/sam460ex.c index 7e34b6c5e0..d42b677898 100644 --- a/hw/ppc/sam460ex.c +++ b/hw/ppc/sam460ex.c @@ -33,6 +33,7 @@ #include "hw/char/serial.h" #include "hw/i2c/ppc4xx_i2c.h" #include "hw/i2c/smbus_eeprom.h" +#include "hw/ide/pci.h" #include "hw/usb/hcd-ehci.h" #include "hw/ppc/fdt.h" #include "hw/qdev-properties.h" @@ -449,15 +450,27 @@ static void sam460ex_init(MachineState *machine) =20 /* PCI devices */ pci_create_simple(pci_bus, PCI_DEVFN(6, 0), "sm501"); - /* SoC has a single SATA port but we don't emulate that yet + /* + * SoC has a single SATA port but we don't emulate that * However, firmware and usual clients have driver for SiI311x - * so add one for convenience by default */ + * PCI SATA card so add one for convenience by default + */ if (defaults_enabled()) { - pci_create_simple(pci_bus, -1, "sii3112"); + PCIIDEState *s =3D PCI_IDE(pci_create_simple(pci_bus, -1, "sii3112= ")); + DriveInfo *di; + + di =3D drive_get_by_index(IF_IDE, 0); + if (di) { + ide_bus_create_drive(&s->bus[0], 0, di); + } + /* Use index 2 only if 1 does not exist, this allows -cdrom */ + di =3D drive_get_by_index(IF_IDE, 1) ?: drive_get_by_index(IF_IDE,= 2); + if (di) { + ide_bus_create_drive(&s->bus[1], 0, di); + } } =20 - /* SoC has 4 UARTs - * but board has only one wired and two are present in fdt */ + /* SoC has 4 UARTs but board has only one wired and two described in f= dt */ if (serial_hd(0) !=3D NULL) { serial_mm_init(get_system_memory(), 0x4ef600300, 0, qdev_get_gpio_in(uic[1], 1), @@ -531,6 +544,7 @@ static void sam460ex_machine_init(MachineClass *mc) { mc->desc =3D "aCube Sam460ex"; mc->init =3D sam460ex_init; + mc->block_default_type =3D IF_IDE; mc->default_cpu_type =3D POWERPC_CPU_TYPE_NAME("460exb"); mc->default_ram_size =3D 512 * MiB; mc->default_ram_id =3D "ppc4xx.sdram"; --=20 2.41.0 From nobody Mon May 13 04:56:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Tue, 12 Mar 2024 01:23:07 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, qemu-arm@nongnu.org, qemu-block@nongnu.org, Zhao Liu , Paul Burton , Aleksandar Rikalo , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 04/13] hw/core/loader-fit: Fix missing ERRP_GUARD() for error_prepend() Date: Tue, 12 Mar 2024 09:22:29 +0100 Message-ID: <20240312082239.69696-5-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240312082239.69696-1-philmd@linaro.org> References: <20240312082239.69696-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=philmd@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1710231883015100003 From: Zhao Liu As the comment in qapi/error, passing @errp to error_prepend() requires ERRP_GUARD(): * =3D Why, when and how to use ERRP_GUARD() =3D * * Without ERRP_GUARD(), use of the @errp parameter is restricted: ... * - It should not be passed to error_prepend(), error_vprepend() or * error_append_hint(), because that doesn't work with &error_fatal. * ERRP_GUARD() lifts these restrictions. * * To use ERRP_GUARD(), add it right at the beginning of the function. * @errp can then be used without worrying about the argument being * NULL or &error_fatal. ERRP_GUARD() could avoid the case when @errp is &error_fatal, the user can't see this additional information, because exit() happens in error_setg earlier than information is added [1]. In hw/core/loader-fit.c, there are 2 functions passing @errp to error_prepend() without ERRP_GUARD(): - fit_load_kernel() - fit_load_fdt() Their @errp parameters are both the pointers of the local @err virable in load_fit(). Though they don't cause the issue like [1] said, to follow the requirement of @errp, add missing ERRP_GUARD() at their beginning. [1]: Issue description in the commit message of commit ae7c80a7bd73 ("error: New macro ERRP_GUARD()"). Cc: Paul Burton Cc: Aleksandar Rikalo Signed-off-by: Zhao Liu Message-ID: <20240311033822.3142585-15-zhao1.liu@linux.intel.com> Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/core/loader-fit.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/core/loader-fit.c b/hw/core/loader-fit.c index b7c7b3ba94..9f20007dbb 100644 --- a/hw/core/loader-fit.c +++ b/hw/core/loader-fit.c @@ -120,6 +120,7 @@ static int fit_load_kernel(const struct fit_loader *ldr= , const void *itb, int cfg, void *opaque, hwaddr *pend, Error **errp) { + ERRP_GUARD(); const char *name; const void *data; const void *load_data; @@ -178,6 +179,7 @@ static int fit_load_fdt(const struct fit_loader *ldr, c= onst void *itb, int cfg, void *opaque, const void *match_data, hwaddr kernel_end, Error **errp) { + ERRP_GUARD(); Error *err =3D NULL; const char *name; const void *data; --=20 2.41.0 From nobody Mon May 13 04:56:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=philmd@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1710231883011100002 From: Zhao Liu As the comment in qapi/error, passing @errp to error_prepend() requires ERRP_GUARD(): * =3D Why, when and how to use ERRP_GUARD() =3D * * Without ERRP_GUARD(), use of the @errp parameter is restricted: ... * - It should not be passed to error_prepend(), error_vprepend() or * error_append_hint(), because that doesn't work with &error_fatal. * ERRP_GUARD() lifts these restrictions. * * To use ERRP_GUARD(), add it right at the beginning of the function. * @errp can then be used without worrying about the argument being * NULL or &error_fatal. ERRP_GUARD() could avoid the case when @errp is &error_fatal, the user can't see this additional information, because exit() happens in error_setg earlier than information is added [1]. The set_chr() passes @errp to error_prepend() without ERRP_GUARD(). As a PropertyInfo.set method, there are too many possible callers to check the impact of this defect; it may or may not be harmless. Thus it is necessary to protect @errp with ERRP_GUARD(). To avoid the issue like [1] said, add missing ERRP_GUARD() at the beginning of this function. [1]: Issue description in the commit message of commit ae7c80a7bd73 ("error: New macro ERRP_GUARD()"). Cc: Paolo Bonzini Cc: "Daniel P. Berrang=C3=A9" Signed-off-by: Zhao Liu Reviewed-by: Markus Armbruster Message-ID: <20240311033822.3142585-16-zhao1.liu@linux.intel.com> Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/core/qdev-properties-system.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/core/qdev-properties-system.c b/hw/core/qdev-properties-sys= tem.c index b45e90edb2..00c968f4f5 100644 --- a/hw/core/qdev-properties-system.c +++ b/hw/core/qdev-properties-system.c @@ -242,6 +242,7 @@ static void get_chr(Object *obj, Visitor *v, const char= *name, void *opaque, static void set_chr(Object *obj, Visitor *v, const char *name, void *opaqu= e, Error **errp) { + ERRP_GUARD(); Property *prop =3D opaque; CharBackend *be =3D object_field_prop_ptr(obj, prop); Chardev *s; --=20 2.41.0 From nobody Mon May 13 04:56:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=philmd@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1710231967290100001 From: Zhao Liu As the comment in qapi/error, passing @errp to error_prepend() requires ERRP_GUARD(): * =3D Why, when and how to use ERRP_GUARD() =3D * * Without ERRP_GUARD(), use of the @errp parameter is restricted: ... * - It should not be passed to error_prepend(), error_vprepend() or * error_append_hint(), because that doesn't work with &error_fatal. * ERRP_GUARD() lifts these restrictions. * * To use ERRP_GUARD(), add it right at the beginning of the function. * @errp can then be used without worrying about the argument being * NULL or &error_fatal. ERRP_GUARD() could avoid the case when @errp is &error_fatal, the user can't see this additional information, because exit() happens in error_setg earlier than information is added [1]. The ivshmem_common_realize() passes @errp to error_prepend(), and as a DeviceClass.realize method, there are too many possible callers to check the impact of this defect; it may or may not be harmless. Thus it is necessary to protect @errp with ERRP_GUARD(). To avoid the issue like [1] said, add missing ERRP_GUARD() at the beginning of this function. [1]: Issue description in the commit message of commit ae7c80a7bd73 ("error: New macro ERRP_GUARD()"). Cc: Juan Quintela Cc: Manos Pitsidianakis Cc: Michael Galaxy Cc: Steve Sistare Signed-off-by: Zhao Liu Message-ID: <20240311033822.3142585-17-zhao1.liu@linux.intel.com> Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/misc/ivshmem.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/misc/ivshmem.c b/hw/misc/ivshmem.c index a2fd0bc365..de49d1b8a8 100644 --- a/hw/misc/ivshmem.c +++ b/hw/misc/ivshmem.c @@ -832,6 +832,7 @@ static void ivshmem_write_config(PCIDevice *pdev, uint3= 2_t address, =20 static void ivshmem_common_realize(PCIDevice *dev, Error **errp) { + ERRP_GUARD(); IVShmemState *s =3D IVSHMEM_COMMON(dev); Error *err =3D NULL; uint8_t *pci_conf; --=20 2.41.0 From nobody Mon May 13 04:56:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=philmd@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1710231933151100002 From: Mark Cave-Ayland During kernel startup OpenBSD accesses addresses mapped by BAR0 of the ebus= device but at offsets where no IO devices exist. Before commit 4aa07e8649 ("hw/spa= rc64/ebus: Access memory regions via pci_address_space_io()") BAR0 was mapped to legac= y IO space which allows accesses to unmapped devices to succeed, but afterwards = these accesses to unmapped PCI IO space cause a memory fault which prevents OpenB= SD from booting. Since no devices are mapped at the addresses accessed by OpenBSD, change eb= us BAR0 from a PCI IO space alias to an IO memory region using unassigned_io_ops wh= ich allows these accesses to succeed and so allows OpenBSD to boot once again. Fixes: 4aa07e8649 ("hw/sparc64/ebus: Access memory regions via pci_address_= space_io()") Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-ID: <20240311064345.2531197-1-mark.cave-ayland@ilande.co.uk> Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/sparc64/sun4u.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/hw/sparc64/sun4u.c b/hw/sparc64/sun4u.c index eda9b58a21..cff6d5abaf 100644 --- a/hw/sparc64/sun4u.c +++ b/hw/sparc64/sun4u.c @@ -360,8 +360,13 @@ static void ebus_realize(PCIDevice *pci_dev, Error **e= rrp) pci_dev->config[0x09] =3D 0x00; // programming i/f pci_dev->config[0x0D] =3D 0x0a; // latency_timer =20 - memory_region_init_alias(&s->bar0, OBJECT(s), "bar0", - pci_address_space_io(pci_dev), 0, 0x1000000); + /* + * BAR0 is accessed by OpenBSD but not for ebus device access: allow a= ny + * memory access to this region to succeed which allows the OpenBSD ke= rnel + * to boot. + */ + memory_region_init_io(&s->bar0, OBJECT(s), &unassigned_io_ops, s, + "bar0", 0x1000000); pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar0); memory_region_init_alias(&s->bar1, OBJECT(s), "bar1", pci_address_space_io(pci_dev), 0, 0x8000); --=20 2.41.0 From nobody Mon May 13 04:56:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1710231931; cv=none; d=zohomail.com; s=zohoarc; b=FBNTkjT2ihe2m8D4F2OgVLgqL/7meDNB7fiZ4Srewl2jfVkYoxSjAauTfCMEbJZrdtYOAjGzNBsekDcsNKllEoRwIqW1tPCEr8jKOp0GWFFl79uoRR0PuqCFv2yjTX9maIY7J5TGUqh5Lg995TIJE1r+2+kY40j4OSSpB+JTQus= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1710231931; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Tue, 12 Mar 2024 01:23:33 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, qemu-arm@nongnu.org, qemu-block@nongnu.org, Zhao Liu , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Eduardo Habkost , Marcel Apfelbaum , Yanan Wang Subject: [PULL 08/13] hw/core: Cleanup unused included headers in cpu-common.c Date: Tue, 12 Mar 2024 09:22:33 +0100 Message-ID: <20240312082239.69696-9-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240312082239.69696-1-philmd@linaro.org> References: <20240312082239.69696-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=philmd@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1710231933142100001 From: Zhao Liu Remove unused headers in cpu-common.c: * qemu/notify.h * exec/cpu-common.h * qemu/error-report.h * qemu/qemu-print.h Tested by "./configure" and then "make". Signed-off-by: Zhao Liu Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-ID: <20240311075621.3224684-2-zhao1.liu@linux.intel.com> Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/core/cpu-common.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c index 0108fb11db..4bd9c70a83 100644 --- a/hw/core/cpu-common.c +++ b/hw/core/cpu-common.c @@ -22,14 +22,10 @@ #include "qapi/error.h" #include "hw/core/cpu.h" #include "sysemu/hw_accel.h" -#include "qemu/notify.h" #include "qemu/log.h" #include "qemu/main-loop.h" #include "exec/log.h" -#include "exec/cpu-common.h" #include "exec/gdbstub.h" -#include "qemu/error-report.h" -#include "qemu/qemu-print.h" #include "sysemu/tcg.h" #include "hw/boards.h" #include "hw/qdev-properties.h" --=20 2.41.0 From nobody Mon May 13 04:56:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=philmd@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1710231883009100001 From: Zhao Liu Remove unused header (qemu/main-loop.h) in machine-qmp-cmds.c. Tested by "./configure" and then "make". Signed-off-by: Zhao Liu Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-ID: <20240311075621.3224684-3-zhao1.liu@linux.intel.com> Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/core/machine-qmp-cmds.c | 1 - 1 file changed, 1 deletion(-) diff --git a/hw/core/machine-qmp-cmds.c b/hw/core/machine-qmp-cmds.c index 3860a50c3b..4b72009cd3 100644 --- a/hw/core/machine-qmp-cmds.c +++ b/hw/core/machine-qmp-cmds.c @@ -19,7 +19,6 @@ #include "qapi/qmp/qobject.h" #include "qapi/qobject-input-visitor.h" #include "qapi/type-helpers.h" -#include "qemu/main-loop.h" #include "qemu/uuid.h" #include "qom/qom-qobject.h" #include "sysemu/hostmem.h" --=20 2.41.0 From nobody Mon May 13 04:56:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=philmd@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1710231895041100003 From: Zhao Liu Remove unused header in numa.c: * qemu/bitmap.h * migration/vmstate.h Note: Though parse_numa_hmat_lb() has the variable named "bitmap_copy", it doesn't use the normal bitmap ops so that it's safe to exclude qemu/bitmap.h header. Tested by "./configure" and then "make". Signed-off-by: Zhao Liu Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-ID: <20240311075621.3224684-4-zhao1.liu@linux.intel.com> Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/core/numa.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/hw/core/numa.c b/hw/core/numa.c index f08956ddb0..81d2124349 100644 --- a/hw/core/numa.c +++ b/hw/core/numa.c @@ -28,7 +28,6 @@ #include "sysemu/numa.h" #include "exec/cpu-common.h" #include "exec/ramlist.h" -#include "qemu/bitmap.h" #include "qemu/error-report.h" #include "qapi/error.h" #include "qapi/opts-visitor.h" @@ -36,7 +35,6 @@ #include "sysemu/qtest.h" #include "hw/core/cpu.h" #include "hw/mem/pc-dimm.h" -#include "migration/vmstate.h" #include "hw/boards.h" #include "hw/mem/memory-device.h" #include "qemu/option.h" --=20 2.41.0 From nobody Mon May 13 04:56:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=philmd@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1710231987308100002 From: Dmitriy Sharikhin NXP PCF8574 and compatible ICs are simple I2C GPIO expanders. PCF8574 incorporates quasi-bidirectional IO, and simple communication protocol, when IO read is I2C byte read, and IO write is I2C byte write. User can think of it as open-drain port, when line high state is input and line low state is output. Signed-off-by: Dmitrii Sharikhin Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-ID: Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- MAINTAINERS | 6 ++ include/hw/gpio/pcf8574.h | 15 ++++ hw/gpio/pcf8574.c | 162 ++++++++++++++++++++++++++++++++++++++ hw/gpio/Kconfig | 4 + hw/gpio/meson.build | 1 + 5 files changed, 188 insertions(+) create mode 100644 include/hw/gpio/pcf8574.h create mode 100644 hw/gpio/pcf8574.c diff --git a/MAINTAINERS b/MAINTAINERS index 4d96f855de..72c23e3682 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2503,6 +2503,12 @@ S: Maintained F: hw/i2c/i2c_mux_pca954x.c F: include/hw/i2c/i2c_mux_pca954x.h =20 +pcf8574 +M: Dmitrii Sharikhin +S: Maintained +F: hw/gpio/pcf8574.c +F: include/gpio/pcf8574.h + Generic Loader M: Alistair Francis S: Maintained diff --git a/include/hw/gpio/pcf8574.h b/include/hw/gpio/pcf8574.h new file mode 100644 index 0000000000..3291d7dbbc --- /dev/null +++ b/include/hw/gpio/pcf8574.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * NXP PCF8574 8-port I2C GPIO expansion chip. + * + * Copyright (c) 2024 KNS Group (YADRO). + * Written by Dmitrii Sharikhin + */ + +#ifndef _HW_GPIO_PCF8574 +#define _HW_GPIO_PCF8574 + +#define TYPE_PCF8574 "pcf8574" + +#endif /* _HW_GPIO_PCF8574 */ diff --git a/hw/gpio/pcf8574.c b/hw/gpio/pcf8574.c new file mode 100644 index 0000000000..d37909e2ad --- /dev/null +++ b/hw/gpio/pcf8574.c @@ -0,0 +1,162 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * NXP PCF8574 8-port I2C GPIO expansion chip. + * Copyright (c) 2024 KNS Group (YADRO). + * Written by Dmitrii Sharikhin + */ + +#include "qemu/osdep.h" +#include "hw/i2c/i2c.h" +#include "hw/gpio/pcf8574.h" +#include "hw/irq.h" +#include "migration/vmstate.h" +#include "qemu/log.h" +#include "qemu/module.h" +#include "qom/object.h" + +/* + * PCF8574 and compatible chips incorporate quasi-bidirectional + * IO. Electrically it means that device sustain pull-up to line + * unless IO port is configured as output _and_ driven low. + * + * IO access is implemented as simple I2C single-byte read + * or write operation. So, to configure line to input user write 1 + * to corresponding bit. To configure line to output and drive it low + * user write 0 to corresponding bit. + * + * In essence, user can think of quasi-bidirectional IO as + * open-drain line, except presence of builtin rising edge acceleration + * embedded in PCF8574 IC + * + * PCF8574 has interrupt request line, which is being pulled down when + * port line state differs from last read. Port read operation clears + * state and INT line returns to high state via pullup. + */ + +OBJECT_DECLARE_SIMPLE_TYPE(PCF8574State, PCF8574) + +#define PORTS_COUNT (8) + +struct PCF8574State { + I2CSlave parent_obj; + uint8_t lastrq; /* Last requested state. If changed - assert irq = */ + uint8_t input; /* external electrical line state */ + uint8_t output; /* Pull-up (1) or drive low (0) on bit */ + qemu_irq handler[PORTS_COUNT]; + qemu_irq intrq; /* External irq request */ +}; + +static void pcf8574_reset(DeviceState *dev) +{ + PCF8574State *s =3D PCF8574(dev); + s->lastrq =3D MAKE_64BIT_MASK(0, PORTS_COUNT); + s->input =3D MAKE_64BIT_MASK(0, PORTS_COUNT); + s->output =3D MAKE_64BIT_MASK(0, PORTS_COUNT); +} + +static inline uint8_t pcf8574_line_state(PCF8574State *s) +{ + /* we driving line low or external circuit does that */ + return s->input & s->output; +} + +static uint8_t pcf8574_rx(I2CSlave *i2c) +{ + PCF8574State *s =3D PCF8574(i2c); + uint8_t linestate =3D pcf8574_line_state(s); + if (s->lastrq !=3D linestate) { + s->lastrq =3D linestate; + if (s->intrq) { + qemu_set_irq(s->intrq, 1); + } + } + return linestate; +} + +static int pcf8574_tx(I2CSlave *i2c, uint8_t data) +{ + PCF8574State *s =3D PCF8574(i2c); + uint8_t prev; + uint8_t diff; + uint8_t actual; + int line =3D 0; + + prev =3D pcf8574_line_state(s); + s->output =3D data; + actual =3D pcf8574_line_state(s); + + for (diff =3D (actual ^ prev); diff; diff &=3D ~(1 << line)) { + line =3D ctz32(diff); + if (s->handler[line]) { + qemu_set_irq(s->handler[line], (actual >> line) & 1); + } + } + + if (s->intrq) { + qemu_set_irq(s->intrq, actual =3D=3D s->lastrq); + } + + return 0; +} + +static const VMStateDescription vmstate_pcf8574 =3D { + .name =3D "pcf8574", + .version_id =3D 0, + .minimum_version_id =3D 0, + .fields =3D (VMStateField[]) { + VMSTATE_I2C_SLAVE(parent_obj, PCF8574State), + VMSTATE_UINT8(lastrq, PCF8574State), + VMSTATE_UINT8(input, PCF8574State), + VMSTATE_UINT8(output, PCF8574State), + VMSTATE_END_OF_LIST() + } +}; + +static void pcf8574_gpio_set(void *opaque, int line, int level) +{ + PCF8574State *s =3D (PCF8574State *) opaque; + assert(line >=3D 0 && line < ARRAY_SIZE(s->handler)); + + if (level) { + s->input |=3D (1 << line); + } else { + s->input &=3D ~(1 << line); + } + + if (pcf8574_line_state(s) !=3D s->lastrq && s->intrq) { + qemu_set_irq(s->intrq, 0); + } +} + +static void pcf8574_realize(DeviceState *dev, Error **errp) +{ + PCF8574State *s =3D PCF8574(dev); + + qdev_init_gpio_in(dev, pcf8574_gpio_set, ARRAY_SIZE(s->handler)); + qdev_init_gpio_out(dev, s->handler, ARRAY_SIZE(s->handler)); + qdev_init_gpio_out_named(dev, &s->intrq, "nINT", 1); +} + +static void pcf8574_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + I2CSlaveClass *k =3D I2C_SLAVE_CLASS(klass); + + k->recv =3D pcf8574_rx; + k->send =3D pcf8574_tx; + dc->realize =3D pcf8574_realize; + dc->reset =3D pcf8574_reset; + dc->vmsd =3D &vmstate_pcf8574; +} + +static const TypeInfo pcf8574_infos[] =3D { + { + .name =3D TYPE_PCF8574, + .parent =3D TYPE_I2C_SLAVE, + .instance_size =3D sizeof(PCF8574State), + .class_init =3D pcf8574_class_init, + } +}; + +DEFINE_TYPES(pcf8574_infos); diff --git a/hw/gpio/Kconfig b/hw/gpio/Kconfig index 712940b8e0..19c97cc823 100644 --- a/hw/gpio/Kconfig +++ b/hw/gpio/Kconfig @@ -19,3 +19,7 @@ config SIFIVE_GPIO =20 config STM32L4X5_GPIO bool + +config PCF8574 + bool + depends on I2C diff --git a/hw/gpio/meson.build b/hw/gpio/meson.build index 3454b503ae..791e93a97b 100644 --- a/hw/gpio/meson.build +++ b/hw/gpio/meson.build @@ -16,3 +16,4 @@ system_ss.add(when: 'CONFIG_RASPI', if_true: files( system_ss.add(when: 'CONFIG_STM32L4X5_SOC', if_true: files('stm32l4x5_gpio= .c')) system_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_gpio.c')) system_ss.add(when: 'CONFIG_SIFIVE_GPIO', if_true: files('sifive_gpio.c')) +system_ss.add(when: 'CONFIG_PCF8574', if_true: files('pcf8574.c')) --=20 2.41.0 From nobody Mon May 13 04:56:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Tue, 12 Mar 2024 01:23:59 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, qemu-arm@nongnu.org, qemu-block@nongnu.org, Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Paolo Bonzini , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Thomas Huth Subject: [PULL 12/13] meson.build: Always require an objc compiler on macos hosts Date: Tue, 12 Mar 2024 09:22:37 +0100 Message-ID: <20240312082239.69696-13-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240312082239.69696-1-philmd@linaro.org> References: <20240312082239.69696-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::12e; envelope-from=philmd@linaro.org; helo=mail-lf1-x12e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1710231987304100001 From: Peter Maydell We currently only insist that an ObjectiveC compiler is present on macos hosts if we're building the Cocoa UI. However, since then we've added some other parts of QEMU which are also written in ObjC: the coreaudio audio backend, and the vmnet net backend. This means that if you try to configure QEMU on macos with --disable-cocoa the build will fail: ../meson.build:3741:13: ERROR: No host machine compiler for 'audio/coreaudi= o.m' Since in practice any macos host will have an ObjC compiler available, rather than trying to gate the compiler detection on an increasingly complicated list of every bit of QEMU that uses ObjC, just require it unconditionally on macos hosts. Resolves https://gitlab.com/qemu-project/qemu/-/issues/2138 Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Daniel P. Berrang=C3=A9 Message-ID: <20240311133334.3991537-1-peter.maydell@linaro.org> Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- meson.build | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meson.build b/meson.build index f9dbe7634e..e3fab8ce9f 100644 --- a/meson.build +++ b/meson.build @@ -66,7 +66,7 @@ if host_os =3D=3D 'windows' and add_languages('cpp', requ= ired: false, native: false) cxx =3D meson.get_compiler('cpp') endif if host_os =3D=3D 'darwin' and \ - add_languages('objc', required: get_option('cocoa'), native: false) + add_languages('objc', required: true, native: false) all_languages +=3D ['objc'] objc =3D meson.get_compiler('objc') endif --=20 2.41.0 From nobody Mon May 13 04:56:55 2024 Delivered-To: importer@patchew.org Received-SPF: none (zohomail.com: 8.43.85.245 is neither permitted nor denied by domain of lists.libvirt.org) client-ip=8.43.85.245; envelope-from=devel-bounces@lists.libvirt.org; helo=lists.libvirt.org; Authentication-Results: mx.zohomail.com; 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no-senders; approved; emergency; loop; banned-address; member-moderation; header-match-config-1; header-match-config-2; header-match-config-3; header-match-devel.lists.libvirt.org-0 CC: qemu-ppc@nongnu.org, qemu-arm@nongnu.org, qemu-block@nongnu.org, Zhao Liu , Thomas Huth , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , devel@lists.libvirt.org X-Mailman-Version: 3.2.2 Precedence: list List-Id: Development discussions about the libvirt library & tools Archived-At: List-Archive: List-Help: List-Post: List-Subscribe: List-Unsubscribe: Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZM-MESSAGEID: 1710231893169100001 From: Zhao Liu In the commit 54c4ea8f3ae6 ("hw/core/machine-smp: Deprecate unsupported 'parameter=3D1' SMP configurations"), the SMP related item is put under the section "User-mode emulator command line arguments" instead of "System emulator command line arguments". -smp is a system emulator command, so move SMP configurations item to system emulator section. Signed-off-by: Zhao Liu Reviewed-by: Thomas Huth Message-ID: <20240312071512.3283513-1-zhao1.liu@linux.intel.com> Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- docs/about/deprecated.rst | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst index dfd681cd02..2f9277c915 100644 --- a/docs/about/deprecated.rst +++ b/docs/about/deprecated.rst @@ -47,16 +47,6 @@ as short-form boolean values, and passed to plugins as `= `arg_name=3Don``. However, short-form booleans are deprecated and full explicit ``arg_name= =3Don`` form is preferred. =20 -User-mode emulator command line arguments ------------------------------------------ - -``-p`` (since 9.0) -'''''''''''''''''' - -The ``-p`` option pretends to control the host page size. However, -it is not possible to change the host page size, and using the -option only causes failures. - ``-smp`` (Unsupported "parameter=3D1" SMP configurations) (since 9.0) ''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''' =20 @@ -71,6 +61,16 @@ configurations (e.g. -smp drawers=3D1,books=3D1,clusters= =3D1 for x86 PC machine) is marked deprecated since 9.0, users have to ensure that all the topology me= mbers described with -smp are supported by the target machine. =20 +User-mode emulator command line arguments +----------------------------------------- + +``-p`` (since 9.0) +'''''''''''''''''' + +The ``-p`` option pretends to control the host page size. However, +it is not possible to change the host page size, and using the +option only causes failures. + QEMU Machine Protocol (QMP) commands ------------------------------------ =20 --=20 2.41.0 _______________________________________________ Devel mailing list -- devel@lists.libvirt.org To unsubscribe send an email to devel-leave@lists.libvirt.org