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Wysocki" , Len Brown , Dan Williams , Vishal Verma , Dave Jiang , Andrew Morton , Jonathan Cameron , Huang Ying , "Ho-Ren (Jack) Chuang" , linux-acpi@vger.kernel.org, linux-kernel@vger.kernel.org, nvdimm@lists.linux.dev, linux-cxl@vger.kernel.org, linux-mm@kvack.org Cc: "Ho-Ren (Jack) Chuang" , "Ho-Ren (Jack) Chuang" , qemu-devel@nongnu.org, Hao Xiang Subject: [PATCH v2 1/1] memory tier: acpi/hmat: create CPUless memory tiers after obtaining HMAT info Date: Tue, 12 Mar 2024 06:17:27 +0000 Message-Id: <20240312061729.1997111-2-horenchuang@bytedance.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20240312061729.1997111-1-horenchuang@bytedance.com> References: <20240312061729.1997111-1-horenchuang@bytedance.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::730; envelope-from=horenchuang@bytedance.com; helo=mail-qk1-x730.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @bytedance.com) X-ZM-MESSAGEID: 1710224335481100003 Content-Type: text/plain; charset="utf-8" The current implementation treats emulated memory devices, such as CXL1.1 type3 memory, as normal DRAM when they are emulated as normal memory (E820_TYPE_RAM). However, these emulated devices have different characteristics than traditional DRAM, making it important to distinguish them. Thus, we modify the tiered memory initialization process to introduce a delay specifically for CPUless NUMA nodes. This delay ensures that the memory tier initialization for these nodes is deferred until HMAT information is obtained during the boot process. Finally, demotion tables are recalculated at the end. * Abstract common functions into `find_alloc_memory_type()` Since different memory devices require finding or allocating a memory type, these common steps are abstracted into a single function, `find_alloc_memory_type()`, enhancing code scalability and conciseness. * Handle cases where there is no HMAT when creating memory tiers There is a scenario where a CPUless node does not provide HMAT information. If no HMAT is specified, it falls back to using the default DRAM tier. * Change adist calculation code to use another new lock, mt_perf_lock. In the current implementation, iterating through CPUlist nodes requires holding the `memory_tier_lock`. However, `mt_calc_adistance()` will end up trying to acquire the same lock, leading to a potential deadlock. Therefore, we propose introducing a standalone `mt_perf_lock` to protect `default_dram_perf`. This approach not only avoids deadlock but also prevents holding a large lock simultaneously. Signed-off-by: Ho-Ren (Jack) Chuang Signed-off-by: Hao Xiang --- drivers/acpi/numa/hmat.c | 11 ++++++ drivers/dax/kmem.c | 13 +------ include/linux/acpi.h | 6 ++++ include/linux/memory-tiers.h | 8 +++++ mm/memory-tiers.c | 70 +++++++++++++++++++++++++++++++++--- 5 files changed, 92 insertions(+), 16 deletions(-) diff --git a/drivers/acpi/numa/hmat.c b/drivers/acpi/numa/hmat.c index d6b85f0f6082..28812ec2c793 100644 --- a/drivers/acpi/numa/hmat.c +++ b/drivers/acpi/numa/hmat.c @@ -38,6 +38,8 @@ static LIST_HEAD(targets); static LIST_HEAD(initiators); static LIST_HEAD(localities); =20 +static LIST_HEAD(hmat_memory_types); + static DEFINE_MUTEX(target_lock); =20 /* @@ -149,6 +151,12 @@ int acpi_get_genport_coordinates(u32 uid, } EXPORT_SYMBOL_NS_GPL(acpi_get_genport_coordinates, CXL); =20 +struct memory_dev_type *hmat_find_alloc_memory_type(int adist) +{ + return find_alloc_memory_type(adist, &hmat_memory_types); +} +EXPORT_SYMBOL_GPL(hmat_find_alloc_memory_type); + static __init void alloc_memory_initiator(unsigned int cpu_pxm) { struct memory_initiator *initiator; @@ -1038,6 +1046,9 @@ static __init int hmat_init(void) if (!hmat_set_default_dram_perf()) register_mt_adistance_algorithm(&hmat_adist_nb); =20 + /* Post-create CPUless memory tiers after getting HMAT info */ + memory_tier_late_init(); + return 0; out_put: hmat_free_structures(); diff --git a/drivers/dax/kmem.c b/drivers/dax/kmem.c index 42ee360cf4e3..aee17ab59f4f 100644 --- a/drivers/dax/kmem.c +++ b/drivers/dax/kmem.c @@ -55,21 +55,10 @@ static LIST_HEAD(kmem_memory_types); =20 static struct memory_dev_type *kmem_find_alloc_memory_type(int adist) { - bool found =3D false; struct memory_dev_type *mtype; =20 mutex_lock(&kmem_memory_type_lock); - list_for_each_entry(mtype, &kmem_memory_types, list) { - if (mtype->adistance =3D=3D adist) { - found =3D true; - break; - } - } - if (!found) { - mtype =3D alloc_memory_type(adist); - if (!IS_ERR(mtype)) - list_add(&mtype->list, &kmem_memory_types); - } + mtype =3D find_alloc_memory_type(adist, &kmem_memory_types); mutex_unlock(&kmem_memory_type_lock); =20 return mtype; diff --git a/include/linux/acpi.h b/include/linux/acpi.h index b7165e52b3c6..3f927ff01f02 100644 --- a/include/linux/acpi.h +++ b/include/linux/acpi.h @@ -434,12 +434,18 @@ int thermal_acpi_critical_trip_temp(struct acpi_devic= e *adev, int *ret_temp); =20 #ifdef CONFIG_ACPI_HMAT int acpi_get_genport_coordinates(u32 uid, struct access_coordinate *coord); +struct memory_dev_type *hmat_find_alloc_memory_type(int adist); #else static inline int acpi_get_genport_coordinates(u32 uid, struct access_coordinate *coord) { return -EOPNOTSUPP; } + +static inline struct memory_dev_type *hmat_find_alloc_memory_type(int adis= t) +{ + return NULL; +} #endif =20 #ifdef CONFIG_ACPI_NUMA diff --git a/include/linux/memory-tiers.h b/include/linux/memory-tiers.h index 69e781900082..4bc2596c5774 100644 --- a/include/linux/memory-tiers.h +++ b/include/linux/memory-tiers.h @@ -48,6 +48,9 @@ int mt_calc_adistance(int node, int *adist); int mt_set_default_dram_perf(int nid, struct access_coordinate *perf, const char *source); int mt_perf_to_adistance(struct access_coordinate *perf, int *adist); +struct memory_dev_type *find_alloc_memory_type(int adist, + struct list_head *memory_types); +void memory_tier_late_init(void); #ifdef CONFIG_MIGRATION int next_demotion_node(int node); void node_get_allowed_targets(pg_data_t *pgdat, nodemask_t *targets); @@ -136,5 +139,10 @@ static inline int mt_perf_to_adistance(struct access_c= oordinate *perf, int *adis { return -EIO; } + +static inline void memory_tier_late_init(void) +{ + +} #endif /* CONFIG_NUMA */ #endif /* _LINUX_MEMORY_TIERS_H */ diff --git a/mm/memory-tiers.c b/mm/memory-tiers.c index 0537664620e5..79f748d60e6f 100644 --- a/mm/memory-tiers.c +++ b/mm/memory-tiers.c @@ -6,6 +6,7 @@ #include #include #include +#include =20 #include "internal.h" =20 @@ -35,6 +36,7 @@ struct node_memory_type_map { }; =20 static DEFINE_MUTEX(memory_tier_lock); +static DEFINE_MUTEX(mt_perf_lock); static LIST_HEAD(memory_tiers); static struct node_memory_type_map node_memory_types[MAX_NUMNODES]; struct memory_dev_type *default_dram_type; @@ -623,6 +625,58 @@ void clear_node_memory_type(int node, struct memory_de= v_type *memtype) } EXPORT_SYMBOL_GPL(clear_node_memory_type); =20 +struct memory_dev_type *find_alloc_memory_type(int adist, struct list_head= *memory_types) +{ + bool found =3D false; + struct memory_dev_type *mtype; + + list_for_each_entry(mtype, memory_types, list) { + if (mtype->adistance =3D=3D adist) { + found =3D true; + break; + } + } + if (!found) { + mtype =3D alloc_memory_type(adist); + if (!IS_ERR(mtype)) + list_add(&mtype->list, memory_types); + } + + return mtype; +} +EXPORT_SYMBOL_GPL(find_alloc_memory_type); + +static void memory_tier_late_create(int node) +{ + struct memory_dev_type *mtype =3D NULL; + int adist =3D MEMTIER_ADISTANCE_DRAM; + + mt_calc_adistance(node, &adist); + if (adist !=3D MEMTIER_ADISTANCE_DRAM) { + mtype =3D hmat_find_alloc_memory_type(adist); + if (!IS_ERR(mtype)) + __init_node_memory_type(node, mtype); + else + pr_err("Failed to allocate a memory type at %s()\n", __func__); + } + + set_node_memory_tier(node); +} + +void memory_tier_late_init(void) +{ + int nid; + + mutex_lock(&memory_tier_lock); + for_each_node_state(nid, N_MEMORY) + if (!node_state(nid, N_CPU)) + memory_tier_late_create(nid); + + establish_demotion_targets(); + mutex_unlock(&memory_tier_lock); +} +EXPORT_SYMBOL_GPL(memory_tier_late_init); + static void dump_hmem_attrs(struct access_coordinate *coord, const char *p= refix) { pr_info( @@ -636,7 +690,7 @@ int mt_set_default_dram_perf(int nid, struct access_coo= rdinate *perf, { int rc =3D 0; =20 - mutex_lock(&memory_tier_lock); + mutex_lock(&mt_perf_lock); if (default_dram_perf_error) { rc =3D -EIO; goto out; @@ -684,7 +738,7 @@ int mt_set_default_dram_perf(int nid, struct access_coo= rdinate *perf, } =20 out: - mutex_unlock(&memory_tier_lock); + mutex_unlock(&mt_perf_lock); return rc; } =20 @@ -700,7 +754,7 @@ int mt_perf_to_adistance(struct access_coordinate *perf= , int *adist) perf->read_bandwidth + perf->write_bandwidth =3D=3D 0) return -EINVAL; =20 - mutex_lock(&memory_tier_lock); + mutex_lock(&mt_perf_lock); /* * The abstract distance of a memory node is in direct proportion to * its memory latency (read + write) and inversely proportional to its @@ -713,7 +767,7 @@ int mt_perf_to_adistance(struct access_coordinate *perf= , int *adist) (default_dram_perf.read_latency + default_dram_perf.write_latency) * (default_dram_perf.read_bandwidth + default_dram_perf.write_bandwidth) / (perf->read_bandwidth + perf->write_bandwidth); - mutex_unlock(&memory_tier_lock); + mutex_unlock(&mt_perf_lock); =20 return 0; } @@ -836,6 +890,14 @@ static int __init memory_tier_init(void) * types assigned. */ for_each_node_state(node, N_MEMORY) { + if (!node_state(node, N_CPU)) + /* + * Defer memory tier initialization on CPUless numa nodes. + * These will be initialized when HMAT information is + * available. + */ + continue; + memtier =3D set_node_memory_tier(node); if (IS_ERR(memtier)) /* --=20 Ho-Ren (Jack) Chuang