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[78.54.250.34]) by smtp.gmail.com with ESMTPSA id b2-20020aa7c902000000b00564e489ce9asm906157edt.12.2024.03.09.05.41.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 09 Mar 2024 05:41:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1709991671; x=1710596471; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wnO66AnmaDp5O1vZPqoDqyIqBLstHR6VW3Zpw6NqLJU=; b=lV1a3PZnBq0gG/P+4K82j7NGGTzvnYkDHATcapFpgdrzCMFFN6zUW8HqQtWSIJmSqv s8yWizN1Z3NNENphEiQsBSrqfPjqGnTZgcsOWZVCk+8U3Odis+f/jZxa/2xMjiOcepxC 5uBgfVbUj8QecmzN8ZeyHfGnouAr/h5qcBEH0FZNkWayQNG7rJPZ0+cKYXtnvyWoqVDw gKRMSmNGJR0aW1RbehdGHTVA34OnaVYimKn03X62IqIKiKX76L10GXaME6jthdQKOmde iUKw1DO3gknvMxFThQV5oxavDskIis7ZfoZtvSp2UqAiNI5FVCEBlEvN2D/m/Al7dEap YMLA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1709991671; x=1710596471; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wnO66AnmaDp5O1vZPqoDqyIqBLstHR6VW3Zpw6NqLJU=; b=H3myUoK96IO+a/0su7DK6K8mzuXJHmC6PAm4pDMDjSf3syBmNK8QKv7cFvYWaXfCai pFn1PUUbaJ1jG19UNS2V+3cwMEDnnuLcfJmsld7sQUc22ubN41JHwKP00Pzbk7IxIB+B VioYcmUho9H8Ki+fw1Vk4IoOe/3+xJ/VGHDfuCUg0a3V0aqEjf4zNOuHqWCggcA5IMwN okQFDWM20uGO1GyHSTkYwCwqMaaLRQidQjtRK2Yz/h9/cUAjyfIspyN7iSlYZ75+OQZb MbJQiRMi5jJTwpi/0zUPLuRWzxvmaAfK+GXbJJOoULmRL7+rj/jTk6G7tdOySQlV2fef aaqw== X-Gm-Message-State: AOJu0YwKNVHYCNHLskF/nRWNtDMEw5kBYQIjTpUAeU+vGuHzAfkhw6ih SMfqxDwmysIDppbGRFlj+RmLpTCSVGG+vCCbIeSSRl6udUAvjULcpZIjljBg X-Google-Smtp-Source: AGHT+IHKCwTHkROB7QdjAPQHJXnV8pyCBIn76o0R/wIO7qtd0y4o0jxYK3xI/kHdjeeBvAexqxX47g== X-Received: by 2002:ac2:4da4:0:b0:513:9b6d:ab0e with SMTP id h4-20020ac24da4000000b005139b6dab0emr1022564lfe.5.1709991670781; Sat, 09 Mar 2024 05:41:10 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: "Michael S. Tsirkin" , Marcel Apfelbaum , Bernhard Beschow Subject: [PATCH 1/2] hw/pci-host/pam: Free PAMMemoryRegion from Intel-specific bit handling Date: Sat, 9 Mar 2024 14:40:55 +0100 Message-ID: <20240309134056.1605-2-shentey@gmail.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240309134056.1605-1-shentey@gmail.com> References: <20240309134056.1605-1-shentey@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::136; envelope-from=shentey@gmail.com; helo=mail-lf1-x136.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1709991743904100003 Content-Type: text/plain; charset="utf-8" The PAM bit extraction is currently spread across pam.c and the northbridge device models, making the extraction logic harder to comprehend. Also note = how pam_update() deals with PAM_REGIONS_COUNT, even though it handles exactly o= ne region. Fix this (at the cost of minor code duplication) by moving the bit extraction into the northbridge device models. As a side effect, pam_update= () becomes less Intel-specific which would allow it to be reused e.g. in VIA northbridges. Signed-off-by: Bernhard Beschow --- include/hw/pci-host/pam.h | 7 +++---- hw/pci-host/i440fx.c | 7 +++++-- hw/pci-host/pam.c | 14 +++++++------- hw/pci-host/q35.c | 5 +++-- 4 files changed, 18 insertions(+), 15 deletions(-) diff --git a/include/hw/pci-host/pam.h b/include/hw/pci-host/pam.h index 005916f826..b9b33aecc8 100644 --- a/include/hw/pci-host/pam.h +++ b/include/hw/pci-host/pam.h @@ -70,7 +70,6 @@ /* PAM registers: log nibble and high nibble*/ #define PAM_ATTR_WE ((uint8_t)2) #define PAM_ATTR_RE ((uint8_t)1) -#define PAM_ATTR_MASK ((uint8_t)3) =20 /* SMRAM register */ #define SMRAM_D_OPEN ((uint8_t)(1 << 6)) @@ -83,13 +82,13 @@ #define PAM_REGIONS_COUNT 13 =20 typedef struct PAMMemoryRegion { - MemoryRegion alias[4]; /* index =3D PAM value */ - unsigned current; + MemoryRegion alias[4]; /* index =3D mode value */ + uint8_t mode; } PAMMemoryRegion; =20 void init_pam(PAMMemoryRegion *mem, Object *owner, MemoryRegion *ram, MemoryRegion *system, MemoryRegion *pci, uint32_t start, uint32_t size); -void pam_update(PAMMemoryRegion *mem, int idx, uint8_t val); +void pam_update(PAMMemoryRegion *mem, uint8_t mode); =20 #endif /* QEMU_PAM_H */ diff --git a/hw/pci-host/i440fx.c b/hw/pci-host/i440fx.c index 4f0a0438d7..cddd506ab0 100644 --- a/hw/pci-host/i440fx.c +++ b/hw/pci-host/i440fx.c @@ -64,6 +64,8 @@ struct I440FXState { #define I440FX_PAM_SIZE 7 #define I440FX_SMRAM 0x72 =20 +#define I440FX_PAM_ATTR_MASK ((uint8_t)3) + /* Keep it 2G to comply with older win32 guests */ #define I440FX_PCI_HOST_HOLE64_SIZE_DEFAULT (1ULL << 31) =20 @@ -88,8 +90,9 @@ static void i440fx_update_memory_mappings(PCII440FXState = *d) =20 memory_region_transaction_begin(); for (i =3D 0; i < ARRAY_SIZE(d->pam_regions); i++) { - pam_update(&d->pam_regions[i], i, - pd->config[I440FX_PAM + DIV_ROUND_UP(i, 2)]); + uint8_t reg =3D pd->config[I440FX_PAM + DIV_ROUND_UP(i, 2)]; + pam_update(&d->pam_regions[i], + (reg >> ((!(i & 1)) * 4)) & I440FX_PAM_ATTR_MASK); } memory_region_set_enabled(&d->smram_region, !(pd->config[I440FX_SMRAM] & SMRAM_D_OPEN)); diff --git a/hw/pci-host/pam.c b/hw/pci-host/pam.c index 68e9884d27..29c0db097a 100644 --- a/hw/pci-host/pam.c +++ b/hw/pci-host/pam.c @@ -51,20 +51,20 @@ void init_pam(PAMMemoryRegion *mem, Object *owner, Memo= ryRegion *ram_memory, start, size); =20 memory_region_transaction_begin(); - for (i =3D 0; i < 4; ++i) { + for (i =3D 0; i < ARRAY_SIZE(mem->alias); ++i) { memory_region_set_enabled(&mem->alias[i], false); memory_region_add_subregion_overlap(system_memory, start, &mem->alias[i], 1); } memory_region_transaction_commit(); - mem->current =3D 0; + mem->mode =3D 0; } =20 -void pam_update(PAMMemoryRegion *pam, int idx, uint8_t val) +void pam_update(PAMMemoryRegion *pam, uint8_t mode) { - assert(0 <=3D idx && idx < PAM_REGIONS_COUNT); + g_assert(mode < ARRAY_SIZE(pam->alias)); =20 - memory_region_set_enabled(&pam->alias[pam->current], false); - pam->current =3D (val >> ((!(idx & 1)) * 4)) & PAM_ATTR_MASK; - memory_region_set_enabled(&pam->alias[pam->current], true); + memory_region_set_enabled(&pam->alias[pam->mode], false); + pam->mode =3D mode; + memory_region_set_enabled(&pam->alias[pam->mode], true); } diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c index 0d7d4e3f08..947d9aa9c4 100644 --- a/hw/pci-host/q35.c +++ b/hw/pci-host/q35.c @@ -330,8 +330,9 @@ static void mch_update_pam(MCHPCIState *mch) =20 memory_region_transaction_begin(); for (i =3D 0; i < 13; i++) { - pam_update(&mch->pam_regions[i], i, - pd->config[MCH_HOST_BRIDGE_PAM0 + DIV_ROUND_UP(i, 2)]); + uint8_t reg =3D pd->config[MCH_HOST_BRIDGE_PAM0 + DIV_ROUND_UP(i, = 2)]; + pam_update(&mch->pam_regions[i], + (reg >> ((!(i & 1)) * 4)) & MCH_HOST_BRIDGE_PAM_MASK); } memory_region_transaction_commit(); } --=20 2.44.0 From nobody Mon May 13 09:45:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; 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Tsirkin" , Marcel Apfelbaum , Bernhard Beschow Subject: [PATCH 2/2] hw/pci-host/pam: Remove northbridge-specific PAM_REGIONS_COUNT Date: Sat, 9 Mar 2024 14:40:56 +0100 Message-ID: <20240309134056.1605-3-shentey@gmail.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240309134056.1605-1-shentey@gmail.com> References: <20240309134056.1605-1-shentey@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::535; envelope-from=shentey@gmail.com; helo=mail-ed1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1709991737872100003 Content-Type: text/plain; charset="utf-8" PAM_REGIONS_COUNT being 13 seems to be Intel-specific. There are VIA 82cXX northbridges having only 10, for example. Communicate this by having northbridge-specific constants. Signed-off-by: Bernhard Beschow -- Do we need the constants or can we omit them, given they're just used once? Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/pci-host/i440fx.h | 4 +++- include/hw/pci-host/pam.h | 2 -- include/hw/pci-host/q35.h | 4 +++- hw/pci-host/q35.c | 2 +- 4 files changed, 7 insertions(+), 5 deletions(-) diff --git a/include/hw/pci-host/i440fx.h b/include/hw/pci-host/i440fx.h index c988f70890..9e9b252660 100644 --- a/include/hw/pci-host/i440fx.h +++ b/include/hw/pci-host/i440fx.h @@ -22,12 +22,14 @@ =20 OBJECT_DECLARE_SIMPLE_TYPE(PCII440FXState, I440FX_PCI_DEVICE) =20 +#define I440FX_HOST_PAM_REGIONS_COUNT 13 + struct PCII440FXState { /*< private >*/ PCIDevice parent_obj; /*< public >*/ =20 - PAMMemoryRegion pam_regions[PAM_REGIONS_COUNT]; + PAMMemoryRegion pam_regions[I440FX_HOST_PAM_REGIONS_COUNT]; MemoryRegion smram_region; MemoryRegion smram, low_smram; }; diff --git a/include/hw/pci-host/pam.h b/include/hw/pci-host/pam.h index b9b33aecc8..25dbe6feaf 100644 --- a/include/hw/pci-host/pam.h +++ b/include/hw/pci-host/pam.h @@ -79,8 +79,6 @@ #define SMRAM_C_BASE_SEG_MASK ((uint8_t)0x7) #define SMRAM_C_BASE_SEG ((uint8_t)0x2) /* hardwired to b010 */ =20 -#define PAM_REGIONS_COUNT 13 - typedef struct PAMMemoryRegion { MemoryRegion alias[4]; /* index =3D mode value */ uint8_t mode; diff --git a/include/hw/pci-host/q35.h b/include/hw/pci-host/q35.h index bafcbe6752..618ecf05f4 100644 --- a/include/hw/pci-host/q35.h +++ b/include/hw/pci-host/q35.h @@ -35,6 +35,8 @@ OBJECT_DECLARE_SIMPLE_TYPE(Q35PCIHost, Q35_HOST_DEVICE) #define TYPE_MCH_PCI_DEVICE "mch" OBJECT_DECLARE_SIMPLE_TYPE(MCHPCIState, MCH_PCI_DEVICE) =20 +#define MCH_HOST_PAM_REGIONS_COUNT 13 + struct MCHPCIState { /*< private >*/ PCIDevice parent_obj; @@ -44,7 +46,7 @@ struct MCHPCIState { MemoryRegion *pci_address_space; MemoryRegion *system_memory; MemoryRegion *address_space_io; - PAMMemoryRegion pam_regions[PAM_REGIONS_COUNT]; + PAMMemoryRegion pam_regions[MCH_HOST_PAM_REGIONS_COUNT]; MemoryRegion smram_region, open_high_smram; MemoryRegion smram, low_smram, high_smram; MemoryRegion tseg_blackhole, tseg_window; diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c index 947d9aa9c4..6782bf4216 100644 --- a/hw/pci-host/q35.c +++ b/hw/pci-host/q35.c @@ -329,7 +329,7 @@ static void mch_update_pam(MCHPCIState *mch) int i; =20 memory_region_transaction_begin(); - for (i =3D 0; i < 13; i++) { + for (i =3D 0; i < ARRAY_SIZE(mch->pam_regions); i++) { uint8_t reg =3D pd->config[MCH_HOST_BRIDGE_PAM0 + DIV_ROUND_UP(i, = 2)]; pam_update(&mch->pam_regions[i], (reg >> ((!(i & 1)) * 4)) & MCH_HOST_BRIDGE_PAM_MASK); --=20 2.44.0