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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 06/14] target/arm: Define CNTPCTSS_EL0 and CNTVCTSS_EL0
Date: Fri, 8 Mar 2024 15:50:07 +0000
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For FEAT_ECV, new registers CNTPCTSS_EL0 and CNTVCTSS_EL0 are
defined, which are "self-synchronized" views of the physical and
virtual counts as seen in the CNTPCT_EL0 and CNTVCT_EL0 registers
(meaning that no barriers are needed around accesses to them to
ensure that reads of them do not occur speculatively and out-of-order
with other instructions).
For QEMU, all our system registers are self-synchronized, so we can
simply copy the existing implementation of CNTPCT_EL0 and CNTVCT_EL0
to the new register encodings.
This means we now implement all the functionality required for
ID_AA64MMFR0_EL1.ECV =3D=3D 0b0001.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240301183219.2424889-7-peter.maydell@linaro.org
---
target/arm/helper.c | 43 +++++++++++++++++++++++++++++++++++++++++++
1 file changed, 43 insertions(+)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 46e0c3c4fcc..68b5d6a4cb0 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -3389,6 +3389,34 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[]=
=3D {
},
};
=20
+/*
+ * FEAT_ECV adds extra views of CNTVCT_EL0 and CNTPCT_EL0 which
+ * are "self-synchronizing". For QEMU all sysregs are self-synchronizing,
+ * so our implementations here are identical to the normal registers.
+ */
+static const ARMCPRegInfo gen_timer_ecv_cp_reginfo[] =3D {
+ { .name =3D "CNTVCTSS", .cp =3D 15, .crm =3D 14, .opc1 =3D 9,
+ .access =3D PL0_R, .type =3D ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_I=
O,
+ .accessfn =3D gt_vct_access,
+ .readfn =3D gt_virt_cnt_read, .resetfn =3D arm_cp_reset_ignore,
+ },
+ { .name =3D "CNTVCTSS_EL0", .state =3D ARM_CP_STATE_AA64,
+ .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 0, .opc2 =3D 6,
+ .access =3D PL0_R, .type =3D ARM_CP_NO_RAW | ARM_CP_IO,
+ .accessfn =3D gt_vct_access, .readfn =3D gt_virt_cnt_read,
+ },
+ { .name =3D "CNTPCTSS", .cp =3D 15, .crm =3D 14, .opc1 =3D 8,
+ .access =3D PL0_R, .type =3D ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_I=
O,
+ .accessfn =3D gt_pct_access,
+ .readfn =3D gt_cnt_read, .resetfn =3D arm_cp_reset_ignore,
+ },
+ { .name =3D "CNTPCTSS_EL0", .state =3D ARM_CP_STATE_AA64,
+ .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 0, .opc2 =3D 5,
+ .access =3D PL0_R, .type =3D ARM_CP_NO_RAW | ARM_CP_IO,
+ .accessfn =3D gt_pct_access, .readfn =3D gt_cnt_read,
+ },
+};
+
#else
=20
/*
@@ -3422,6 +3450,18 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[]=
=3D {
},
};
=20
+/*
+ * CNTVCTSS_EL0 has the same trap conditions as CNTVCT_EL0, so it also
+ * is exposed to userspace by Linux.
+ */
+static const ARMCPRegInfo gen_timer_ecv_cp_reginfo[] =3D {
+ { .name =3D "CNTVCTSS_EL0", .state =3D ARM_CP_STATE_AA64,
+ .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 0, .opc2 =3D 6,
+ .access =3D PL0_R, .type =3D ARM_CP_NO_RAW | ARM_CP_IO,
+ .readfn =3D gt_virt_cnt_read,
+ },
+};
+
#endif
=20
static void par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t v=
alue)
@@ -9258,6 +9298,9 @@ void register_cp_regs_for_features(ARMCPU *cpu)
if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) {
define_arm_cp_regs(cpu, generic_timer_cp_reginfo);
}
+ if (cpu_isar_feature(aa64_ecv_traps, cpu)) {
+ define_arm_cp_regs(cpu, gen_timer_ecv_cp_reginfo);
+ }
if (arm_feature(env, ARM_FEATURE_VAPA)) {
ARMCPRegInfo vapa_cp_reginfo[] =3D {
{ .name =3D "PAR", .cp =3D 15, .crn =3D 7, .crm =3D 4, .opc1 =
=3D 0, .opc2 =3D 0,
--=20
2.34.1