From nobody Fri May 10 18:36:38 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1709913067; cv=none; d=zohomail.com; s=zohoarc; b=WLWmj6JlMjM7k8vF26TXIrrcggBHNBB/+k3+IP5kJfJSyJD6+gRE1+ZHGJXgM9W6PWA8KYyzvw9fvrhreS9iz4IoZhndOie0LW4MfJDKe8xb6sAh3E0yRI48bqJDDcQiD61NnjoxjUiuNhQBwgtLNDEnckwt2yjNrWGziNpHPkA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1709913067; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=47yLtI40tP8SrxZeJmDjIcSuSF/7CaeRaZZ7IrtzCkU=; b=PMWPB2dHMiyDy6BlokQixdTaHZ0FBujDFOifcYXh2hF9poH1TqJL/biD1Et4IynsXPz0/8t3jBrBGpYetttmdTiF48s5dPkqJU3Sdhn8RABqUodUBLPm5pfZvXay6YkjByPJbzBHG0dXy8PNRl2ceLoXwA39VyVGMGuXGCdCUBw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1709913067936563.5034244912405; Fri, 8 Mar 2024 07:51:07 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ricUL-0007PV-1p; Fri, 08 Mar 2024 10:50:25 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ricUI-0007EH-Sb for qemu-devel@nongnu.org; Fri, 08 Mar 2024 10:50:22 -0500 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ricUE-0004GR-Tx for qemu-devel@nongnu.org; Fri, 08 Mar 2024 10:50:22 -0500 Received: by mail-wr1-x434.google.com with SMTP id ffacd0b85a97d-33e7ae72312so209721f8f.1 for ; Fri, 08 Mar 2024 07:50:18 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f2-20020adff8c2000000b0033e7a204dc7sm856080wrq.32.2024.03.08.07.50.16 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Mar 2024 07:50:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1709913017; x=1710517817; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=47yLtI40tP8SrxZeJmDjIcSuSF/7CaeRaZZ7IrtzCkU=; b=uPyCa3/kfha10ldziFp7kwnXRf0281Bjwmr/pLTMLYP/4WInwn3YtjMRCaix6RjY9p Ww7vwBnkniz5BrH0olt25Q7GJ38yusQEB8mnBBWrKTgVdAsTLCcNtQa1ySim4GUqWvpJ E1n8xrWK18xFsOvESk51wEZdGDuX/8TK2XbHK3Io+iY09nCmLgmbTcOFthVtqTkD0aTp /hHAvyXQPsuN8C1kdNY+cz7S4sq1JVDbXvfXm2k8IernP9si7IVkRJRcM1EEQlGBQASc Z9I3J/Cb96PeRoOow+lCSxfDdm9abOfOGYJyWsNDaZ6+OiX8P7mtAXzOReT+5Sk6fF7H dd/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1709913017; x=1710517817; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=47yLtI40tP8SrxZeJmDjIcSuSF/7CaeRaZZ7IrtzCkU=; b=FeRVU1pCocO8Yi7k3tG7CW0XhbDRRV+vqp1ycw7pc76ZKzoJYB+9zMOvwirx6c22ys LpvR4LsTzBtVJuhiyHvgUYF6LLMbT2NYCkklQvTxIjPAK1Nm1zgSx2LJXA7InzbQM7Mn ORMq1egsNwk1tqRv55j3mR01IkK1W3LJkMpsAyIUCh9hJ5c9KUCtjt2xxhDrDk/1tq82 5+wuo6OCA+3itjdp/Zz6Ai9fxFGlDEdvaLbpfc/fPWedZLM85ahHtFHhL+WsYdfqxnCh BiKy9rX/GbTE+uGGDfluAiVGsASzWTU+CtOsyYtKsms0Ewl1+VnDytMIGCzl5BsNQtyW DIpQ== X-Gm-Message-State: AOJu0YyOSwCv8cVI+/B770xzcYCuutWpj55wLanJ2xymOVFAMVY2p063 WorvWrMkRDvKn5ePff/FQs8baZjbLUQM4ahmeiMerPA2tFrrdXcKQzuu2yZoJQ9Oqf9Qfcu8bYy 6 X-Google-Smtp-Source: AGHT+IGXXUa85pB1aReoId1+GEH9nf1V/qudigTSIqnSfDZlDGeKS5ZqHBtZI/FlLl2PHyVEHxTCpQ== X-Received: by 2002:adf:e7d1:0:b0:33e:7a9e:2fad with SMTP id e17-20020adfe7d1000000b0033e7a9e2fadmr599232wrn.47.1709913017219; Fri, 08 Mar 2024 07:50:17 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 01/14] target/arm: Move some register related defines to internals.h Date: Fri, 8 Mar 2024 15:50:02 +0000 Message-Id: <20240308155015.3637663-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240308155015.3637663-1-peter.maydell@linaro.org> References: <20240308155015.3637663-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1709913068571100001 cpu.h has a lot of #defines relating to CPU register fields. Most of these aren't actually used outside target/arm code, so there's no point in cluttering up the cpu.h file with them. Move some easy ones to internals.h. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-id: 20240301183219.2424889-2-peter.maydell@linaro.org --- target/arm/cpu.h | 128 ----------------------------------------- target/arm/internals.h | 128 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 128 insertions(+), 128 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index a5b3d8f7da7..c827daa33fa 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -140,11 +140,6 @@ typedef struct ARMGenericTimer { uint64_t ctl; /* Timer Control register */ } ARMGenericTimer; =20 -#define VTCR_NSW (1u << 29) -#define VTCR_NSA (1u << 30) -#define VSTCR_SW VTCR_NSW -#define VSTCR_SA VTCR_NSA - /* Define a maximum sized vector register. * For 32-bit, this is a 128-bit NEON/AdvSIMD register. * For 64-bit, this is a 2048-bit SVE register. @@ -1375,73 +1370,6 @@ void pmu_init(ARMCPU *cpu); #define SCTLR_SPINTMASK (1ULL << 62) /* FEAT_NMI */ #define SCTLR_TIDCP (1ULL << 63) /* FEAT_TIDCP1 */ =20 -/* Bit definitions for CPACR (AArch32 only) */ -FIELD(CPACR, CP10, 20, 2) -FIELD(CPACR, CP11, 22, 2) -FIELD(CPACR, TRCDIS, 28, 1) /* matches CPACR_EL1.TTA */ -FIELD(CPACR, D32DIS, 30, 1) /* up to v7; RAZ in v8 */ -FIELD(CPACR, ASEDIS, 31, 1) - -/* Bit definitions for CPACR_EL1 (AArch64 only) */ -FIELD(CPACR_EL1, ZEN, 16, 2) -FIELD(CPACR_EL1, FPEN, 20, 2) -FIELD(CPACR_EL1, SMEN, 24, 2) -FIELD(CPACR_EL1, TTA, 28, 1) /* matches CPACR.TRCDIS */ - -/* Bit definitions for HCPTR (AArch32 only) */ -FIELD(HCPTR, TCP10, 10, 1) -FIELD(HCPTR, TCP11, 11, 1) -FIELD(HCPTR, TASE, 15, 1) -FIELD(HCPTR, TTA, 20, 1) -FIELD(HCPTR, TAM, 30, 1) /* matches CPTR_EL2.TAM */ -FIELD(HCPTR, TCPAC, 31, 1) /* matches CPTR_EL2.TCPAC */ - -/* Bit definitions for CPTR_EL2 (AArch64 only) */ -FIELD(CPTR_EL2, TZ, 8, 1) /* !E2H */ -FIELD(CPTR_EL2, TFP, 10, 1) /* !E2H, matches HCPTR.TCP10 */ -FIELD(CPTR_EL2, TSM, 12, 1) /* !E2H */ -FIELD(CPTR_EL2, ZEN, 16, 2) /* E2H */ -FIELD(CPTR_EL2, FPEN, 20, 2) /* E2H */ -FIELD(CPTR_EL2, SMEN, 24, 2) /* E2H */ -FIELD(CPTR_EL2, TTA, 28, 1) -FIELD(CPTR_EL2, TAM, 30, 1) /* matches HCPTR.TAM */ -FIELD(CPTR_EL2, TCPAC, 31, 1) /* matches HCPTR.TCPAC */ - -/* Bit definitions for CPTR_EL3 (AArch64 only) */ -FIELD(CPTR_EL3, EZ, 8, 1) -FIELD(CPTR_EL3, TFP, 10, 1) -FIELD(CPTR_EL3, ESM, 12, 1) -FIELD(CPTR_EL3, TTA, 20, 1) -FIELD(CPTR_EL3, TAM, 30, 1) -FIELD(CPTR_EL3, TCPAC, 31, 1) - -#define MDCR_MTPME (1U << 28) -#define MDCR_TDCC (1U << 27) -#define MDCR_HLP (1U << 26) /* MDCR_EL2 */ -#define MDCR_SCCD (1U << 23) /* MDCR_EL3 */ -#define MDCR_HCCD (1U << 23) /* MDCR_EL2 */ -#define MDCR_EPMAD (1U << 21) -#define MDCR_EDAD (1U << 20) -#define MDCR_TTRF (1U << 19) -#define MDCR_STE (1U << 18) /* MDCR_EL3 */ -#define MDCR_SPME (1U << 17) /* MDCR_EL3 */ -#define MDCR_HPMD (1U << 17) /* MDCR_EL2 */ -#define MDCR_SDD (1U << 16) -#define MDCR_SPD (3U << 14) -#define MDCR_TDRA (1U << 11) -#define MDCR_TDOSA (1U << 10) -#define MDCR_TDA (1U << 9) -#define MDCR_TDE (1U << 8) -#define MDCR_HPME (1U << 7) -#define MDCR_TPM (1U << 6) -#define MDCR_TPMCR (1U << 5) -#define MDCR_HPMN (0x1fU) - -/* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */ -#define SDCR_VALID_MASK (MDCR_MTPME | MDCR_TDCC | MDCR_SCCD | \ - MDCR_EPMAD | MDCR_EDAD | MDCR_TTRF | \ - MDCR_STE | MDCR_SPME | MDCR_SPD) - #define CPSR_M (0x1fU) #define CPSR_T (1U << 5) #define CPSR_F (1U << 6) @@ -1488,41 +1416,6 @@ FIELD(CPTR_EL3, TCPAC, 31, 1) #define XPSR_NZCV CPSR_NZCV #define XPSR_IT CPSR_IT =20 -#define TTBCR_N (7U << 0) /* TTBCR.EAE=3D=3D0 */ -#define TTBCR_T0SZ (7U << 0) /* TTBCR.EAE=3D=3D1 */ -#define TTBCR_PD0 (1U << 4) -#define TTBCR_PD1 (1U << 5) -#define TTBCR_EPD0 (1U << 7) -#define TTBCR_IRGN0 (3U << 8) -#define TTBCR_ORGN0 (3U << 10) -#define TTBCR_SH0 (3U << 12) -#define TTBCR_T1SZ (3U << 16) -#define TTBCR_A1 (1U << 22) -#define TTBCR_EPD1 (1U << 23) -#define TTBCR_IRGN1 (3U << 24) -#define TTBCR_ORGN1 (3U << 26) -#define TTBCR_SH1 (1U << 28) -#define TTBCR_EAE (1U << 31) - -FIELD(VTCR, T0SZ, 0, 6) -FIELD(VTCR, SL0, 6, 2) -FIELD(VTCR, IRGN0, 8, 2) -FIELD(VTCR, ORGN0, 10, 2) -FIELD(VTCR, SH0, 12, 2) -FIELD(VTCR, TG0, 14, 2) -FIELD(VTCR, PS, 16, 3) -FIELD(VTCR, VS, 19, 1) -FIELD(VTCR, HA, 21, 1) -FIELD(VTCR, HD, 22, 1) -FIELD(VTCR, HWU59, 25, 1) -FIELD(VTCR, HWU60, 26, 1) -FIELD(VTCR, HWU61, 27, 1) -FIELD(VTCR, HWU62, 28, 1) -FIELD(VTCR, NSW, 29, 1) -FIELD(VTCR, NSA, 30, 1) -FIELD(VTCR, DS, 32, 1) -FIELD(VTCR, SL2, 33, 1) - /* Bit definitions for ARMv8 SPSR (PSTATE) format. * Only these are valid when in AArch64 mode; in * AArch32 mode SPSRs are basically CPSR-format. @@ -1730,21 +1623,6 @@ static inline void xpsr_write(CPUARMState *env, uint= 32_t val, uint32_t mask) #define HCR_TWEDEN (1ULL << 59) #define HCR_TWEDEL MAKE_64BIT_MASK(60, 4) =20 -#define HCRX_ENAS0 (1ULL << 0) -#define HCRX_ENALS (1ULL << 1) -#define HCRX_ENASR (1ULL << 2) -#define HCRX_FNXS (1ULL << 3) -#define HCRX_FGTNXS (1ULL << 4) -#define HCRX_SMPME (1ULL << 5) -#define HCRX_TALLINT (1ULL << 6) -#define HCRX_VINMI (1ULL << 7) -#define HCRX_VFNMI (1ULL << 8) -#define HCRX_CMOW (1ULL << 9) -#define HCRX_MCE2 (1ULL << 10) -#define HCRX_MSCEN (1ULL << 11) - -#define HPFAR_NS (1ULL << 63) - #define SCR_NS (1ULL << 0) #define SCR_IRQ (1ULL << 1) #define SCR_FIQ (1ULL << 2) @@ -1783,12 +1661,6 @@ static inline void xpsr_write(CPUARMState *env, uint= 32_t val, uint32_t mask) #define SCR_GPF (1ULL << 48) #define SCR_NSE (1ULL << 62) =20 -#define HSTR_TTEE (1 << 16) -#define HSTR_TJDBX (1 << 17) - -#define CNTHCTL_CNTVMASK (1 << 18) -#define CNTHCTL_CNTPMASK (1 << 19) - /* Return the current FPSCR value. */ uint32_t vfp_get_fpscr(CPUARMState *env); void vfp_set_fpscr(CPUARMState *env, uint32_t val); diff --git a/target/arm/internals.h b/target/arm/internals.h index 860bcc0c664..d8622c8e0f1 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -99,6 +99,134 @@ FIELD(DBGWCR, WT, 20, 1) FIELD(DBGWCR, MASK, 24, 5) FIELD(DBGWCR, SSCE, 29, 1) =20 +#define VTCR_NSW (1u << 29) +#define VTCR_NSA (1u << 30) +#define VSTCR_SW VTCR_NSW +#define VSTCR_SA VTCR_NSA + +/* Bit definitions for CPACR (AArch32 only) */ +FIELD(CPACR, CP10, 20, 2) +FIELD(CPACR, CP11, 22, 2) +FIELD(CPACR, TRCDIS, 28, 1) /* matches CPACR_EL1.TTA */ +FIELD(CPACR, D32DIS, 30, 1) /* up to v7; RAZ in v8 */ +FIELD(CPACR, ASEDIS, 31, 1) + +/* Bit definitions for CPACR_EL1 (AArch64 only) */ +FIELD(CPACR_EL1, ZEN, 16, 2) +FIELD(CPACR_EL1, FPEN, 20, 2) +FIELD(CPACR_EL1, SMEN, 24, 2) +FIELD(CPACR_EL1, TTA, 28, 1) /* matches CPACR.TRCDIS */ + +/* Bit definitions for HCPTR (AArch32 only) */ +FIELD(HCPTR, TCP10, 10, 1) +FIELD(HCPTR, TCP11, 11, 1) +FIELD(HCPTR, TASE, 15, 1) +FIELD(HCPTR, TTA, 20, 1) +FIELD(HCPTR, TAM, 30, 1) /* matches CPTR_EL2.TAM */ +FIELD(HCPTR, TCPAC, 31, 1) /* matches CPTR_EL2.TCPAC */ + +/* Bit definitions for CPTR_EL2 (AArch64 only) */ +FIELD(CPTR_EL2, TZ, 8, 1) /* !E2H */ +FIELD(CPTR_EL2, TFP, 10, 1) /* !E2H, matches HCPTR.TCP10 */ +FIELD(CPTR_EL2, TSM, 12, 1) /* !E2H */ +FIELD(CPTR_EL2, ZEN, 16, 2) /* E2H */ +FIELD(CPTR_EL2, FPEN, 20, 2) /* E2H */ +FIELD(CPTR_EL2, SMEN, 24, 2) /* E2H */ +FIELD(CPTR_EL2, TTA, 28, 1) +FIELD(CPTR_EL2, TAM, 30, 1) /* matches HCPTR.TAM */ +FIELD(CPTR_EL2, TCPAC, 31, 1) /* matches HCPTR.TCPAC */ + +/* Bit definitions for CPTR_EL3 (AArch64 only) */ +FIELD(CPTR_EL3, EZ, 8, 1) +FIELD(CPTR_EL3, TFP, 10, 1) +FIELD(CPTR_EL3, ESM, 12, 1) +FIELD(CPTR_EL3, TTA, 20, 1) +FIELD(CPTR_EL3, TAM, 30, 1) +FIELD(CPTR_EL3, TCPAC, 31, 1) + +#define MDCR_MTPME (1U << 28) +#define MDCR_TDCC (1U << 27) +#define MDCR_HLP (1U << 26) /* MDCR_EL2 */ +#define MDCR_SCCD (1U << 23) /* MDCR_EL3 */ +#define MDCR_HCCD (1U << 23) /* MDCR_EL2 */ +#define MDCR_EPMAD (1U << 21) +#define MDCR_EDAD (1U << 20) +#define MDCR_TTRF (1U << 19) +#define MDCR_STE (1U << 18) /* MDCR_EL3 */ +#define MDCR_SPME (1U << 17) /* MDCR_EL3 */ +#define MDCR_HPMD (1U << 17) /* MDCR_EL2 */ +#define MDCR_SDD (1U << 16) +#define MDCR_SPD (3U << 14) +#define MDCR_TDRA (1U << 11) +#define MDCR_TDOSA (1U << 10) +#define MDCR_TDA (1U << 9) +#define MDCR_TDE (1U << 8) +#define MDCR_HPME (1U << 7) +#define MDCR_TPM (1U << 6) +#define MDCR_TPMCR (1U << 5) +#define MDCR_HPMN (0x1fU) + +/* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */ +#define SDCR_VALID_MASK (MDCR_MTPME | MDCR_TDCC | MDCR_SCCD | \ + MDCR_EPMAD | MDCR_EDAD | MDCR_TTRF | \ + MDCR_STE | MDCR_SPME | MDCR_SPD) + +#define TTBCR_N (7U << 0) /* TTBCR.EAE=3D=3D0 */ +#define TTBCR_T0SZ (7U << 0) /* TTBCR.EAE=3D=3D1 */ +#define TTBCR_PD0 (1U << 4) +#define TTBCR_PD1 (1U << 5) +#define TTBCR_EPD0 (1U << 7) +#define TTBCR_IRGN0 (3U << 8) +#define TTBCR_ORGN0 (3U << 10) +#define TTBCR_SH0 (3U << 12) +#define TTBCR_T1SZ (3U << 16) +#define TTBCR_A1 (1U << 22) +#define TTBCR_EPD1 (1U << 23) +#define TTBCR_IRGN1 (3U << 24) +#define TTBCR_ORGN1 (3U << 26) +#define TTBCR_SH1 (1U << 28) +#define TTBCR_EAE (1U << 31) + +FIELD(VTCR, T0SZ, 0, 6) +FIELD(VTCR, SL0, 6, 2) +FIELD(VTCR, IRGN0, 8, 2) +FIELD(VTCR, ORGN0, 10, 2) +FIELD(VTCR, SH0, 12, 2) +FIELD(VTCR, TG0, 14, 2) +FIELD(VTCR, PS, 16, 3) +FIELD(VTCR, VS, 19, 1) +FIELD(VTCR, HA, 21, 1) +FIELD(VTCR, HD, 22, 1) +FIELD(VTCR, HWU59, 25, 1) +FIELD(VTCR, HWU60, 26, 1) +FIELD(VTCR, HWU61, 27, 1) +FIELD(VTCR, HWU62, 28, 1) +FIELD(VTCR, NSW, 29, 1) +FIELD(VTCR, NSA, 30, 1) +FIELD(VTCR, DS, 32, 1) +FIELD(VTCR, SL2, 33, 1) + +#define HCRX_ENAS0 (1ULL << 0) +#define HCRX_ENALS (1ULL << 1) +#define HCRX_ENASR (1ULL << 2) +#define HCRX_FNXS (1ULL << 3) +#define HCRX_FGTNXS (1ULL << 4) +#define HCRX_SMPME (1ULL << 5) +#define HCRX_TALLINT (1ULL << 6) +#define HCRX_VINMI (1ULL << 7) +#define HCRX_VFNMI (1ULL << 8) +#define HCRX_CMOW (1ULL << 9) +#define HCRX_MCE2 (1ULL << 10) +#define HCRX_MSCEN (1ULL << 11) + +#define HPFAR_NS (1ULL << 63) + +#define HSTR_TTEE (1 << 16) +#define HSTR_TJDBX (1 << 17) + +#define CNTHCTL_CNTVMASK (1 << 18) +#define CNTHCTL_CNTPMASK (1 << 19) + /* We use a few fake FSR values for internal purposes in M profile. * M profile cores don't have A/R format FSRs, but currently our * get_phys_addr() code assumes A/R profile and reports failures via --=20 2.34.1 From nobody Fri May 10 18:36:38 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f2-20020adff8c2000000b0033e7a204dc7sm856080wrq.32.2024.03.08.07.50.17 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Mar 2024 07:50:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1709913018; x=1710517818; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=ZyiPy5xXJ/X9HqSi2OgP9Ewz4kgyfIfLY+4hqUdEidI=; b=Z1op39Wz6tWsy7PND3kxeTOVG8Mms8V9S/yDVNGbNbMwCco+VwOT+RAf1x1htgKLSa Ayde+R1ySjnnZqaBVKs0w1OMw+aOuBW8MIrtUy2bt2hKP52CTTf1llCb1EU5QCDq+Jcs B/5uXVJepBUayKp+2r1fsQx80aa0Wdh8gCq0ZxjElF26Fk4znU8sWehegpiR2zVPb3oP A3Tuqsqs5HDhhx1uyegcAwsYfa0WgjSr58HD5AREQJ+cZpFf4vv8e4hxPMq5QUiz4nB9 WCpA/vUItB0J/n+myDcbTfWVO81VYDYA4HkUnJANhvm+mto7soHV3JQcqYveJWItz+Ia Y3Wg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1709913018; x=1710517818; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ZyiPy5xXJ/X9HqSi2OgP9Ewz4kgyfIfLY+4hqUdEidI=; b=ZZo+3BOhO/97tNtpe34K+fXrRn3Pk5V7SJg2vH/sj8WbO2Tt7uCsQ0guzKcl7JWoLX MLfwID39YFc+ja4eU3m7ApTlol27n0SLgVQxGTk25vOXxmjWx8rIpddtOIOAN+6MmVqy xDXMWfbFhjymlKiZSMam1S5fo2cuRU+h/Ur1dkglGKWptdvvBjI5lG6JqonJoEkKKgKl b7X5t/0IPMxZTIvFmHRqId8/q4kshKFc3nnESJ/5F4V59IpVrtJ54XGXy0jVbiZZR/de Ub4eOnMYnTRiMa6Ik41wr91RleFWS1dg0nXFTk8q/gHE2+gsAWDArrYzJ0gERdz4DP5U EN/A== X-Gm-Message-State: AOJu0YzpqtSdahUgfAbMpxOhSuq22nsuFLnFubwsiSrVP4sQz3ikjhjd 0jbHx6ogfbQxL2yN8bckSdC9cgbtbXPhMfwVV4xthRfgLHGzqucBEjmHDtkqysnP9MNAW+byqtB L X-Google-Smtp-Source: AGHT+IF1dMWes94BUnn2CbgmcQZHL52j20gP8oMqEvF/lX4zUe1GEzPVq957t4CU/LHLpjqy/VKklw== X-Received: by 2002:ac2:5b44:0:b0:513:3e22:6e01 with SMTP id i4-20020ac25b44000000b005133e226e01mr3393952lfp.16.1709913017639; Fri, 08 Mar 2024 07:50:17 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 02/14] target/arm: Timer _EL02 registers UNDEF for E2H == 0 Date: Fri, 8 Mar 2024 15:50:03 +0000 Message-Id: <20240308155015.3637663-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240308155015.3637663-1-peter.maydell@linaro.org> References: <20240308155015.3637663-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::129; envelope-from=peter.maydell@linaro.org; helo=mail-lf1-x129.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1709913181061100002 Content-Type: text/plain; charset="utf-8" The timer _EL02 registers should UNDEF for invalid accesses from EL2 or EL3 when HCR_EL2.E2H =3D=3D 0, not take a cp access trap. We were delivering the exception to EL2 with the wrong syndrome. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20240301183219.2424889-3-peter.maydell@linaro.org --- target/arm/helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 90c4fb72ce4..978df6f2823 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6551,7 +6551,7 @@ static CPAccessResult e2h_access(CPUARMState *env, co= nst ARMCPRegInfo *ri, return CP_ACCESS_OK; } if (!(arm_hcr_el2_eff(env) & HCR_E2H)) { - return CP_ACCESS_TRAP; + return CP_ACCESS_TRAP_UNCATEGORIZED; } return CP_ACCESS_OK; } --=20 2.34.1 From nobody Fri May 10 18:36:38 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1709913176; cv=none; d=zohomail.com; s=zohoarc; b=k1fC41Nwqsx45uEIOVPPv8N2+Q6QgNm8l2YP1ljU2LFV51T2ngKgsgOupu4EiWZcNYzUUenRABXHe9r0UJbC/1u7HEiduC+OAgTaX/3dk3aFaawY4muwl57jL4nMagjjnz22nyHB42S2QWKVoqsM6L6HPF8bsY3S0q5U9FIwYB0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1709913176; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=3cWuaoCkTQVu5qObgGDnDzWYB/sSDqmlrWjM/kbjq6Y=; b=Q71J1sXL2Qgd6zWGcAWqXvNcfk7DYwXdKbwD0RP7qjDemtSNF3BPTagIeBX2cFvfaOlxqgSVw2nCOi9o9iv/RDxxXo1voVzj71Ruk+gUJqlszm14SRPrmgp9vZ8OG/WnhMmPMmI2Hxat8pGItTkRWDsK33ZGN+dxXta+A2XaRH8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1709913176507181.47125012075105; Fri, 8 Mar 2024 07:52:56 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ricUU-0008Jd-AD; Fri, 08 Mar 2024 10:50:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ricUL-0007Uc-RP for qemu-devel@nongnu.org; Fri, 08 Mar 2024 10:50:25 -0500 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ricUF-0004GX-NH for qemu-devel@nongnu.org; Fri, 08 Mar 2024 10:50:25 -0500 Received: by mail-wr1-x429.google.com with SMTP id ffacd0b85a97d-33e17342ea7so617182f8f.2 for ; Fri, 08 Mar 2024 07:50:19 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f2-20020adff8c2000000b0033e7a204dc7sm856080wrq.32.2024.03.08.07.50.17 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Mar 2024 07:50:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1709913018; x=1710517818; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=3cWuaoCkTQVu5qObgGDnDzWYB/sSDqmlrWjM/kbjq6Y=; b=YAMICA+YMQ08x0I5ifZP4dZOVXJGvGS0cbMWyVo5NEJcgAXkhz7VWGDUDopaQht967 Yn6cI1rmoR8w+7dx8F7iEXnOsR0N9WXxk/UYixtsUXfARXDYYQ27L2hMxXPbvD7lOXML VTxyg6HNLTp/TE6yLJXEULYdtvjQa4hTKqymoVcVq55x+AH5jKGmc33Xi/zMW/Bw/fvQ LGoom9G74gyFDeuOS+qPDVNJotjPQHTeDDJSXXRBt9yiv4CjVsemMYH9jx838dP7/RXZ pnzu9SqSbfHtBav6Z+8lp07K7Nk8BInUPwMlPWmPSTvM9vnjtafnwhwFLSsGswaSSXTQ 3G+Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1709913018; x=1710517818; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3cWuaoCkTQVu5qObgGDnDzWYB/sSDqmlrWjM/kbjq6Y=; b=e6gVKCzQKvhHVeCb2h1LO38deahQep27Dp0h/rdGCC6TewSgHjm3dw2+jzspyMSa6x KLCaIt8gQ+u0e1Dx5zb+0Ge+lIr1DSfDiFDzQ+KrIOfJvChb+xmXfWD1yXe35niV7qco WNhyDqHW5wf5Q3a0vuvfnH68za1DP8MEBLFBHUL2nEL98NdfaBwYsyTxsxiu9ll4CShM f9msaDwrZl+2a5lBjTnZh1SvcFmp2SZb3ghUmQPtAyxn/QoqULjnrvyFLj0CLpZ1WFnN uxBXq4/xhhyNQYxQeKNmeEzRdvuL7XDif4HnVl3+rAD3fxCwq+PBoS1GoiPTvvoy7kqJ 8Kuw== X-Gm-Message-State: AOJu0Yx65+x5jLVo/EEsgSv+y1OVz6JEKuYwRfC3yaRW82kq0nZYPZ0f kW1tRq7vkCEnNhuTn4mHLg8oHts1YUMiDllOcCjlYtZPutxhGYalKVI8K4abfKCBB8ESbKWnkyR W X-Google-Smtp-Source: AGHT+IEThre7/6PEGkb+BnZZJGbX3DXc0UHAF1SshUWoxiOtXgbuiQjFKrsG5CFrQyHHoZGodqvZYQ== X-Received: by 2002:a5d:6e48:0:b0:33d:7e99:babc with SMTP id j8-20020a5d6e48000000b0033d7e99babcmr14603150wrz.50.1709913018058; Fri, 08 Mar 2024 07:50:18 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 03/14] target/arm: use FIELD macro for CNTHCTL bit definitions Date: Fri, 8 Mar 2024 15:50:04 +0000 Message-Id: <20240308155015.3637663-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240308155015.3637663-1-peter.maydell@linaro.org> References: <20240308155015.3637663-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1709913177063100012 We prefer the FIELD macro over ad-hoc #defines for register bits; switch CNTHCTL to that style before we add any more bits. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-id: 20240301183219.2424889-4-peter.maydell@linaro.org --- target/arm/internals.h | 27 +++++++++++++++++++++++++-- target/arm/helper.c | 9 ++++----- 2 files changed, 29 insertions(+), 7 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index d8622c8e0f1..dd3da211a3f 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -224,8 +224,31 @@ FIELD(VTCR, SL2, 33, 1) #define HSTR_TTEE (1 << 16) #define HSTR_TJDBX (1 << 17) =20 -#define CNTHCTL_CNTVMASK (1 << 18) -#define CNTHCTL_CNTPMASK (1 << 19) +/* + * Depending on the value of HCR_EL2.E2H, bits 0 and 1 + * have different bit definitions, and EL1PCTEN might be + * bit 0 or bit 10. We use _E2H1 and _E2H0 suffixes to + * disambiguate if necessary. + */ +FIELD(CNTHCTL, EL0PCTEN_E2H1, 0, 1) +FIELD(CNTHCTL, EL0VCTEN_E2H1, 1, 1) +FIELD(CNTHCTL, EL1PCTEN_E2H0, 0, 1) +FIELD(CNTHCTL, EL1PCEN_E2H0, 1, 1) +FIELD(CNTHCTL, EVNTEN, 2, 1) +FIELD(CNTHCTL, EVNTDIR, 3, 1) +FIELD(CNTHCTL, EVNTI, 4, 4) +FIELD(CNTHCTL, EL0VTEN, 8, 1) +FIELD(CNTHCTL, EL0PTEN, 9, 1) +FIELD(CNTHCTL, EL1PCTEN_E2H1, 10, 1) +FIELD(CNTHCTL, EL1PTEN, 11, 1) +FIELD(CNTHCTL, ECV, 12, 1) +FIELD(CNTHCTL, EL1TVT, 13, 1) +FIELD(CNTHCTL, EL1TVCT, 14, 1) +FIELD(CNTHCTL, EL1NVPCT, 15, 1) +FIELD(CNTHCTL, EL1NVVCT, 16, 1) +FIELD(CNTHCTL, EVNTIS, 17, 1) +FIELD(CNTHCTL, CNTVMASK, 18, 1) +FIELD(CNTHCTL, CNTPMASK, 19, 1) =20 /* We use a few fake FSR values for internal purposes in M profile. * M profile cores don't have A/R format FSRs, but currently our diff --git a/target/arm/helper.c b/target/arm/helper.c index 978df6f2823..1c82d12a883 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2652,8 +2652,8 @@ static void gt_update_irq(ARMCPU *cpu, int timeridx) * It is RES0 in Secure and NonSecure state. */ if ((ss =3D=3D ARMSS_Root || ss =3D=3D ARMSS_Realm) && - ((timeridx =3D=3D GTIMER_VIRT && (cnthctl & CNTHCTL_CNTVMASK)) || - (timeridx =3D=3D GTIMER_PHYS && (cnthctl & CNTHCTL_CNTPMASK)))) { + ((timeridx =3D=3D GTIMER_VIRT && (cnthctl & R_CNTHCTL_CNTVMASK_MAS= K)) || + (timeridx =3D=3D GTIMER_PHYS && (cnthctl & R_CNTHCTL_CNTPMASK_MAS= K)))) { irqstate =3D 0; } =20 @@ -2968,12 +2968,11 @@ static void gt_cnthctl_write(CPUARMState *env, cons= t ARMCPRegInfo *ri, { ARMCPU *cpu =3D env_archcpu(env); uint32_t oldval =3D env->cp15.cnthctl_el2; - raw_write(env, ri, value); =20 - if ((oldval ^ value) & CNTHCTL_CNTVMASK) { + if ((oldval ^ value) & R_CNTHCTL_CNTVMASK_MASK) { gt_update_irq(cpu, GTIMER_VIRT); - } else if ((oldval ^ value) & CNTHCTL_CNTPMASK) { + } else if ((oldval ^ value) & R_CNTHCTL_CNTPMASK_MASK) { gt_update_irq(cpu, GTIMER_PHYS); } } --=20 2.34.1 From nobody Fri May 10 18:36:38 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1709913205; cv=none; d=zohomail.com; s=zohoarc; b=XyPsSWdVdQdaOUfjpHp+YQqmkL8VXh8chFWkDigGwkQDmwJd01/lDRfS/ktc9LlCh7ErswMH/Cflo8EASbU5J/FrH4qSsQxLpFUGRBmVoiAEJBiy5EjE2T8PtfUlz4jBQbcvHU4/JixvbQE5q74ZlFeXtd6cNF1oqUfL8qsdPnc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1709913205; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=ejoX6B83wxuPaH1DIRcrBj3nXLL1aa1KSo/sDVGM2V8=; b=BD0Ln7rKUUZn87qOCx4WgrRddWODfNifxW2sOd8umuYewNlUZsQX2yopze1fWLEyubXgKuuCrzKeQ0pYZMp9fI9l3dO2wPyNPTgS1SouJ6m+3zEuZIq+abEddLWAGmISzwsPfQp8uIjTNuQoOQFDA1puYkdp32RlzFR+bjofI1s= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1709913205873949.0032805390665; Fri, 8 Mar 2024 07:53:25 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ricUQ-0007tr-DK; Fri, 08 Mar 2024 10:50:30 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ricUL-0007UE-O9 for qemu-devel@nongnu.org; Fri, 08 Mar 2024 10:50:25 -0500 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ricUI-0004HD-1W for qemu-devel@nongnu.org; Fri, 08 Mar 2024 10:50:25 -0500 Received: by mail-wr1-x430.google.com with SMTP id ffacd0b85a97d-33e70d71756so930646f8f.1 for ; Fri, 08 Mar 2024 07:50:20 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f2-20020adff8c2000000b0033e7a204dc7sm856080wrq.32.2024.03.08.07.50.18 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Mar 2024 07:50:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1709913018; x=1710517818; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=ejoX6B83wxuPaH1DIRcrBj3nXLL1aa1KSo/sDVGM2V8=; b=TixzLlnRm8vqtrF7HpFPNFql9RvmFxu9v3N1qnhWMs/OZolFeJJNmetpLF4GuEqn79 ausIi1jR4mpoo3ECtu7tt3zc78NCAp5ru6PRZLTjPdgtQYSd1jkRHNusVCt5sNBJY86a nIuC6eQgdBVveTvdexrHQ+f0vFmPNzMv7+X1LGDU90scV+htM9Iox+043+rH04wJSbJ/ qy9TT7KY7Mx2DUZdAwRhgWQ3LG6aRbk2uMWO06tZFmaufc21vj55S4HG6CYXlr06+n2s p7HmBKjpJmCODqu8zBtHikYVF19ZCdxIZU+0nYoVHp//T/6b3r1DFtC4OGNlHapyrGEp JEoA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1709913018; x=1710517818; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ejoX6B83wxuPaH1DIRcrBj3nXLL1aa1KSo/sDVGM2V8=; b=EIQBRnkAEJNjZc7jej2fC5QBaSATDR39yypp+dc0+ldPtYyp0SCw8yG4OO/c3y2S5E SScPdUCjwh8E9v+lfA+SYleDb4MoG42SvbNdSfo9aRlqYgbMi6Llp6kgWZuiD2GN5Ixx eIDbAfLcfIMkL1Bs4MJ4uSOr8f4uijQfCZeG4s/aOE/iL//XkXAtyBhkPmoUoVaTvyEu 5IvA+c4elYe2aEq41wDBVorm/uZjH3GpTcHmguPQJ9US498NtY1B7RNA81v/zYnAqsQQ VaK8LC+AvSfytjJ4z2rQT20bGTBX02BKqC2pg7i+P5AiP5LGieH6QzerkAIRT+icdSAG Qcig== X-Gm-Message-State: AOJu0Yz0ME2L/FK78kqPkkZSgdV8FkJJLkKLo/96nLYgxTB/uiyQUm7U Zf3yr1SzIr3vMPhM9ebZdLL0YoUtHTkUhEVLWPDF8qdz6pJN16in7V60ZFT6o7P5dVyPutpDd+4 o X-Google-Smtp-Source: AGHT+IGXTB0g2oaucEAbhB74FVaVN9LhSoP6sdfE3PWpd437XXtRlCm0ITZgJpjGpf0KgzyD6izFnA== X-Received: by 2002:a5d:604f:0:b0:33d:f60c:53e2 with SMTP id j15-20020a5d604f000000b0033df60c53e2mr658853wrt.11.1709913018461; Fri, 08 Mar 2024 07:50:18 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 04/14] target/arm: Don't allow RES0 CNTHCTL_EL2 bits to be written Date: Fri, 8 Mar 2024 15:50:05 +0000 Message-Id: <20240308155015.3637663-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240308155015.3637663-1-peter.maydell@linaro.org> References: <20240308155015.3637663-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1709913207192100001 Content-Type: text/plain; charset="utf-8" Don't allow the guest to write CNTHCTL_EL2 bits which don't exist. This is not strictly architecturally required, but it is how we've tended to implement registers more recently. In particular, bits [19:18] are only present with FEAT_RME, and bits [17:12] will only be present with FEAT_ECV. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20240301183219.2424889-5-peter.maydell@linaro.org --- target/arm/helper.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index 1c82d12a883..37845218527 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2968,6 +2968,24 @@ static void gt_cnthctl_write(CPUARMState *env, const= ARMCPRegInfo *ri, { ARMCPU *cpu =3D env_archcpu(env); uint32_t oldval =3D env->cp15.cnthctl_el2; + uint32_t valid_mask =3D + R_CNTHCTL_EL0PCTEN_E2H1_MASK | + R_CNTHCTL_EL0VCTEN_E2H1_MASK | + R_CNTHCTL_EVNTEN_MASK | + R_CNTHCTL_EVNTDIR_MASK | + R_CNTHCTL_EVNTI_MASK | + R_CNTHCTL_EL0VTEN_MASK | + R_CNTHCTL_EL0PTEN_MASK | + R_CNTHCTL_EL1PCTEN_E2H1_MASK | + R_CNTHCTL_EL1PTEN_MASK; + + if (cpu_isar_feature(aa64_rme, cpu)) { + valid_mask |=3D R_CNTHCTL_CNTVMASK_MASK | R_CNTHCTL_CNTPMASK_MASK; + } + + /* Clear RES0 bits */ + value &=3D valid_mask; + raw_write(env, ri, value); =20 if ((oldval ^ value) & R_CNTHCTL_CNTVMASK_MASK) { --=20 2.34.1 From nobody Fri May 10 18:36:38 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1709913216; cv=none; d=zohomail.com; s=zohoarc; b=OM/JBV/xEtxXVCc1JCca/NXutk4hipU98YvGLY9vPiJ/SlgJs526Pe9DlE+6BG1r//lVzMbxUvSSB31wGHcjSg47nAiGfmefm8/iGOvI8dF8IDQVbSzmjFvt4k3hZ7qXSeT9Xka8jB4L4jXPYdYucn90CMltJyCkxeRysA44b3w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1709913216; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=jb73dre+liBKVTGsxSnPO/03s2fFvGwYZ1zKRjJSR7I=; b=miN/FP32+9tdkAUoyQ6/HQrz80DvpA/sJ0k3kodJLYc77hmDtOrPTB6SQLbUjSXfoVNDEFRrK6phgPhzp8Wtu/Xhba4EHDIrwfl0izfLq4Gve2pEXNbH528GJS4ZvoEt0OgxsB2gC1oyHVDBZOdZB7AuJJ/YwsqkbajHvkZ/sac= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1709913216693420.71563361234575; Fri, 8 Mar 2024 07:53:36 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ricUP-0007og-EJ; Fri, 08 Mar 2024 10:50:29 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ricUK-0007MU-EN for qemu-devel@nongnu.org; Fri, 08 Mar 2024 10:50:24 -0500 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ricUH-0004LV-BB for qemu-devel@nongnu.org; Fri, 08 Mar 2024 10:50:23 -0500 Received: by mail-wr1-x430.google.com with SMTP id ffacd0b85a97d-33e4f15710aso587102f8f.2 for ; Fri, 08 Mar 2024 07:50:20 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f2-20020adff8c2000000b0033e7a204dc7sm856080wrq.32.2024.03.08.07.50.18 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Mar 2024 07:50:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1709913019; x=1710517819; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=jb73dre+liBKVTGsxSnPO/03s2fFvGwYZ1zKRjJSR7I=; b=M4VDsNidn9Bn7KPNEXM+6maZKeicqvRKrVgT78hLPgbtuBYtQWTsEkDyp+fj0pJPu4 A8Y/pUaVz+LUteeyLV3m+kYNlBkzAWxfj1xv49XHf5aiFBUhZNu3ym91qjUB8BIbuAzW 4/GG06XBfsk+vvHcLiRQhStUp9Q5wAHXU430MVwoeNZtYlzkh/Hi/5RpgNsGSnwjKLuT ogC81dhh2iAnDz6Z271KDA1wsLgy6GZKSU8ltYD9e3hUBr6GOzSVCARXESMmeBg0eNWZ FhkkbgbCWGsl8Xq1omv/PLrzQC5bUL7uwGaDLYup4QbeTyk4RYHCF4FY2AnlIWodvsUj dqzw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1709913019; x=1710517819; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jb73dre+liBKVTGsxSnPO/03s2fFvGwYZ1zKRjJSR7I=; b=PS4RNguEfiG7iBkAujnHWwri9eAak9mH6ynHnR8kkkE8ZiwCIG61iLkB05EHuCaY2D X5RJ2zIQAxi91LFr8tXTnFx5fUbStesSS+M+DyqmzuuBFxtOo4eMQz/vq2XrSsQU20C/ QEL+SR+FMceyngCJWUeXNcSw0RxJxFCKZ9M91/m45LzS+TBRbi7xxDsXvr5VAam6L+ff 0G6b1ttTCjqOajagB50fCB8eDH2zACZ7rODG9ZUfWNUbXDCrTJcc9YcDNvVAK9XQeIiu Tezgu2Z0SdIPq7POqsGV3r5yFO7Tw+s3aEkE6to+ElG/60s6Z0cKts37/cDFVZj8wVXe 0HNA== X-Gm-Message-State: AOJu0YyfBNdn2HN7V6Z6jTi0hzSe8Oy+nU1m5l71tmZY6UgqDrRfmzW/ kDfsLzmjvSXEbYwk2FBrV5nVMUFHSxtzTcBR4KtLLVAqy0dem4IKaO4HbcGNd9R3jPw+IGPhG0Q 5 X-Google-Smtp-Source: AGHT+IGwl/XduBfbQLyG3b3xbY07BWFFDj/s9llYkszmORWH7BHgr3F0X3bHv5LA5xzk6Ab2XddRSg== X-Received: by 2002:adf:cd82:0:b0:33e:78d5:848e with SMTP id q2-20020adfcd82000000b0033e78d5848emr1182572wrj.12.1709913018842; Fri, 08 Mar 2024 07:50:18 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 05/14] target/arm: Implement new FEAT_ECV trap bits Date: Fri, 8 Mar 2024 15:50:06 +0000 Message-Id: <20240308155015.3637663-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240308155015.3637663-1-peter.maydell@linaro.org> References: <20240308155015.3637663-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1709913217235100001 Content-Type: text/plain; charset="utf-8" The functionality defined by ID_AA64MMFR0_EL1.ECV =3D=3D 1 is: * four new trap bits for various counter and timer registers * the CNTHCTL_EL2.EVNTIS and CNTKCTL_EL1.EVNTIS bits which control scaling of the event stream. This is a no-op for us, because we don't implement the event stream (our WFE is a NOP): all we need to do is allow CNTHCTL_EL2.ENVTIS to be read and written. * extensions to PMSCR_EL1.PCT, PMSCR_EL2.PCT, TRFCR_EL1.TS and TRFCR_EL2.TS: these are all no-ops for us, because we don't implement FEAT_SPE or FEAT_TRF. * new registers CNTPCTSS_EL0 and NCTVCTSS_EL0 which are "self-sychronizing" views of the CNTPCT_EL0 and CNTVCT_EL0, meaning that no barriers are needed around their accesses. For us these are just the same as the normal views, because all our sysregs are inherently self-sychronizing. In this commit we implement the trap handling and permit the new CNTHCTL_EL2 bits to be written. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20240301183219.2424889-6-peter.maydell@linaro.org --- target/arm/cpu-features.h | 5 ++++ target/arm/helper.c | 51 +++++++++++++++++++++++++++++++++++---- 2 files changed, 51 insertions(+), 5 deletions(-) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index 7567854db63..b447ec5c0e6 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -741,6 +741,11 @@ static inline bool isar_feature_aa64_fgt(const ARMISAR= egisters *id) return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, FGT) !=3D 0; } =20 +static inline bool isar_feature_aa64_ecv_traps(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, ECV) > 0; +} + static inline bool isar_feature_aa64_vh(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, VH) !=3D 0; diff --git a/target/arm/helper.c b/target/arm/helper.c index 37845218527..46e0c3c4fcc 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2530,6 +2530,11 @@ static CPAccessResult gt_counter_access(CPUARMState = *env, int timeridx, : !extract32(env->cp15.cnthctl_el2, 0, 1))) { return CP_ACCESS_TRAP_EL2; } + if (has_el2 && timeridx =3D=3D GTIMER_VIRT) { + if (FIELD_EX64(env->cp15.cnthctl_el2, CNTHCTL, EL1TVCT)) { + return CP_ACCESS_TRAP_EL2; + } + } break; } return CP_ACCESS_OK; @@ -2573,6 +2578,11 @@ static CPAccessResult gt_timer_access(CPUARMState *e= nv, int timeridx, } } } + if (has_el2 && timeridx =3D=3D GTIMER_VIRT) { + if (FIELD_EX64(env->cp15.cnthctl_el2, CNTHCTL, EL1TVT)) { + return CP_ACCESS_TRAP_EL2; + } + } break; } return CP_ACCESS_OK; @@ -2982,6 +2992,14 @@ static void gt_cnthctl_write(CPUARMState *env, const= ARMCPRegInfo *ri, if (cpu_isar_feature(aa64_rme, cpu)) { valid_mask |=3D R_CNTHCTL_CNTVMASK_MASK | R_CNTHCTL_CNTPMASK_MASK; } + if (cpu_isar_feature(aa64_ecv_traps, cpu)) { + valid_mask |=3D + R_CNTHCTL_EL1TVT_MASK | + R_CNTHCTL_EL1TVCT_MASK | + R_CNTHCTL_EL1NVPCT_MASK | + R_CNTHCTL_EL1NVVCT_MASK | + R_CNTHCTL_EVNTIS_MASK; + } =20 /* Clear RES0 bits */ value &=3D valid_mask; @@ -6564,7 +6582,6 @@ static CPAccessResult e2h_access(CPUARMState *env, co= nst ARMCPRegInfo *ri, { if (arm_current_el(env) =3D=3D 1) { /* This must be a FEAT_NV access */ - /* TODO: FEAT_ECV will need to check CNTHCTL_EL2 here */ return CP_ACCESS_OK; } if (!(arm_hcr_el2_eff(env) & HCR_E2H)) { @@ -6573,6 +6590,30 @@ static CPAccessResult e2h_access(CPUARMState *env, c= onst ARMCPRegInfo *ri, return CP_ACCESS_OK; } =20 +static CPAccessResult access_el1nvpct(CPUARMState *env, const ARMCPRegInfo= *ri, + bool isread) +{ + if (arm_current_el(env) =3D=3D 1) { + /* This must be a FEAT_NV access with NVx =3D=3D 101 */ + if (FIELD_EX64(env->cp15.cnthctl_el2, CNTHCTL, EL1NVPCT)) { + return CP_ACCESS_TRAP_EL2; + } + } + return e2h_access(env, ri, isread); +} + +static CPAccessResult access_el1nvvct(CPUARMState *env, const ARMCPRegInfo= *ri, + bool isread) +{ + if (arm_current_el(env) =3D=3D 1) { + /* This must be a FEAT_NV access with NVx =3D=3D 101 */ + if (FIELD_EX64(env->cp15.cnthctl_el2, CNTHCTL, EL1NVVCT)) { + return CP_ACCESS_TRAP_EL2; + } + } + return e2h_access(env, ri, isread); +} + /* Test if system register redirection is to occur in the current state. = */ static bool redirect_for_e2h(CPUARMState *env) { @@ -8398,14 +8439,14 @@ static const ARMCPRegInfo vhe_reginfo[] =3D { { .name =3D "CNTP_CTL_EL02", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 5, .crn =3D 14, .crm =3D 2, .opc2 =3D 1, .type =3D ARM_CP_IO | ARM_CP_ALIAS, - .access =3D PL2_RW, .accessfn =3D e2h_access, + .access =3D PL2_RW, .accessfn =3D access_el1nvpct, .nv2_redirect_offset =3D 0x180 | NV2_REDIR_NO_NV1, .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].c= tl), .writefn =3D gt_phys_ctl_write, .raw_writefn =3D raw_write }, { .name =3D "CNTV_CTL_EL02", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 5, .crn =3D 14, .crm =3D 3, .opc2 =3D 1, .type =3D ARM_CP_IO | ARM_CP_ALIAS, - .access =3D PL2_RW, .accessfn =3D e2h_access, + .access =3D PL2_RW, .accessfn =3D access_el1nvvct, .nv2_redirect_offset =3D 0x170 | NV2_REDIR_NO_NV1, .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].c= tl), .writefn =3D gt_virt_ctl_write, .raw_writefn =3D raw_write }, @@ -8424,14 +8465,14 @@ static const ARMCPRegInfo vhe_reginfo[] =3D { .type =3D ARM_CP_IO | ARM_CP_ALIAS, .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].c= val), .nv2_redirect_offset =3D 0x178 | NV2_REDIR_NO_NV1, - .access =3D PL2_RW, .accessfn =3D e2h_access, + .access =3D PL2_RW, .accessfn =3D access_el1nvpct, .writefn =3D gt_phys_cval_write, .raw_writefn =3D raw_write }, { .name =3D "CNTV_CVAL_EL02", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 5, .crn =3D 14, .crm =3D 3, .opc2 =3D 2, .type =3D ARM_CP_IO | ARM_CP_ALIAS, .nv2_redirect_offset =3D 0x168 | NV2_REDIR_NO_NV1, .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].c= val), - .access =3D PL2_RW, .accessfn =3D e2h_access, + .access =3D PL2_RW, .accessfn =3D access_el1nvvct, .writefn =3D gt_virt_cval_write, .raw_writefn =3D raw_write }, #endif }; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f2-20020adff8c2000000b0033e7a204dc7sm856080wrq.32.2024.03.08.07.50.18 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Mar 2024 07:50:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1709913019; x=1710517819; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=3Sm35nBBjeyJtKOD4iPFn/FW++KVU08Dtn0CIVkC0JA=; b=nQsbeTKMbywyU1lzrJMuO9n85LzjZUiNlrErcyMPY5wmBErK1/oNQbNbj4BBRz+5G3 C2GKdq3fHboC2NN+r/+Eih+Lp41izZfwPYd5iQVyCgBfA1bzgxyB5jiUBZRuArjG8PxT FJOoXDYNFhUdq8LdKk+9H3zEID6JDF326h20Qk85Pybx9pKOgd6I5iZoNqvlazqPOi39 pWOlt55TBM+IG3gMuap+LsUt9bBr7BCwILwycw/kqTAcIGueGraYeYS5UvRnNr7IeEII /AXTGg05lkEAXEzaWj/EVDoLf8I18DHCEDet8zmpbMfXPwOprfpTC9gmO5/gHXF21PB7 62Bg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1709913019; x=1710517819; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3Sm35nBBjeyJtKOD4iPFn/FW++KVU08Dtn0CIVkC0JA=; b=MPSIrFNJFRQxCDHEYk5eDq+amkabf6r+YeK7k3UNO/n5eR6VTP48gjSBrKFkQzpqBt HhNMymwM0AL17OsG9iYeHKOjqfZSFEfePdBKLsJxjpNCIvvEecMAitUWdpaqo5m/sSAo 7sXp+KCYrLNZHYJ0AJpx1qK306gAZB+vpqeD/Z36FqHmJt4XJBHYiaBPZpMJsSivEhlM 7cM7tajqK38LX7HhlTv7OZHt7BMkhLLZUvy1UMuGzM1aPzF58miA+qdY6wjiVzzY3nKb eJftoTmiwJdT5CEMgrqvQyTAkqy/pDDfStIq4+xyolcvfRL7VvzSj+v9qMRkcKOPj9nM c6sQ== X-Gm-Message-State: AOJu0YzkfDrHiY+t56y9qvELNUk+zHTzkr7Rbzt3IqfM96sI3YXiw6m8 PSFiNZfUBrhU1xFGvVFyZdGUEtCtSEH544cekMi85RbIflJBadKLy5tVzZXsa9nwo753e9LGKsW H X-Google-Smtp-Source: AGHT+IFm+WwSrksjnt/KOBtMvX9zZwUXWNAEKZluAqIlnIBX+KZ2D1D1mdtiPGXgRBCImrIKf9YOGQ== X-Received: by 2002:adf:ea8d:0:b0:33e:74ce:6121 with SMTP id s13-20020adfea8d000000b0033e74ce6121mr2044876wrm.3.1709913019231; Fri, 08 Mar 2024 07:50:19 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 06/14] target/arm: Define CNTPCTSS_EL0 and CNTVCTSS_EL0 Date: Fri, 8 Mar 2024 15:50:07 +0000 Message-Id: <20240308155015.3637663-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240308155015.3637663-1-peter.maydell@linaro.org> References: <20240308155015.3637663-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1709913086638100003 Content-Type: text/plain; charset="utf-8" For FEAT_ECV, new registers CNTPCTSS_EL0 and CNTVCTSS_EL0 are defined, which are "self-synchronized" views of the physical and virtual counts as seen in the CNTPCT_EL0 and CNTVCT_EL0 registers (meaning that no barriers are needed around accesses to them to ensure that reads of them do not occur speculatively and out-of-order with other instructions). For QEMU, all our system registers are self-synchronized, so we can simply copy the existing implementation of CNTPCT_EL0 and CNTVCT_EL0 to the new register encodings. This means we now implement all the functionality required for ID_AA64MMFR0_EL1.ECV =3D=3D 0b0001. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20240301183219.2424889-7-peter.maydell@linaro.org --- target/arm/helper.c | 43 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index 46e0c3c4fcc..68b5d6a4cb0 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3389,6 +3389,34 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[]= =3D { }, }; =20 +/* + * FEAT_ECV adds extra views of CNTVCT_EL0 and CNTPCT_EL0 which + * are "self-synchronizing". For QEMU all sysregs are self-synchronizing, + * so our implementations here are identical to the normal registers. + */ +static const ARMCPRegInfo gen_timer_ecv_cp_reginfo[] =3D { + { .name =3D "CNTVCTSS", .cp =3D 15, .crm =3D 14, .opc1 =3D 9, + .access =3D PL0_R, .type =3D ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_I= O, + .accessfn =3D gt_vct_access, + .readfn =3D gt_virt_cnt_read, .resetfn =3D arm_cp_reset_ignore, + }, + { .name =3D "CNTVCTSS_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 0, .opc2 =3D 6, + .access =3D PL0_R, .type =3D ARM_CP_NO_RAW | ARM_CP_IO, + .accessfn =3D gt_vct_access, .readfn =3D gt_virt_cnt_read, + }, + { .name =3D "CNTPCTSS", .cp =3D 15, .crm =3D 14, .opc1 =3D 8, + .access =3D PL0_R, .type =3D ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_I= O, + .accessfn =3D gt_pct_access, + .readfn =3D gt_cnt_read, .resetfn =3D arm_cp_reset_ignore, + }, + { .name =3D "CNTPCTSS_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 0, .opc2 =3D 5, + .access =3D PL0_R, .type =3D ARM_CP_NO_RAW | ARM_CP_IO, + .accessfn =3D gt_pct_access, .readfn =3D gt_cnt_read, + }, +}; + #else =20 /* @@ -3422,6 +3450,18 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[]= =3D { }, }; =20 +/* + * CNTVCTSS_EL0 has the same trap conditions as CNTVCT_EL0, so it also + * is exposed to userspace by Linux. + */ +static const ARMCPRegInfo gen_timer_ecv_cp_reginfo[] =3D { + { .name =3D "CNTVCTSS_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 0, .opc2 =3D 6, + .access =3D PL0_R, .type =3D ARM_CP_NO_RAW | ARM_CP_IO, + .readfn =3D gt_virt_cnt_read, + }, +}; + #endif =20 static void par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t v= alue) @@ -9258,6 +9298,9 @@ void register_cp_regs_for_features(ARMCPU *cpu) if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { define_arm_cp_regs(cpu, generic_timer_cp_reginfo); } + if (cpu_isar_feature(aa64_ecv_traps, cpu)) { + define_arm_cp_regs(cpu, gen_timer_ecv_cp_reginfo); + } if (arm_feature(env, ARM_FEATURE_VAPA)) { ARMCPRegInfo vapa_cp_reginfo[] =3D { { .name =3D "PAR", .cp =3D 15, .crn =3D 7, .crm =3D 4, .opc1 = =3D 0, .opc2 =3D 0, --=20 2.34.1 From nobody Fri May 10 18:36:38 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1709913180; cv=none; d=zohomail.com; s=zohoarc; b=aHx6/0xaYufWVftTHfc5un1tg8PpWVdngpVkjhC4b54AJsXs8ZYjWsbz3/iPzTdwNbSqUb9hijckIRjeUinKpRelDKugVkn9DfxaxPeq1IcU0j/xf5IpK+0u3gzTqU34AJL4PJoMKBVDeHz9apFbtdYWTDLEwZyeXzuJSUC+9k8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1709913180; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=Z8cudjxseJfBqRgnwTHuE2v1lkoipHqT1HiImqg+oJ0=; b=aTCk8tFTtwK6pl7jAMNTlMQvGoqGWVO14JJgduMzFqKX5ewKXE5kWyV8kfA1gTCQATXxCwdqWl/HQuSdT2/M07OiXsE/Nb+42EsGAQH7FrMMPXLqWddFZu7HKcePPlLxsqshP+vGePoxsIfD1/LSIUyZtU1bj2eljtFWZCIZZaM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1709913180166744.7851415869062; Fri, 8 Mar 2024 07:53:00 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ricUO-0007gC-B3; Fri, 08 Mar 2024 10:50:28 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ricUK-0007LF-AL for qemu-devel@nongnu.org; Fri, 08 Mar 2024 10:50:24 -0500 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ricUH-0004Rs-8l for qemu-devel@nongnu.org; Fri, 08 Mar 2024 10:50:23 -0500 Received: by mail-wr1-x431.google.com with SMTP id ffacd0b85a97d-33e4f15710aso587118f8f.2 for ; Fri, 08 Mar 2024 07:50:20 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f2-20020adff8c2000000b0033e7a204dc7sm856080wrq.32.2024.03.08.07.50.19 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Mar 2024 07:50:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1709913020; x=1710517820; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=Z8cudjxseJfBqRgnwTHuE2v1lkoipHqT1HiImqg+oJ0=; b=xR1b0QanZpfVGeyGbGyG+Gs8S5bNh72jhI064sF474vLGKAM88/VDH4xhhvJd5hyL0 OKqRotUqN06uUadlN7KQ8yMAKz1TdFJKqDZpIhqDx4ziUJ5xpraT3C3YHN9zby++/odM wYhRgzmArHxgTpviIa/A9LmR9YR7ILIWsWkMddvDA8dNEIdTpK59ywZxLeW5+TzsJ3bY BLKrUbPix77Z12Ksg6P+ydPm23HRrYKUOr3PEa+5HtZ44/7/j3vgAo/Qz82xWdiOV99p R7qmk5FSfdrJs6mSCjpiRBlU916qUbSWjTJ1tLs/JELZFVT2tS05Bp8qkMTJprqbHOkd lf/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1709913020; x=1710517820; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Z8cudjxseJfBqRgnwTHuE2v1lkoipHqT1HiImqg+oJ0=; b=dayV3qBJuGaCIeINT6dx+ebaDY9er81kJdjtRqMOZiq8xJdHOIbcBstLiKLLFBrQFd nL7Y3v08WdQto40x9gM3vwBIinPfcS23JFH9dDiA3TAhJzesjFaNnFeL1bCd4mo+flkR ZYnOwOBH5Me4L+r2iPvE6lbJelDI1BJlPy7mfk03V6dw8tZPnuGxUmQPRj9m3S9y8i0u T/Fctle3CUb0Z8NVeJWftfarMEmMg38KWKfDXymRHqS5MuzsGix58F+wOY1IZHDCf4gJ G/MKJIvqF3km7nMTZDy9uSX0Ka4jZ+ngHXC/7rFj9bA8VQaD5W8wPGimD3g6lLBA/e9n FKeA== X-Gm-Message-State: AOJu0YyFPqbEZtnGFwdOqxWr5wO7uwx1JBd8ivNtD+q5KOTjrZdFKedi G6sEo9TOH8VAQY1ZT7RIXlVYzVfkQ50IW7tSf3yKkrOIsjH+bjpy6i8LNItU5/OTHWkXZ/519TG U X-Google-Smtp-Source: AGHT+IFmPBbxhD21/Q6MfSlQCEE7+KQ63WrDoK6NR48ydWxdI2Zzg2mUKwYugMVEsLx0ltdCEUNBtQ== X-Received: by 2002:a5d:63d2:0:b0:33e:6a80:353b with SMTP id c18-20020a5d63d2000000b0033e6a80353bmr2834705wrw.42.1709913019765; Fri, 08 Mar 2024 07:50:19 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 07/14] target/arm: Implement FEAT_ECV CNTPOFF_EL2 handling Date: Fri, 8 Mar 2024 15:50:08 +0000 Message-Id: <20240308155015.3637663-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240308155015.3637663-1-peter.maydell@linaro.org> References: <20240308155015.3637663-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1709913181052100001 Content-Type: text/plain; charset="utf-8" When ID_AA64MMFR0_EL1.ECV is 0b0010, a new register CNTPOFF_EL2 is implemented. This is similar to the existing CNTVOFF_EL2, except that it controls a hypervisor-adjustable offset made to the physical counter and timer. Implement the handling for this register, which includes control/trap bits in SCR_EL3 and CNTHCTL_EL2. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20240301183219.2424889-8-peter.maydell@linaro.org --- target/arm/cpu-features.h | 5 +++ target/arm/cpu.h | 1 + target/arm/helper.c | 68 +++++++++++++++++++++++++++++++++++++-- target/arm/trace-events | 1 + 4 files changed, 73 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index b447ec5c0e6..e5758d9fbc8 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -746,6 +746,11 @@ static inline bool isar_feature_aa64_ecv_traps(const A= RMISARegisters *id) return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, ECV) > 0; } =20 +static inline bool isar_feature_aa64_ecv(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, ECV) > 1; +} + static inline bool isar_feature_aa64_vh(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, VH) !=3D 0; diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c827daa33fa..bc0c84873ff 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -452,6 +452,7 @@ typedef struct CPUArchState { uint64_t c14_cntkctl; /* Timer Control register */ uint64_t cnthctl_el2; /* Counter/Timer Hyp Control register */ uint64_t cntvoff_el2; /* Counter Virtual Offset register */ + uint64_t cntpoff_el2; /* Counter Physical Offset register */ ARMGenericTimer c14_timer[NUM_GTIMERS]; uint32_t c15_cpar; /* XScale Coprocessor Access Register */ uint32_t c15_ticonfig; /* TI925T configuration byte. */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 68b5d6a4cb0..3f3a5b55d4a 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1923,6 +1923,9 @@ static void scr_write(CPUARMState *env, const ARMCPRe= gInfo *ri, uint64_t value) if (cpu_isar_feature(aa64_rme, cpu)) { valid_mask |=3D SCR_NSE | SCR_GPF; } + if (cpu_isar_feature(aa64_ecv, cpu)) { + valid_mask |=3D SCR_ECVEN; + } } else { valid_mask &=3D ~(SCR_RW | SCR_ST); if (cpu_isar_feature(aa32_ras, cpu)) { @@ -2682,6 +2685,25 @@ void gt_rme_post_el_change(ARMCPU *cpu, void *ignore= d) gt_update_irq(cpu, GTIMER_PHYS); } =20 +static uint64_t gt_phys_raw_cnt_offset(CPUARMState *env) +{ + if ((env->cp15.scr_el3 & SCR_ECVEN) && + FIELD_EX64(env->cp15.cnthctl_el2, CNTHCTL, ECV) && + arm_is_el2_enabled(env) && + (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) !=3D (HCR_E2H | HCR_T= GE)) { + return env->cp15.cntpoff_el2; + } + return 0; +} + +static uint64_t gt_phys_cnt_offset(CPUARMState *env) +{ + if (arm_current_el(env) >=3D 2) { + return 0; + } + return gt_phys_raw_cnt_offset(env); +} + static void gt_recalc_timer(ARMCPU *cpu, int timeridx) { ARMGenericTimer *gt =3D &cpu->env.cp15.c14_timer[timeridx]; @@ -2692,7 +2714,7 @@ static void gt_recalc_timer(ARMCPU *cpu, int timeridx) * reset timer to when ISTATUS next has to change */ uint64_t offset =3D timeridx =3D=3D GTIMER_VIRT ? - cpu->env.cp15.cntvoff_el2 : 0; + cpu->env.cp15.cntvoff_el2 : gt_phys_raw_cnt_offset(&cpu->env); uint64_t count =3D gt_get_countervalue(&cpu->env); /* Note that this must be unsigned 64 bit arithmetic: */ int istatus =3D count - offset >=3D gt->cval; @@ -2755,7 +2777,7 @@ static void gt_timer_reset(CPUARMState *env, const AR= MCPRegInfo *ri, =20 static uint64_t gt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri) { - return gt_get_countervalue(env); + return gt_get_countervalue(env) - gt_phys_cnt_offset(env); } =20 static uint64_t gt_virt_cnt_offset(CPUARMState *env) @@ -2804,6 +2826,9 @@ static uint64_t gt_tval_read(CPUARMState *env, const = ARMCPRegInfo *ri, case GTIMER_HYPVIRT: offset =3D gt_virt_cnt_offset(env); break; + case GTIMER_PHYS: + offset =3D gt_phys_cnt_offset(env); + break; } =20 return (uint32_t)(env->cp15.c14_timer[timeridx].cval - @@ -2821,6 +2846,9 @@ static void gt_tval_write(CPUARMState *env, const ARM= CPRegInfo *ri, case GTIMER_HYPVIRT: offset =3D gt_virt_cnt_offset(env); break; + case GTIMER_PHYS: + offset =3D gt_phys_cnt_offset(env); + break; } =20 trace_arm_gt_tval_write(timeridx, value); @@ -3000,6 +3028,9 @@ static void gt_cnthctl_write(CPUARMState *env, const = ARMCPRegInfo *ri, R_CNTHCTL_EL1NVVCT_MASK | R_CNTHCTL_EVNTIS_MASK; } + if (cpu_isar_feature(aa64_ecv, cpu)) { + valid_mask |=3D R_CNTHCTL_ECV_MASK; + } =20 /* Clear RES0 bits */ value &=3D valid_mask; @@ -3417,6 +3448,34 @@ static const ARMCPRegInfo gen_timer_ecv_cp_reginfo[]= =3D { }, }; =20 +static CPAccessResult gt_cntpoff_access(CPUARMState *env, + const ARMCPRegInfo *ri, + bool isread) +{ + if (arm_current_el(env) =3D=3D 2 && !(env->cp15.scr_el3 & SCR_ECVEN)) { + return CP_ACCESS_TRAP_EL3; + } + return CP_ACCESS_OK; +} + +static void gt_cntpoff_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + ARMCPU *cpu =3D env_archcpu(env); + + trace_arm_gt_cntpoff_write(value); + raw_write(env, ri, value); + gt_recalc_timer(cpu, GTIMER_PHYS); +} + +static const ARMCPRegInfo gen_timer_cntpoff_reginfo =3D { + .name =3D "CNTPOFF_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 14, .crm =3D 0, .opc2 =3D 6, + .access =3D PL2_RW, .type =3D ARM_CP_IO, .resetvalue =3D 0, + .accessfn =3D gt_cntpoff_access, .writefn =3D gt_cntpoff_write, + .nv2_redirect_offset =3D 0x1a8, + .fieldoffset =3D offsetof(CPUARMState, cp15.cntpoff_el2), +}; #else =20 /* @@ -9301,6 +9360,11 @@ void register_cp_regs_for_features(ARMCPU *cpu) if (cpu_isar_feature(aa64_ecv_traps, cpu)) { define_arm_cp_regs(cpu, gen_timer_ecv_cp_reginfo); } +#ifndef CONFIG_USER_ONLY + if (cpu_isar_feature(aa64_ecv, cpu)) { + define_one_arm_cp_reg(cpu, &gen_timer_cntpoff_reginfo); + } +#endif if (arm_feature(env, ARM_FEATURE_VAPA)) { ARMCPRegInfo vapa_cp_reginfo[] =3D { { .name =3D "PAR", .cp =3D 15, .crn =3D 7, .crm =3D 4, .opc1 = =3D 0, .opc2 =3D 0, diff --git a/target/arm/trace-events b/target/arm/trace-events index 48cc0512dbe..4438dce7bec 100644 --- a/target/arm/trace-events +++ b/target/arm/trace-events @@ -8,6 +8,7 @@ arm_gt_tval_write(int timer, uint64_t value) "gt_tval_write= : timer %d value 0x%" arm_gt_ctl_write(int timer, uint64_t value) "gt_ctl_write: timer %d value = 0x%" PRIx64 arm_gt_imask_toggle(int timer) "gt_ctl_write: timer %d IMASK toggle" arm_gt_cntvoff_write(uint64_t value) "gt_cntvoff_write: value 0x%" PRIx64 +arm_gt_cntpoff_write(uint64_t value) "gt_cntpoff_write: value 0x%" PRIx64 arm_gt_update_irq(int timer, int irqstate) "gt_update_irq: timer %d irqsta= te %d" =20 # kvm.c --=20 2.34.1 From nobody Fri May 10 18:36:38 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-id: 20240301183219.2424889-9-peter.maydell@linaro.org --- docs/system/arm/emulation.rst | 1 + target/arm/tcg/cpu64.c | 1 + 2 files changed, 2 insertions(+) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index f67aea2d836..2a7bbb82dc4 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -28,6 +28,7 @@ the following architecture extensions: - FEAT_DotProd (Advanced SIMD dot product instructions) - FEAT_DoubleFault (Double Fault Extension) - FEAT_E0PD (Preventing EL0 access to halves of address maps) +- FEAT_ECV (Enhanced Counter Virtualization) - FEAT_EPAC (Enhanced pointer authentication) - FEAT_ETS (Enhanced Translation Synchronization) - FEAT_EVT (Enhanced Virtualization Traps) diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 5fba2c0f040..9f7a9f3d2cc 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -1184,6 +1184,7 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64MMFR0, TGRAN64_2, 2); /* 64k stage2 support= ed */ t =3D FIELD_DP64(t, ID_AA64MMFR0, TGRAN4_2, 2); /* 4k stage2 support= ed */ t =3D FIELD_DP64(t, ID_AA64MMFR0, FGT, 1); /* FEAT_FGT */ + t =3D FIELD_DP64(t, ID_AA64MMFR0, ECV, 2); /* FEAT_ECV */ cpu->isar.id_aa64mmfr0 =3D t; =20 t =3D cpu->isar.id_aa64mmfr1; --=20 2.34.1 From nobody Fri May 10 18:36:38 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1709913103; cv=none; d=zohomail.com; s=zohoarc; b=n5FzCiL7P3EAyy09XDOoHM5FbBzPrnm5y5CNdeH6UNAKI6Ealx8tx0U2u4xznNOJjmmc2rAJZ6CJFP+pnSEzL4xulINOP1whmNXZ2nRff3iFtJkZA5/OG4agMY2bFwpPid5+k7C3RtDFjM9e4Yj6Mh2Sypn0fAhkAQtic2zS/y0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1709913103; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=R9JSKRpCPp7qaF+0ucL8c3wtTbO7O1swM8G0dg1s+uo=; b=Rqa7djGkY0KWqZ1xD4dunADerBhgo9BI/fSyL1SZXPa8/iUREdEH4JlVBDlTjd9/1ua0yViOfqkwSU22FvYseFphKBNsFq5fInr2Pbq9kItNeIkbUx8H7krnE+cFF5bP60CVYSPa8Z2zjwTeI8BEWz63O83ah1pWJY3ikFZCjdY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1709913103771433.2692026547229; Fri, 8 Mar 2024 07:51:43 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ricUs-0000Yo-L3; Fri, 08 Mar 2024 10:50:58 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ricUT-0008Ic-Ra for qemu-devel@nongnu.org; Fri, 08 Mar 2024 10:50:33 -0500 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ricUI-0004Se-Fo for qemu-devel@nongnu.org; Fri, 08 Mar 2024 10:50:33 -0500 Received: by mail-wr1-x435.google.com with SMTP id ffacd0b85a97d-33e7ae72312so209765f8f.1 for ; Fri, 08 Mar 2024 07:50:21 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01, WEIRD_QUOTING=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1709913105008100001 From: In=C3=A8s Varhol Features supported : - the 8 STM32L4x5 GPIOs are initialized with their reset values (except IDR, see below) - input mode : setting a pin in input mode "externally" (using input irqs) results in an out irq (transmitted to SYSCFG) - output mode : setting a bit in ODR sets the corresponding out irq (if this line is configured in output mode) - pull-up, pull-down - push-pull, open-drain Difference with the real GPIOs : - Alternate Function and Analog mode aren't implemented : pins in AF/Analog behave like pins in input mode - floating pins stay at their last value - register IDR reset values differ from the real one : values are coherent with the other registers reset values and the fact that AF/Analog modes aren't implemented - setting I/O output speed isn't supported - locking port bits isn't supported - ADC function isn't supported - GPIOH has 16 pins instead of 2 pins - writing to registers LCKR, AFRL, AFRH and ASCR is ineffective Signed-off-by: Arnaud Minier Signed-off-by: In=C3=A8s Varhol Reviewed-by: Philippe Mathieu-Daud=C3=A9 Acked-by: Alistair Francis Message-id: 20240305210444.310665-2-ines.varhol@telecom-paris.fr Signed-off-by: Peter Maydell --- MAINTAINERS | 1 + docs/system/arm/b-l475e-iot01a.rst | 2 +- include/hw/gpio/stm32l4x5_gpio.h | 70 +++++ hw/gpio/stm32l4x5_gpio.c | 477 +++++++++++++++++++++++++++++ hw/gpio/Kconfig | 3 + hw/gpio/meson.build | 1 + hw/gpio/trace-events | 6 + 7 files changed, 559 insertions(+), 1 deletion(-) create mode 100644 include/hw/gpio/stm32l4x5_gpio.h create mode 100644 hw/gpio/stm32l4x5_gpio.c diff --git a/MAINTAINERS b/MAINTAINERS index 4183f2f3abb..4d96f855de5 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1133,6 +1133,7 @@ F: hw/arm/stm32l4x5_soc.c F: hw/misc/stm32l4x5_exti.c F: hw/misc/stm32l4x5_syscfg.c F: hw/misc/stm32l4x5_rcc.c +F: hw/gpio/stm32l4x5_gpio.c F: include/hw/*/stm32l4x5_*.h =20 B-L475E-IOT01A IoT Node diff --git a/docs/system/arm/b-l475e-iot01a.rst b/docs/system/arm/b-l475e-i= ot01a.rst index b857a56ca4e..0afef8e4f45 100644 --- a/docs/system/arm/b-l475e-iot01a.rst +++ b/docs/system/arm/b-l475e-iot01a.rst @@ -18,6 +18,7 @@ Currently B-L475E-IOT01A machine's only supports the foll= owing devices: - STM32L4x5 EXTI (Extended interrupts and events controller) - STM32L4x5 SYSCFG (System configuration controller) - STM32L4x5 RCC (Reset and clock control) +- STM32L4x5 GPIOs (General-purpose I/Os) =20 Missing devices """"""""""""""" @@ -25,7 +26,6 @@ Missing devices The B-L475E-IOT01A does *not* support the following devices: =20 - Serial ports (UART) -- General-purpose I/Os (GPIO) - Analog to Digital Converter (ADC) - SPI controller - Timer controller (TIMER) diff --git a/include/hw/gpio/stm32l4x5_gpio.h b/include/hw/gpio/stm32l4x5_g= pio.h new file mode 100644 index 00000000000..0d361f34105 --- /dev/null +++ b/include/hw/gpio/stm32l4x5_gpio.h @@ -0,0 +1,70 @@ +/* + * STM32L4x5 GPIO (General Purpose Input/Ouput) + * + * Copyright (c) 2024 Arnaud Minier + * Copyright (c) 2024 In=C3=A8s Varhol + * + * SPDX-License-Identifier: GPL-2.0-or-later + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +/* + * The reference used is the STMicroElectronics RM0351 Reference manual + * for STM32L4x5 and STM32L4x6 advanced Arm =C2=AE -based 32-bit MCUs. + * https://www.st.com/en/microcontrollers-microprocessors/stm32l4x5/docume= ntation.html + */ + +#ifndef HW_STM32L4X5_GPIO_H +#define HW_STM32L4X5_GPIO_H + +#include "hw/sysbus.h" +#include "qom/object.h" + +#define TYPE_STM32L4X5_GPIO "stm32l4x5-gpio" +OBJECT_DECLARE_SIMPLE_TYPE(Stm32l4x5GpioState, STM32L4X5_GPIO) + +#define GPIO_NUM_PINS 16 + +struct Stm32l4x5GpioState { + SysBusDevice parent_obj; + + MemoryRegion mmio; + + /* GPIO registers */ + uint32_t moder; + uint32_t otyper; + uint32_t ospeedr; + uint32_t pupdr; + uint32_t idr; + uint32_t odr; + uint32_t lckr; + uint32_t afrl; + uint32_t afrh; + uint32_t ascr; + + /* GPIO registers reset values */ + uint32_t moder_reset; + uint32_t ospeedr_reset; + uint32_t pupdr_reset; + + /* + * External driving of pins. + * The pins can be set externally through the device + * anonymous input GPIOs lines under certain conditions. + * The pin must not be in push-pull output mode, + * and can't be set high in open-drain mode. + * Pins driven externally and configured to + * output mode will in general be "disconnected" + * (see `get_gpio_pinmask_to_disconnect()`) + */ + uint16_t disconnected_pins; + uint16_t pins_connected_high; + + char *name; + Clock *clk; + qemu_irq pin[GPIO_NUM_PINS]; +}; + +#endif diff --git a/hw/gpio/stm32l4x5_gpio.c b/hw/gpio/stm32l4x5_gpio.c new file mode 100644 index 00000000000..63b8763e9d3 --- /dev/null +++ b/hw/gpio/stm32l4x5_gpio.c @@ -0,0 +1,477 @@ +/* + * STM32L4x5 GPIO (General Purpose Input/Ouput) + * + * Copyright (c) 2024 Arnaud Minier + * Copyright (c) 2024 In=C3=A8s Varhol + * + * SPDX-License-Identifier: GPL-2.0-or-later + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +/* + * The reference used is the STMicroElectronics RM0351 Reference manual + * for STM32L4x5 and STM32L4x6 advanced Arm =C2=AE -based 32-bit MCUs. + * https://www.st.com/en/microcontrollers-microprocessors/stm32l4x5/docume= ntation.html + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "hw/gpio/stm32l4x5_gpio.h" +#include "hw/irq.h" +#include "hw/qdev-clock.h" +#include "hw/qdev-properties.h" +#include "qapi/visitor.h" +#include "qapi/error.h" +#include "migration/vmstate.h" +#include "trace.h" + +#define GPIO_MODER 0x00 +#define GPIO_OTYPER 0x04 +#define GPIO_OSPEEDR 0x08 +#define GPIO_PUPDR 0x0C +#define GPIO_IDR 0x10 +#define GPIO_ODR 0x14 +#define GPIO_BSRR 0x18 +#define GPIO_LCKR 0x1C +#define GPIO_AFRL 0x20 +#define GPIO_AFRH 0x24 +#define GPIO_BRR 0x28 +#define GPIO_ASCR 0x2C + +/* 0b11111111_11111111_00000000_00000000 */ +#define RESERVED_BITS_MASK 0xFFFF0000 + +static void update_gpio_idr(Stm32l4x5GpioState *s); + +static bool is_pull_up(Stm32l4x5GpioState *s, unsigned pin) +{ + return extract32(s->pupdr, 2 * pin, 2) =3D=3D 1; +} + +static bool is_pull_down(Stm32l4x5GpioState *s, unsigned pin) +{ + return extract32(s->pupdr, 2 * pin, 2) =3D=3D 2; +} + +static bool is_output(Stm32l4x5GpioState *s, unsigned pin) +{ + return extract32(s->moder, 2 * pin, 2) =3D=3D 1; +} + +static bool is_open_drain(Stm32l4x5GpioState *s, unsigned pin) +{ + return extract32(s->otyper, pin, 1) =3D=3D 1; +} + +static bool is_push_pull(Stm32l4x5GpioState *s, unsigned pin) +{ + return extract32(s->otyper, pin, 1) =3D=3D 0; +} + +static void stm32l4x5_gpio_reset_hold(Object *obj) +{ + Stm32l4x5GpioState *s =3D STM32L4X5_GPIO(obj); + + s->moder =3D s->moder_reset; + s->otyper =3D 0x00000000; + s->ospeedr =3D s->ospeedr_reset; + s->pupdr =3D s->pupdr_reset; + s->idr =3D 0x00000000; + s->odr =3D 0x00000000; + s->lckr =3D 0x00000000; + s->afrl =3D 0x00000000; + s->afrh =3D 0x00000000; + s->ascr =3D 0x00000000; + + s->disconnected_pins =3D 0xFFFF; + s->pins_connected_high =3D 0x0000; + update_gpio_idr(s); +} + +static void stm32l4x5_gpio_set(void *opaque, int line, int level) +{ + Stm32l4x5GpioState *s =3D opaque; + /* + * The pin isn't set if line is configured in output mode + * except if level is 0 and the output is open-drain. + * This way there will be no short-circuit prone situations. + */ + if (is_output(s, line) && !(is_open_drain(s, line) && (level =3D=3D 0)= )) { + qemu_log_mask(LOG_GUEST_ERROR, "Line %d can't be driven externally= \n", + line); + return; + } + + s->disconnected_pins &=3D ~(1 << line); + if (level) { + s->pins_connected_high |=3D (1 << line); + } else { + s->pins_connected_high &=3D ~(1 << line); + } + trace_stm32l4x5_gpio_pins(s->name, s->disconnected_pins, + s->pins_connected_high); + update_gpio_idr(s); +} + + +static void update_gpio_idr(Stm32l4x5GpioState *s) +{ + uint32_t new_idr_mask =3D 0; + uint32_t new_idr =3D s->odr; + uint32_t old_idr =3D s->idr; + int new_pin_state, old_pin_state; + + for (int i =3D 0; i < GPIO_NUM_PINS; i++) { + if (is_output(s, i)) { + if (is_push_pull(s, i)) { + new_idr_mask |=3D (1 << i); + } else if (!(s->odr & (1 << i))) { + /* open-drain ODR 0 */ + new_idr_mask |=3D (1 << i); + /* open-drain ODR 1 */ + } else if (!(s->disconnected_pins & (1 << i)) && + !(s->pins_connected_high & (1 << i))) { + /* open-drain ODR 1 with pin connected low */ + new_idr_mask |=3D (1 << i); + new_idr &=3D ~(1 << i); + /* open-drain ODR 1 with unactive pin */ + } else if (is_pull_up(s, i)) { + new_idr_mask |=3D (1 << i); + } else if (is_pull_down(s, i)) { + new_idr_mask |=3D (1 << i); + new_idr &=3D ~(1 << i); + } + /* + * The only case left is for open-drain ODR 1 + * with unactive pin without pull-up or pull-down : + * the value is floating. + */ + /* input or analog mode with connected pin */ + } else if (!(s->disconnected_pins & (1 << i))) { + if (s->pins_connected_high & (1 << i)) { + /* pin high */ + new_idr_mask |=3D (1 << i); + new_idr |=3D (1 << i); + } else { + /* pin low */ + new_idr_mask |=3D (1 << i); + new_idr &=3D ~(1 << i); + } + /* input or analog mode with disconnected pin */ + } else { + if (is_pull_up(s, i)) { + /* pull-up */ + new_idr_mask |=3D (1 << i); + new_idr |=3D (1 << i); + } else if (is_pull_down(s, i)) { + /* pull-down */ + new_idr_mask |=3D (1 << i); + new_idr &=3D ~(1 << i); + } + /* + * The only case left is for a disconnected pin + * without pull-up or pull-down : + * the value is floating. + */ + } + } + + s->idr =3D (old_idr & ~new_idr_mask) | (new_idr & new_idr_mask); + trace_stm32l4x5_gpio_update_idr(s->name, old_idr, s->idr); + + for (int i =3D 0; i < GPIO_NUM_PINS; i++) { + if (new_idr_mask & (1 << i)) { + new_pin_state =3D (new_idr & (1 << i)) > 0; + old_pin_state =3D (old_idr & (1 << i)) > 0; + if (new_pin_state > old_pin_state) { + qemu_irq_raise(s->pin[i]); + } else if (new_pin_state < old_pin_state) { + qemu_irq_lower(s->pin[i]); + } + } + } +} + +/* + * Return mask of pins that are both configured in output + * mode and externally driven (except pins in open-drain + * mode externally set to 0). + */ +static uint32_t get_gpio_pinmask_to_disconnect(Stm32l4x5GpioState *s) +{ + uint32_t pins_to_disconnect =3D 0; + for (int i =3D 0; i < GPIO_NUM_PINS; i++) { + /* for each connected pin in output mode */ + if (!(s->disconnected_pins & (1 << i)) && is_output(s, i)) { + /* if either push-pull or high level */ + if (is_push_pull(s, i) || s->pins_connected_high & (1 << i)) { + pins_to_disconnect |=3D (1 << i); + qemu_log_mask(LOG_GUEST_ERROR, + "Line %d can't be driven externally\n", + i); + } + } + } + return pins_to_disconnect; +} + +/* + * Set field `disconnected_pins` and call `update_gpio_idr()` + */ +static void disconnect_gpio_pins(Stm32l4x5GpioState *s, uint16_t lines) +{ + s->disconnected_pins |=3D lines; + trace_stm32l4x5_gpio_pins(s->name, s->disconnected_pins, + s->pins_connected_high); + update_gpio_idr(s); +} + +static void disconnected_pins_set(Object *obj, Visitor *v, + const char *name, void *opaque, Error **errp) +{ + Stm32l4x5GpioState *s =3D STM32L4X5_GPIO(obj); + uint16_t value; + if (!visit_type_uint16(v, name, &value, errp)) { + return; + } + disconnect_gpio_pins(s, value); +} + +static void disconnected_pins_get(Object *obj, Visitor *v, + const char *name, void *opaque, Error **errp) +{ + visit_type_uint16(v, name, (uint16_t *)opaque, errp); +} + +static void clock_freq_get(Object *obj, Visitor *v, + const char *name, void *opaque, Error **errp) +{ + Stm32l4x5GpioState *s =3D STM32L4X5_GPIO(obj); + uint32_t clock_freq_hz =3D clock_get_hz(s->clk); + visit_type_uint32(v, name, &clock_freq_hz, errp); +} + +static void stm32l4x5_gpio_write(void *opaque, hwaddr addr, + uint64_t val64, unsigned int size) +{ + Stm32l4x5GpioState *s =3D opaque; + + uint32_t value =3D val64; + trace_stm32l4x5_gpio_write(s->name, addr, val64); + + switch (addr) { + case GPIO_MODER: + s->moder =3D value; + disconnect_gpio_pins(s, get_gpio_pinmask_to_disconnect(s)); + qemu_log_mask(LOG_UNIMP, + "%s: Analog and AF modes aren't supported\n\ + Analog and AF mode behave like input mode\n", + __func__); + return; + case GPIO_OTYPER: + s->otyper =3D value & ~RESERVED_BITS_MASK; + disconnect_gpio_pins(s, get_gpio_pinmask_to_disconnect(s)); + return; + case GPIO_OSPEEDR: + qemu_log_mask(LOG_UNIMP, + "%s: Changing I/O output speed isn't supported\n\ + I/O speed is already maximal\n", + __func__); + s->ospeedr =3D value; + return; + case GPIO_PUPDR: + s->pupdr =3D value; + update_gpio_idr(s); + return; + case GPIO_IDR: + qemu_log_mask(LOG_UNIMP, + "%s: GPIO->IDR is read-only\n", + __func__); + return; + case GPIO_ODR: + s->odr =3D value & ~RESERVED_BITS_MASK; + update_gpio_idr(s); + return; + case GPIO_BSRR: { + uint32_t bits_to_reset =3D (value & RESERVED_BITS_MASK) >> GPIO_NU= M_PINS; + uint32_t bits_to_set =3D value & ~RESERVED_BITS_MASK; + /* If both BSx and BRx are set, BSx has priority.*/ + s->odr &=3D ~bits_to_reset; + s->odr |=3D bits_to_set; + update_gpio_idr(s); + return; + } + case GPIO_LCKR: + qemu_log_mask(LOG_UNIMP, + "%s: Locking port bits configuration isn't supported= \n", + __func__); + s->lckr =3D value & ~RESERVED_BITS_MASK; + return; + case GPIO_AFRL: + qemu_log_mask(LOG_UNIMP, + "%s: Alternate functions aren't supported\n", + __func__); + s->afrl =3D value; + return; + case GPIO_AFRH: + qemu_log_mask(LOG_UNIMP, + "%s: Alternate functions aren't supported\n", + __func__); + s->afrh =3D value; + return; + case GPIO_BRR: { + uint32_t bits_to_reset =3D value & ~RESERVED_BITS_MASK; + s->odr &=3D ~bits_to_reset; + update_gpio_idr(s); + return; + } + case GPIO_ASCR: + qemu_log_mask(LOG_UNIMP, + "%s: ADC function isn't supported\n", + __func__); + s->ascr =3D value & ~RESERVED_BITS_MASK; + return; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, add= r); + } +} + +static uint64_t stm32l4x5_gpio_read(void *opaque, hwaddr addr, + unsigned int size) +{ + Stm32l4x5GpioState *s =3D opaque; + + trace_stm32l4x5_gpio_read(s->name, addr); + + switch (addr) { + case GPIO_MODER: + return s->moder; + case GPIO_OTYPER: + return s->otyper; + case GPIO_OSPEEDR: + return s->ospeedr; + case GPIO_PUPDR: + return s->pupdr; + case GPIO_IDR: + return s->idr; + case GPIO_ODR: + return s->odr; + case GPIO_BSRR: + return 0; + case GPIO_LCKR: + return s->lckr; + case GPIO_AFRL: + return s->afrl; + case GPIO_AFRH: + return s->afrh; + case GPIO_BRR: + return 0; + case GPIO_ASCR: + return s->ascr; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, add= r); + return 0; + } +} + +static const MemoryRegionOps stm32l4x5_gpio_ops =3D { + .read =3D stm32l4x5_gpio_read, + .write =3D stm32l4x5_gpio_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, + .impl =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + .unaligned =3D false, + }, + .valid =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + .unaligned =3D false, + }, +}; + +static void stm32l4x5_gpio_init(Object *obj) +{ + Stm32l4x5GpioState *s =3D STM32L4X5_GPIO(obj); + + memory_region_init_io(&s->mmio, obj, &stm32l4x5_gpio_ops, s, + TYPE_STM32L4X5_GPIO, 0x400); + + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); + + qdev_init_gpio_out(DEVICE(obj), s->pin, GPIO_NUM_PINS); + qdev_init_gpio_in(DEVICE(obj), stm32l4x5_gpio_set, GPIO_NUM_PINS); + + s->clk =3D qdev_init_clock_in(DEVICE(s), "clk", NULL, s, 0); + + object_property_add(obj, "disconnected-pins", "uint16", + disconnected_pins_get, disconnected_pins_set, + NULL, &s->disconnected_pins); + object_property_add(obj, "clock-freq-hz", "uint32", + clock_freq_get, NULL, NULL, NULL); +} + +static void stm32l4x5_gpio_realize(DeviceState *dev, Error **errp) +{ + Stm32l4x5GpioState *s =3D STM32L4X5_GPIO(dev); + if (!clock_has_source(s->clk)) { + error_setg(errp, "GPIO: clk input must be connected"); + return; + } +} + +static const VMStateDescription vmstate_stm32l4x5_gpio =3D { + .name =3D TYPE_STM32L4X5_GPIO, + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]){ + VMSTATE_UINT32(moder, Stm32l4x5GpioState), + VMSTATE_UINT32(otyper, Stm32l4x5GpioState), + VMSTATE_UINT32(ospeedr, Stm32l4x5GpioState), + VMSTATE_UINT32(pupdr, Stm32l4x5GpioState), + VMSTATE_UINT32(idr, Stm32l4x5GpioState), + VMSTATE_UINT32(odr, Stm32l4x5GpioState), + VMSTATE_UINT32(lckr, Stm32l4x5GpioState), + VMSTATE_UINT32(afrl, Stm32l4x5GpioState), + VMSTATE_UINT32(afrh, Stm32l4x5GpioState), + VMSTATE_UINT32(ascr, Stm32l4x5GpioState), + VMSTATE_UINT16(disconnected_pins, Stm32l4x5GpioState), + VMSTATE_UINT16(pins_connected_high, Stm32l4x5GpioState), + VMSTATE_END_OF_LIST() + } +}; + +static Property stm32l4x5_gpio_properties[] =3D { + DEFINE_PROP_STRING("name", Stm32l4x5GpioState, name), + DEFINE_PROP_UINT32("mode-reset", Stm32l4x5GpioState, moder_reset, 0), + DEFINE_PROP_UINT32("ospeed-reset", Stm32l4x5GpioState, ospeedr_reset, = 0), + DEFINE_PROP_UINT32("pupd-reset", Stm32l4x5GpioState, pupdr_reset, 0), + DEFINE_PROP_END_OF_LIST(), +}; + +static void stm32l4x5_gpio_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + ResettableClass *rc =3D RESETTABLE_CLASS(klass); + + device_class_set_props(dc, stm32l4x5_gpio_properties); + dc->vmsd =3D &vmstate_stm32l4x5_gpio; + dc->realize =3D stm32l4x5_gpio_realize; + rc->phases.hold =3D stm32l4x5_gpio_reset_hold; +} + +static const TypeInfo stm32l4x5_gpio_types[] =3D { + { + .name =3D TYPE_STM32L4X5_GPIO, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(Stm32l4x5GpioState), + .instance_init =3D stm32l4x5_gpio_init, + .class_init =3D stm32l4x5_gpio_class_init, + }, +}; + +DEFINE_TYPES(stm32l4x5_gpio_types) diff --git a/hw/gpio/Kconfig b/hw/gpio/Kconfig index d2cf3accc88..712940b8e0b 100644 --- a/hw/gpio/Kconfig +++ b/hw/gpio/Kconfig @@ -16,3 +16,6 @@ config GPIO_PWR =20 config SIFIVE_GPIO bool + +config STM32L4X5_GPIO + bool diff --git a/hw/gpio/meson.build b/hw/gpio/meson.build index 8a8d03d885b..3454b503aeb 100644 --- a/hw/gpio/meson.build +++ b/hw/gpio/meson.build @@ -13,5 +13,6 @@ system_ss.add(when: 'CONFIG_RASPI', if_true: files( 'bcm2835_gpio.c', 'bcm2838_gpio.c' )) +system_ss.add(when: 'CONFIG_STM32L4X5_SOC', if_true: files('stm32l4x5_gpio= .c')) system_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_gpio.c')) system_ss.add(when: 'CONFIG_SIFIVE_GPIO', if_true: files('sifive_gpio.c')) diff --git a/hw/gpio/trace-events b/hw/gpio/trace-events index 9736b362ac1..9331f4289d5 100644 --- a/hw/gpio/trace-events +++ b/hw/gpio/trace-events @@ -31,3 +31,9 @@ sifive_gpio_update_output_irq(int64_t line, int64_t value= ) "line %" PRIi64 " val # aspeed_gpio.c aspeed_gpio_read(uint64_t offset, uint64_t value) "offset: 0x%" PRIx64 " v= alue 0x%" PRIx64 aspeed_gpio_write(uint64_t offset, uint64_t value) "offset: 0x%" PRIx64 " = value 0x%" PRIx64 + +# stm32l4x5_gpio.c +stm32l4x5_gpio_read(char *gpio, uint64_t addr) "GPIO%s addr: 0x%" PRIx64 "= " +stm32l4x5_gpio_write(char *gpio, uint64_t addr, uint64_t data) "GPIO%s add= r: 0x%" PRIx64 " val: 0x%" PRIx64 "" +stm32l4x5_gpio_update_idr(char *gpio, uint32_t old_idr, uint32_t new_idr) = "GPIO%s from: 0x%x to: 0x%x" +stm32l4x5_gpio_pins(char *gpio, uint16_t disconnected, uint16_t high) "GPI= O%s disconnected pins: 0x%x levels: 0x%x" --=20 2.34.1 From nobody Fri May 10 18:36:38 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1709913231321100003 From: In=C3=A8s Varhol Signed-off-by: Arnaud Minier Signed-off-by: In=C3=A8s Varhol Reviewed-by: Philippe Mathieu-Daud=C3=A9 Acked-by: Alistair Francis Message-id: 20240305210444.310665-3-ines.varhol@telecom-paris.fr Signed-off-by: Peter Maydell --- include/hw/arm/stm32l4x5_soc.h | 2 + include/hw/gpio/stm32l4x5_gpio.h | 1 + include/hw/misc/stm32l4x5_syscfg.h | 3 +- hw/arm/stm32l4x5_soc.c | 71 +++++++++++++++++++++++------- hw/misc/stm32l4x5_syscfg.c | 1 + hw/arm/Kconfig | 3 +- 6 files changed, 63 insertions(+), 18 deletions(-) diff --git a/include/hw/arm/stm32l4x5_soc.h b/include/hw/arm/stm32l4x5_soc.h index af67b089efc..ee5f3624055 100644 --- a/include/hw/arm/stm32l4x5_soc.h +++ b/include/hw/arm/stm32l4x5_soc.h @@ -30,6 +30,7 @@ #include "hw/misc/stm32l4x5_syscfg.h" #include "hw/misc/stm32l4x5_exti.h" #include "hw/misc/stm32l4x5_rcc.h" +#include "hw/gpio/stm32l4x5_gpio.h" #include "qom/object.h" =20 #define TYPE_STM32L4X5_SOC "stm32l4x5-soc" @@ -49,6 +50,7 @@ struct Stm32l4x5SocState { OrIRQState exti_or_gates[NUM_EXTI_OR_GATES]; Stm32l4x5SyscfgState syscfg; Stm32l4x5RccState rcc; + Stm32l4x5GpioState gpio[NUM_GPIOS]; =20 MemoryRegion sram1; MemoryRegion sram2; diff --git a/include/hw/gpio/stm32l4x5_gpio.h b/include/hw/gpio/stm32l4x5_g= pio.h index 0d361f34105..878bd19fc9b 100644 --- a/include/hw/gpio/stm32l4x5_gpio.h +++ b/include/hw/gpio/stm32l4x5_gpio.h @@ -25,6 +25,7 @@ #define TYPE_STM32L4X5_GPIO "stm32l4x5-gpio" OBJECT_DECLARE_SIMPLE_TYPE(Stm32l4x5GpioState, STM32L4X5_GPIO) =20 +#define NUM_GPIOS 8 #define GPIO_NUM_PINS 16 =20 struct Stm32l4x5GpioState { diff --git a/include/hw/misc/stm32l4x5_syscfg.h b/include/hw/misc/stm32l4x5= _syscfg.h index 29c3522f9dd..23bb5641507 100644 --- a/include/hw/misc/stm32l4x5_syscfg.h +++ b/include/hw/misc/stm32l4x5_syscfg.h @@ -26,12 +26,11 @@ =20 #include "hw/sysbus.h" #include "qom/object.h" +#include "hw/gpio/stm32l4x5_gpio.h" =20 #define TYPE_STM32L4X5_SYSCFG "stm32l4x5-syscfg" OBJECT_DECLARE_SIMPLE_TYPE(Stm32l4x5SyscfgState, STM32L4X5_SYSCFG) =20 -#define NUM_GPIOS 8 -#define GPIO_NUM_PINS 16 #define SYSCFG_NUM_EXTICR 4 =20 struct Stm32l4x5SyscfgState { diff --git a/hw/arm/stm32l4x5_soc.c b/hw/arm/stm32l4x5_soc.c index bf9926057be..40e294f838f 100644 --- a/hw/arm/stm32l4x5_soc.c +++ b/hw/arm/stm32l4x5_soc.c @@ -28,6 +28,7 @@ #include "sysemu/sysemu.h" #include "hw/or-irq.h" #include "hw/arm/stm32l4x5_soc.h" +#include "hw/gpio/stm32l4x5_gpio.h" #include "hw/qdev-clock.h" #include "hw/misc/unimp.h" =20 @@ -99,6 +100,22 @@ static const int exti_or_gate1_lines_in[EXTI_OR_GATE1_N= UM_LINES_IN] =3D { 16, 35, 36, 37, 38, }; =20 +static const struct { + uint32_t addr; + uint32_t moder_reset; + uint32_t ospeedr_reset; + uint32_t pupdr_reset; +} stm32l4x5_gpio_cfg[NUM_GPIOS] =3D { + { 0x48000000, 0xABFFFFFF, 0x0C000000, 0x64000000 }, + { 0x48000400, 0xFFFFFEBF, 0x00000000, 0x00000100 }, + { 0x48000800, 0xFFFFFFFF, 0x00000000, 0x00000000 }, + { 0x48000C00, 0xFFFFFFFF, 0x00000000, 0x00000000 }, + { 0x48001000, 0xFFFFFFFF, 0x00000000, 0x00000000 }, + { 0x48001400, 0xFFFFFFFF, 0x00000000, 0x00000000 }, + { 0x48001800, 0xFFFFFFFF, 0x00000000, 0x00000000 }, + { 0x48001C00, 0x0000000F, 0x00000000, 0x00000000 }, +}; + static void stm32l4x5_soc_initfn(Object *obj) { Stm32l4x5SocState *s =3D STM32L4X5_SOC(obj); @@ -110,6 +127,11 @@ static void stm32l4x5_soc_initfn(Object *obj) } object_initialize_child(obj, "syscfg", &s->syscfg, TYPE_STM32L4X5_SYSC= FG); object_initialize_child(obj, "rcc", &s->rcc, TYPE_STM32L4X5_RCC); + + for (unsigned i =3D 0; i < NUM_GPIOS; i++) { + g_autofree char *name =3D g_strdup_printf("gpio%c", 'a' + i); + object_initialize_child(obj, name, &s->gpio[i], TYPE_STM32L4X5_GPI= O); + } } =20 static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp) @@ -118,8 +140,9 @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc,= Error **errp) Stm32l4x5SocState *s =3D STM32L4X5_SOC(dev_soc); const Stm32l4x5SocClass *sc =3D STM32L4X5_SOC_GET_CLASS(dev_soc); MemoryRegion *system_memory =3D get_system_memory(); - DeviceState *armv7m; + DeviceState *armv7m, *dev; SysBusDevice *busdev; + uint32_t pin_index; =20 if (!memory_region_init_rom(&s->flash, OBJECT(dev_soc), "flash", sc->flash_size, errp)) { @@ -160,17 +183,43 @@ static void stm32l4x5_soc_realize(DeviceState *dev_so= c, Error **errp) return; } =20 + /* GPIOs */ + for (unsigned i =3D 0; i < NUM_GPIOS; i++) { + g_autofree char *name =3D g_strdup_printf("%c", 'A' + i); + dev =3D DEVICE(&s->gpio[i]); + qdev_prop_set_string(dev, "name", name); + qdev_prop_set_uint32(dev, "mode-reset", + stm32l4x5_gpio_cfg[i].moder_reset); + qdev_prop_set_uint32(dev, "ospeed-reset", + stm32l4x5_gpio_cfg[i].ospeedr_reset); + qdev_prop_set_uint32(dev, "pupd-reset", + stm32l4x5_gpio_cfg[i].pupdr_reset); + busdev =3D SYS_BUS_DEVICE(&s->gpio[i]); + g_free(name); + name =3D g_strdup_printf("gpio%c-out", 'a' + i); + qdev_connect_clock_in(DEVICE(&s->gpio[i]), "clk", + qdev_get_clock_out(DEVICE(&(s->rcc)), name)); + if (!sysbus_realize(busdev, errp)) { + return; + } + sysbus_mmio_map(busdev, 0, stm32l4x5_gpio_cfg[i].addr); + } + /* System configuration controller */ busdev =3D SYS_BUS_DEVICE(&s->syscfg); if (!sysbus_realize(busdev, errp)) { return; } sysbus_mmio_map(busdev, 0, SYSCFG_ADDR); - /* - * TODO: when the GPIO device is implemented, connect it - * to SYCFG using `qdev_connect_gpio_out`, NUM_GPIOS and - * GPIO_NUM_PINS. - */ + + for (unsigned i =3D 0; i < NUM_GPIOS; i++) { + for (unsigned j =3D 0; j < GPIO_NUM_PINS; j++) { + pin_index =3D GPIO_NUM_PINS * i + j; + qdev_connect_gpio_out(DEVICE(&s->gpio[i]), j, + qdev_get_gpio_in(DEVICE(&s->syscfg), + pin_index)); + } + } =20 /* EXTI device */ busdev =3D SYS_BUS_DEVICE(&s->exti); @@ -217,7 +266,7 @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc,= Error **errp) } } =20 - for (unsigned i =3D 0; i < 16; i++) { + for (unsigned i =3D 0; i < GPIO_NUM_PINS; i++) { qdev_connect_gpio_out(DEVICE(&s->syscfg), i, qdev_get_gpio_in(DEVICE(&s->exti), i)); } @@ -302,14 +351,6 @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc= , Error **errp) /* RESERVED: 0x40024400, 0x7FDBC00 */ =20 /* AHB2 BUS */ - create_unimplemented_device("GPIOA", 0x48000000, 0x400); - create_unimplemented_device("GPIOB", 0x48000400, 0x400); - create_unimplemented_device("GPIOC", 0x48000800, 0x400); - create_unimplemented_device("GPIOD", 0x48000C00, 0x400); - create_unimplemented_device("GPIOE", 0x48001000, 0x400); - create_unimplemented_device("GPIOF", 0x48001400, 0x400); - create_unimplemented_device("GPIOG", 0x48001800, 0x400); - create_unimplemented_device("GPIOH", 0x48001C00, 0x400); /* RESERVED: 0x48002000, 0x7FDBC00 */ create_unimplemented_device("OTG_FS", 0x50000000, 0x40000); create_unimplemented_device("ADC", 0x50040000, 0x400); diff --git a/hw/misc/stm32l4x5_syscfg.c b/hw/misc/stm32l4x5_syscfg.c index fd68cb800bb..3dafc00b49d 100644 --- a/hw/misc/stm32l4x5_syscfg.c +++ b/hw/misc/stm32l4x5_syscfg.c @@ -27,6 +27,7 @@ #include "hw/irq.h" #include "migration/vmstate.h" #include "hw/misc/stm32l4x5_syscfg.h" +#include "hw/gpio/stm32l4x5_gpio.h" =20 #define SYSCFG_MEMRMP 0x00 #define SYSCFG_CFGR1 0x04 diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index d58d820788c..893a7bff66b 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -473,9 +473,10 @@ config STM32L4X5_SOC bool select ARM_V7M select OR_IRQ - select STM32L4X5_SYSCFG select STM32L4X5_EXTI + select STM32L4X5_SYSCFG select STM32L4X5_RCC + select STM32L4X5_GPIO =20 config XLNX_ZYNQMP_ARM bool --=20 2.34.1 From nobody Fri May 10 18:36:38 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f2-20020adff8c2000000b0033e7a204dc7sm856080wrq.32.2024.03.08.07.50.21 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Mar 2024 07:50:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1709913022; x=1710517822; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=960OLSjqCMX++IpXUlryGWvsAGbqsr+uBib4BGSP5ns=; b=hV5+8jk2sLexiP0hrK/43vWDub2vEVIbm1Kn+cGj0gkE+KGE0DVyT2mTxHhqetgxXg CYVX3uZejMx8Lh/78wtFQbyAsK8hS0YW6VCMN1lcXkPU2SHlz04H+M4UlDy8hwLJjBdI MoFt+HCKjyUcrn7UelmJavU8IOeMc4jFNrnWMBm2sqyd+ebK0fqE5ZPJaFFZeQq+G6QD dyfyaPclXOHoYhQ1b3nSpyi5u8mD3JbT1AwpRn2HnN9A9JIbCSv257Oo7tYtAv28dqMY HKsz3Gfeyu+Xg9V6ERB8u+kf8XZIDTfIFzvJE1lylrZRpwhh9ERYJoYG93+ZulKGGDEQ jhxQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1709913022; x=1710517822; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=960OLSjqCMX++IpXUlryGWvsAGbqsr+uBib4BGSP5ns=; b=SQjhA8q6SYgARn8IAZrZucsxs6w6abYTgkZh0037rmnkewHIpygKLg6VDPtKhaYZDd xJjwkvQqnc9UpK5Y3MHBiWxMgzKfI6Q7i2BSD9jbgoftY74HvBS7/k3iPcI8uG1WJD2y AYnyMTraFP3XXgKQvcliKq/OUe79LRYAaKz6JPGGLrgYkVDD/hNia7Vg9WNH3EyeqQ89 Qg6HMEGuyKE4O9XwCC8ofXT9B+dFM/7FQfDur4r7n/3lNSV0Jyjpb0lwUT947VuiAgLe o5mFu8aRsvxA0EDnrQvd1Z/XOggweoo86rBBCVG7LrcRHVSX236dmceBYlFoobOaeIxi XeMA== X-Gm-Message-State: AOJu0YytN2Oqi95trargDGWgqB6Ce/nCNZlZCEr00R2V/oWwkMl976r9 XzzocVYhMT8755ARdK2vsBRLI22VITBpnTu8C7UG2fO9yAc+CRc7s2EfrC2TiB4dg6aYlN9VMuF l X-Google-Smtp-Source: AGHT+IEm1/WMMjxyvqtPcljSt/qf8eRbMG90/VaDOBC3QKVlW6Ez9SlZgJ/JzzGZQPXu16GtBcDQxg== X-Received: by 2002:adf:ebcb:0:b0:33e:12eb:7822 with SMTP id v11-20020adfebcb000000b0033e12eb7822mr14792828wrn.71.1709913021700; Fri, 08 Mar 2024 07:50:21 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 11/14] tests/qtest: Add STM32L4x5 GPIO QTest testcase Date: Fri, 8 Mar 2024 15:50:12 +0000 Message-Id: <20240308155015.3637663-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240308155015.3637663-1-peter.maydell@linaro.org> References: <20240308155015.3637663-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1709913185172100001 From: In=C3=A8s Varhol The testcase contains : - `test_idr_reset_value()` : Checks the reset values of MODER, OTYPER, PUPDR, ODR and IDR. - `test_gpio_output_mode()` : Checks that writing a bit in register ODR results in the corresponding pin rising or lowering, if this pin is configured in output mode. - `test_gpio_input_mode()` : Checks that a input pin set high or low externally results in the pin rising and lowering. - `test_pull_up_pull_down()` : Checks that a floating pin in pull-up/down mode is actually high/down. - `test_push_pull()` : Checks that a pin set externally is disconnected when configured in push-pull output mode, and can't be set externally while in this mode. - `test_open_drain()` : Checks that a pin set externally high is disconnected when configured in open-drain output mode, and can't be set high while in this mode. - `test_bsrr_brr()` : Checks that writing to BSRR and BRR has the desired result in ODR. - `test_clock_enable()` : Checks that GPIO clock is at the right frequency after enabling it. Acked-by: Thomas Huth Signed-off-by: Arnaud Minier Signed-off-by: In=C3=A8s Varhol Message-id: 20240305210444.310665-4-ines.varhol@telecom-paris.fr Signed-off-by: Peter Maydell --- tests/qtest/stm32l4x5_gpio-test.c | 551 ++++++++++++++++++++++++++++++ tests/qtest/meson.build | 3 +- 2 files changed, 553 insertions(+), 1 deletion(-) create mode 100644 tests/qtest/stm32l4x5_gpio-test.c diff --git a/tests/qtest/stm32l4x5_gpio-test.c b/tests/qtest/stm32l4x5_gpio= -test.c new file mode 100644 index 00000000000..cc56be2031f --- /dev/null +++ b/tests/qtest/stm32l4x5_gpio-test.c @@ -0,0 +1,551 @@ +/* + * QTest testcase for STM32L4x5_GPIO + * + * Copyright (c) 2024 Arnaud Minier + * Copyright (c) 2024 In=C3=A8s Varhol + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "libqtest-single.h" + +#define GPIO_BASE_ADDR 0x48000000 +#define GPIO_SIZE 0x400 +#define NUM_GPIOS 8 +#define NUM_GPIO_PINS 16 + +#define GPIO_A 0x48000000 +#define GPIO_B 0x48000400 +#define GPIO_C 0x48000800 +#define GPIO_D 0x48000C00 +#define GPIO_E 0x48001000 +#define GPIO_F 0x48001400 +#define GPIO_G 0x48001800 +#define GPIO_H 0x48001C00 + +#define MODER 0x00 +#define OTYPER 0x04 +#define PUPDR 0x0C +#define IDR 0x10 +#define ODR 0x14 +#define BSRR 0x18 +#define BRR 0x28 + +#define MODER_INPUT 0 +#define MODER_OUTPUT 1 + +#define PUPDR_NONE 0 +#define PUPDR_PULLUP 1 +#define PUPDR_PULLDOWN 2 + +#define OTYPER_PUSH_PULL 0 +#define OTYPER_OPEN_DRAIN 1 + +const uint32_t moder_reset[NUM_GPIOS] =3D { + 0xABFFFFFF, + 0xFFFFFEBF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0x0000000F +}; + +const uint32_t pupdr_reset[NUM_GPIOS] =3D { + 0x64000000, + 0x00000100, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000 +}; + +const uint32_t idr_reset[NUM_GPIOS] =3D { + 0x0000A000, + 0x00000010, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000 +}; + +static uint32_t gpio_readl(unsigned int gpio, unsigned int offset) +{ + return readl(gpio + offset); +} + +static void gpio_writel(unsigned int gpio, unsigned int offset, uint32_t v= alue) +{ + writel(gpio + offset, value); +} + +static void gpio_set_bit(unsigned int gpio, unsigned int reg, + unsigned int pin, uint32_t value) +{ + uint32_t mask =3D 0xFFFFFFFF & ~(0x1 << pin); + gpio_writel(gpio, reg, (gpio_readl(gpio, reg) & mask) | value << pin); +} + +static void gpio_set_2bits(unsigned int gpio, unsigned int reg, + unsigned int pin, uint32_t value) +{ + uint32_t offset =3D 2 * pin; + uint32_t mask =3D 0xFFFFFFFF & ~(0x3 << offset); + gpio_writel(gpio, reg, (gpio_readl(gpio, reg) & mask) | value << offse= t); +} + +static unsigned int get_gpio_id(uint32_t gpio_addr) +{ + return (gpio_addr - GPIO_BASE_ADDR) / GPIO_SIZE; +} + +static void gpio_set_irq(unsigned int gpio, int num, int level) +{ + g_autofree char *name =3D g_strdup_printf("/machine/soc/gpio%c", + get_gpio_id(gpio) + 'a'); + qtest_set_irq_in(global_qtest, name, NULL, num, level); +} + +static void disconnect_all_pins(unsigned int gpio) +{ + g_autofree char *path =3D g_strdup_printf("/machine/soc/gpio%c", + get_gpio_id(gpio) + 'a'); + QDict *r; + + r =3D qtest_qmp(global_qtest, "{ 'execute': 'qom-set', 'arguments': " + "{ 'path': %s, 'property': 'disconnected-pins', 'value': %d } }", + path, 0xFFFF); + g_assert_false(qdict_haskey(r, "error")); + qobject_unref(r); +} + +static uint32_t get_disconnected_pins(unsigned int gpio) +{ + g_autofree char *path =3D g_strdup_printf("/machine/soc/gpio%c", + get_gpio_id(gpio) + 'a'); + uint32_t disconnected_pins =3D 0; + QDict *r; + + r =3D qtest_qmp(global_qtest, "{ 'execute': 'qom-get', 'arguments':" + " { 'path': %s, 'property': 'disconnected-pins'} }", path); + g_assert_false(qdict_haskey(r, "error")); + disconnected_pins =3D qdict_get_int(r, "return"); + qobject_unref(r); + return disconnected_pins; +} + +static uint32_t reset(uint32_t gpio, unsigned int offset) +{ + switch (offset) { + case MODER: + return moder_reset[get_gpio_id(gpio)]; + case PUPDR: + return pupdr_reset[get_gpio_id(gpio)]; + case IDR: + return idr_reset[get_gpio_id(gpio)]; + } + return 0x0; +} + +static void system_reset(void) +{ + QDict *r; + r =3D qtest_qmp(global_qtest, "{'execute': 'system_reset'}"); + g_assert_false(qdict_haskey(r, "error")); + qobject_unref(r); +} + +static void test_idr_reset_value(void) +{ + /* + * Checks that the values in MODER, OTYPER, PUPDR and ODR + * after reset are correct, and that the value in IDR is + * coherent. + * Since AF and analog modes aren't implemented, IDR reset + * values aren't the same as with a real board. + * + * Register IDR contains the actual values of all GPIO pins. + * Its value depends on the pins' configuration + * (intput/output/analog : register MODER, push-pull/open-drain : + * register OTYPER, pull-up/pull-down/none : register PUPDR) + * and on the values stored in register ODR + * (in case the pin is in output mode). + */ + + gpio_writel(GPIO_A, MODER, 0xDEADBEEF); + gpio_writel(GPIO_A, ODR, 0xDEADBEEF); + gpio_writel(GPIO_A, OTYPER, 0xDEADBEEF); + gpio_writel(GPIO_A, PUPDR, 0xDEADBEEF); + + gpio_writel(GPIO_B, MODER, 0xDEADBEEF); + gpio_writel(GPIO_B, ODR, 0xDEADBEEF); + gpio_writel(GPIO_B, OTYPER, 0xDEADBEEF); + gpio_writel(GPIO_B, PUPDR, 0xDEADBEEF); + + gpio_writel(GPIO_C, MODER, 0xDEADBEEF); + gpio_writel(GPIO_C, ODR, 0xDEADBEEF); + gpio_writel(GPIO_C, OTYPER, 0xDEADBEEF); + gpio_writel(GPIO_C, PUPDR, 0xDEADBEEF); + + gpio_writel(GPIO_H, MODER, 0xDEADBEEF); + gpio_writel(GPIO_H, ODR, 0xDEADBEEF); + gpio_writel(GPIO_H, OTYPER, 0xDEADBEEF); + gpio_writel(GPIO_H, PUPDR, 0xDEADBEEF); + + system_reset(); + + uint32_t moder =3D gpio_readl(GPIO_A, MODER); + uint32_t odr =3D gpio_readl(GPIO_A, ODR); + uint32_t otyper =3D gpio_readl(GPIO_A, OTYPER); + uint32_t pupdr =3D gpio_readl(GPIO_A, PUPDR); + uint32_t idr =3D gpio_readl(GPIO_A, IDR); + /* 15: AF, 14: AF, 13: AF, 12: Analog ... */ + /* here AF is the same as Analog and Input mode */ + g_assert_cmphex(moder, =3D=3D, reset(GPIO_A, MODER)); + g_assert_cmphex(odr, =3D=3D, reset(GPIO_A, ODR)); + g_assert_cmphex(otyper, =3D=3D, reset(GPIO_A, OTYPER)); + /* 15: pull-up, 14: pull-down, 13: pull-up, 12: neither ... */ + g_assert_cmphex(pupdr, =3D=3D, reset(GPIO_A, PUPDR)); + /* 15 : 1, 14: 0, 13: 1, 12 : reset value ... */ + g_assert_cmphex(idr, =3D=3D, reset(GPIO_A, IDR)); + + moder =3D gpio_readl(GPIO_B, MODER); + odr =3D gpio_readl(GPIO_B, ODR); + otyper =3D gpio_readl(GPIO_B, OTYPER); + pupdr =3D gpio_readl(GPIO_B, PUPDR); + idr =3D gpio_readl(GPIO_B, IDR); + /* ... 5: Analog, 4: AF, 3: AF, 2: Analog ... */ + /* here AF is the same as Analog and Input mode */ + g_assert_cmphex(moder, =3D=3D, reset(GPIO_B, MODER)); + g_assert_cmphex(odr, =3D=3D, reset(GPIO_B, ODR)); + g_assert_cmphex(otyper, =3D=3D, reset(GPIO_B, OTYPER)); + /* ... 5: neither, 4: pull-up, 3: neither ... */ + g_assert_cmphex(pupdr, =3D=3D, reset(GPIO_B, PUPDR)); + /* ... 5 : reset value, 4 : 1, 3 : reset value ... */ + g_assert_cmphex(idr, =3D=3D, reset(GPIO_B, IDR)); + + moder =3D gpio_readl(GPIO_C, MODER); + odr =3D gpio_readl(GPIO_C, ODR); + otyper =3D gpio_readl(GPIO_C, OTYPER); + pupdr =3D gpio_readl(GPIO_C, PUPDR); + idr =3D gpio_readl(GPIO_C, IDR); + /* Analog, same as Input mode*/ + g_assert_cmphex(moder, =3D=3D, reset(GPIO_C, MODER)); + g_assert_cmphex(odr, =3D=3D, reset(GPIO_C, ODR)); + g_assert_cmphex(otyper, =3D=3D, reset(GPIO_C, OTYPER)); + /* no pull-up or pull-down */ + g_assert_cmphex(pupdr, =3D=3D, reset(GPIO_C, PUPDR)); + /* reset value */ + g_assert_cmphex(idr, =3D=3D, reset(GPIO_C, IDR)); + + moder =3D gpio_readl(GPIO_H, MODER); + odr =3D gpio_readl(GPIO_H, ODR); + otyper =3D gpio_readl(GPIO_H, OTYPER); + pupdr =3D gpio_readl(GPIO_H, PUPDR); + idr =3D gpio_readl(GPIO_H, IDR); + /* Analog, same as Input mode */ + g_assert_cmphex(moder, =3D=3D, reset(GPIO_H, MODER)); + g_assert_cmphex(odr, =3D=3D, reset(GPIO_H, ODR)); + g_assert_cmphex(otyper, =3D=3D, reset(GPIO_H, OTYPER)); + /* no pull-up or pull-down */ + g_assert_cmphex(pupdr, =3D=3D, reset(GPIO_H, PUPDR)); + /* reset value */ + g_assert_cmphex(idr, =3D=3D, reset(GPIO_H, IDR)); +} + +static void test_gpio_output_mode(const void *data) +{ + /* + * Checks that setting a bit in ODR sets the corresponding + * GPIO line high : it should set the right bit in IDR + * and send an irq to syscfg. + * Additionally, it checks that values written to ODR + * when not in output mode are stored and not discarded. + */ + unsigned int pin =3D ((uint64_t)data) & 0xF; + uint32_t gpio =3D ((uint64_t)data) >> 32; + unsigned int gpio_id =3D get_gpio_id(gpio); + + qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg"); + + /* Set a bit in ODR and check nothing happens */ + gpio_set_bit(gpio, ODR, pin, 1); + g_assert_cmphex(gpio_readl(gpio, IDR), =3D=3D, reset(gpio, IDR)); + g_assert_false(get_irq(gpio_id * NUM_GPIO_PINS + pin)); + + /* Configure the relevant line as output and check the pin is high */ + gpio_set_2bits(gpio, MODER, pin, MODER_OUTPUT); + g_assert_cmphex(gpio_readl(gpio, IDR), =3D=3D, reset(gpio, IDR) | (1 <= < pin)); + g_assert_true(get_irq(gpio_id * NUM_GPIO_PINS + pin)); + + /* Reset the bit in ODR and check the pin is low */ + gpio_set_bit(gpio, ODR, pin, 0); + g_assert_cmphex(gpio_readl(gpio, IDR), =3D=3D, reset(gpio, IDR) & ~(1 = << pin)); + g_assert_false(get_irq(gpio_id * NUM_GPIO_PINS + pin)); + + /* Clean the test */ + gpio_writel(gpio, ODR, reset(gpio, ODR)); + gpio_writel(gpio, MODER, reset(gpio, MODER)); + g_assert_cmphex(gpio_readl(gpio, IDR), =3D=3D, reset(gpio, IDR)); + g_assert_false(get_irq(gpio_id * NUM_GPIO_PINS + pin)); +} + +static void test_gpio_input_mode(const void *data) +{ + /* + * Test that setting a line high/low externally sets the + * corresponding GPIO line high/low : it should set the + * right bit in IDR and send an irq to syscfg. + */ + unsigned int pin =3D ((uint64_t)data) & 0xF; + uint32_t gpio =3D ((uint64_t)data) >> 32; + unsigned int gpio_id =3D get_gpio_id(gpio); + + qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg"); + + /* Configure a line as input, raise it, and check that the pin is high= */ + gpio_set_2bits(gpio, MODER, pin, MODER_INPUT); + gpio_set_irq(gpio, pin, 1); + g_assert_cmphex(gpio_readl(gpio, IDR), =3D=3D, reset(gpio, IDR) | (1 <= < pin)); + g_assert_true(get_irq(gpio_id * NUM_GPIO_PINS + pin)); + + /* Lower the line and check that the pin is low */ + gpio_set_irq(gpio, pin, 0); + g_assert_cmphex(gpio_readl(gpio, IDR), =3D=3D, reset(gpio, IDR) & ~(1 = << pin)); + g_assert_false(get_irq(gpio_id * NUM_GPIO_PINS + pin)); + + /* Clean the test */ + gpio_writel(gpio, MODER, reset(gpio, MODER)); + disconnect_all_pins(gpio); + g_assert_cmphex(gpio_readl(gpio, IDR), =3D=3D, reset(gpio, IDR)); +} + +static void test_pull_up_pull_down(const void *data) +{ + /* + * Test that a floating pin with pull-up sets the pin + * high and vice-versa. + */ + unsigned int pin =3D ((uint64_t)data) & 0xF; + uint32_t gpio =3D ((uint64_t)data) >> 32; + unsigned int gpio_id =3D get_gpio_id(gpio); + + qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg"); + + /* Configure a line as input with pull-up, check the line is set high = */ + gpio_set_2bits(gpio, MODER, pin, MODER_INPUT); + gpio_set_2bits(gpio, PUPDR, pin, PUPDR_PULLUP); + g_assert_cmphex(gpio_readl(gpio, IDR), =3D=3D, reset(gpio, IDR) | (1 <= < pin)); + g_assert_true(get_irq(gpio_id * NUM_GPIO_PINS + pin)); + + /* Configure the line with pull-down, check the line is low */ + gpio_set_2bits(gpio, PUPDR, pin, PUPDR_PULLDOWN); + g_assert_cmphex(gpio_readl(gpio, IDR), =3D=3D, reset(gpio, IDR) & ~(1 = << pin)); + g_assert_false(get_irq(gpio_id * NUM_GPIO_PINS + pin)); + + /* Clean the test */ + gpio_writel(gpio, MODER, reset(gpio, MODER)); + gpio_writel(gpio, PUPDR, reset(gpio, PUPDR)); + g_assert_cmphex(gpio_readl(gpio, IDR), =3D=3D, reset(gpio, IDR)); +} + +static void test_push_pull(const void *data) +{ + /* + * Test that configuring a line in push-pull output mode + * disconnects the pin, that the pin can't be set or reset + * externally afterwards. + */ + unsigned int pin =3D ((uint64_t)data) & 0xF; + uint32_t gpio =3D ((uint64_t)data) >> 32; + uint32_t gpio2 =3D GPIO_BASE_ADDR + (GPIO_H - gpio); + + qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg"); + + /* Setting a line high externally, configuring it in push-pull output = */ + /* And checking the pin was disconnected */ + gpio_set_irq(gpio, pin, 1); + gpio_set_2bits(gpio, MODER, pin, MODER_OUTPUT); + g_assert_cmphex(get_disconnected_pins(gpio), =3D=3D, 0xFFFF); + g_assert_cmphex(gpio_readl(gpio, IDR), =3D=3D, reset(gpio, IDR) & ~(1 = << pin)); + + /* Setting a line low externally, configuring it in push-pull output */ + /* And checking the pin was disconnected */ + gpio_set_irq(gpio2, pin, 0); + gpio_set_bit(gpio2, ODR, pin, 1); + gpio_set_2bits(gpio2, MODER, pin, MODER_OUTPUT); + g_assert_cmphex(get_disconnected_pins(gpio2), =3D=3D, 0xFFFF); + g_assert_cmphex(gpio_readl(gpio2, IDR), =3D=3D, reset(gpio2, IDR) | (1= << pin)); + + /* Trying to set a push-pull output pin, checking it doesn't work */ + gpio_set_irq(gpio, pin, 1); + g_assert_cmphex(get_disconnected_pins(gpio), =3D=3D, 0xFFFF); + g_assert_cmphex(gpio_readl(gpio, IDR), =3D=3D, reset(gpio, IDR) & ~(1 = << pin)); + + /* Trying to reset a push-pull output pin, checking it doesn't work */ + gpio_set_irq(gpio2, pin, 0); + g_assert_cmphex(get_disconnected_pins(gpio2), =3D=3D, 0xFFFF); + g_assert_cmphex(gpio_readl(gpio2, IDR), =3D=3D, reset(gpio2, IDR) | (1= << pin)); + + /* Clean the test */ + gpio_writel(gpio, MODER, reset(gpio, MODER)); + gpio_writel(gpio2, ODR, reset(gpio2, ODR)); + gpio_writel(gpio2, MODER, reset(gpio2, MODER)); +} + +static void test_open_drain(const void *data) +{ + /* + * Test that configuring a line in open-drain output mode + * disconnects a pin set high externally and that the pin + * can't be set high externally while configured in open-drain. + * + * However a pin set low externally shouldn't be disconnected, + * and it can be set low externally when in open-drain mode. + */ + unsigned int pin =3D ((uint64_t)data) & 0xF; + uint32_t gpio =3D ((uint64_t)data) >> 32; + uint32_t gpio2 =3D GPIO_BASE_ADDR + (GPIO_H - gpio); + + qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg"); + + /* Setting a line high externally, configuring it in open-drain output= */ + /* And checking the pin was disconnected */ + gpio_set_irq(gpio, pin, 1); + gpio_set_bit(gpio, OTYPER, pin, OTYPER_OPEN_DRAIN); + gpio_set_2bits(gpio, MODER, pin, MODER_OUTPUT); + g_assert_cmphex(get_disconnected_pins(gpio), =3D=3D, 0xFFFF); + g_assert_cmphex(gpio_readl(gpio, IDR), =3D=3D, reset(gpio, IDR) & ~(1 = << pin)); + + /* Setting a line low externally, configuring it in open-drain output = */ + /* And checking the pin wasn't disconnected */ + gpio_set_irq(gpio2, pin, 0); + gpio_set_bit(gpio2, ODR, pin, 1); + gpio_set_bit(gpio2, OTYPER, pin, OTYPER_OPEN_DRAIN); + gpio_set_2bits(gpio2, MODER, pin, MODER_OUTPUT); + g_assert_cmphex(get_disconnected_pins(gpio2), =3D=3D, 0xFFFF & ~(1 << = pin)); + g_assert_cmphex(gpio_readl(gpio2, IDR), =3D=3D, + reset(gpio2, IDR) & ~(1 << pin)); + + /* Trying to set a open-drain output pin, checking it doesn't work */ + gpio_set_irq(gpio, pin, 1); + g_assert_cmphex(get_disconnected_pins(gpio), =3D=3D, 0xFFFF); + g_assert_cmphex(gpio_readl(gpio, IDR), =3D=3D, reset(gpio, IDR) & ~(1 = << pin)); + + /* Trying to reset a open-drain output pin, checking it works */ + gpio_set_bit(gpio, ODR, pin, 1); + gpio_set_irq(gpio, pin, 0); + g_assert_cmphex(get_disconnected_pins(gpio2), =3D=3D, 0xFFFF & ~(1 << = pin)); + g_assert_cmphex(gpio_readl(gpio2, IDR), =3D=3D, + reset(gpio2, IDR) & ~(1 << pin)); + + /* Clean the test */ + disconnect_all_pins(gpio2); + gpio_writel(gpio2, OTYPER, reset(gpio2, OTYPER)); + gpio_writel(gpio2, ODR, reset(gpio2, ODR)); + gpio_writel(gpio2, MODER, reset(gpio2, MODER)); + g_assert_cmphex(gpio_readl(gpio2, IDR), =3D=3D, reset(gpio2, IDR)); + disconnect_all_pins(gpio); + gpio_writel(gpio, OTYPER, reset(gpio, OTYPER)); + gpio_writel(gpio, ODR, reset(gpio, ODR)); + gpio_writel(gpio, MODER, reset(gpio, MODER)); + g_assert_cmphex(gpio_readl(gpio, IDR), =3D=3D, reset(gpio, IDR)); +} + +static void test_bsrr_brr(const void *data) +{ + /* + * Test that writing a '1' in BSS and BSRR + * has the desired effect on ODR. + * In BSRR, BSx has priority over BRx. + */ + unsigned int pin =3D ((uint64_t)data) & 0xF; + uint32_t gpio =3D ((uint64_t)data) >> 32; + + gpio_writel(gpio, BSRR, (1 << pin)); + g_assert_cmphex(gpio_readl(gpio, ODR), =3D=3D, reset(gpio, ODR) | (1 <= < pin)); + + gpio_writel(gpio, BSRR, (1 << (pin + NUM_GPIO_PINS))); + g_assert_cmphex(gpio_readl(gpio, ODR), =3D=3D, reset(gpio, ODR)); + + gpio_writel(gpio, BSRR, (1 << pin)); + g_assert_cmphex(gpio_readl(gpio, ODR), =3D=3D, reset(gpio, ODR) | (1 <= < pin)); + + gpio_writel(gpio, BRR, (1 << pin)); + g_assert_cmphex(gpio_readl(gpio, ODR), =3D=3D, reset(gpio, ODR)); + + /* BSx should have priority over BRx */ + gpio_writel(gpio, BSRR, (1 << pin) | (1 << (pin + NUM_GPIO_PINS))); + g_assert_cmphex(gpio_readl(gpio, ODR), =3D=3D, reset(gpio, ODR) | (1 <= < pin)); + + gpio_writel(gpio, BRR, (1 << pin)); + g_assert_cmphex(gpio_readl(gpio, ODR), =3D=3D, reset(gpio, ODR)); + + gpio_writel(gpio, ODR, reset(gpio, ODR)); +} + +int main(int argc, char **argv) +{ + int ret; + + g_test_init(&argc, &argv, NULL); + g_test_set_nonfatal_assertions(); + qtest_add_func("stm32l4x5/gpio/test_idr_reset_value", + test_idr_reset_value); + /* + * The inputs for the tests (gpio and pin) can be changed, + * but the tests don't work for pins that are high at reset + * (GPIOA15, GPIO13 and GPIOB5). + * Specifically, rising the pin then checking `get_irq()` + * is problematic since the pin was already high. + */ + qtest_add_data_func("stm32l4x5/gpio/test_gpioc5_output_mode", + (void *)((uint64_t)GPIO_C << 32 | 5), + test_gpio_output_mode); + qtest_add_data_func("stm32l4x5/gpio/test_gpioh3_output_mode", + (void *)((uint64_t)GPIO_H << 32 | 3), + test_gpio_output_mode); + qtest_add_data_func("stm32l4x5/gpio/test_gpio_input_mode1", + (void *)((uint64_t)GPIO_D << 32 | 6), + test_gpio_input_mode); + qtest_add_data_func("stm32l4x5/gpio/test_gpio_input_mode2", + (void *)((uint64_t)GPIO_C << 32 | 10), + test_gpio_input_mode); + qtest_add_data_func("stm32l4x5/gpio/test_gpio_pull_up_pull_down1", + (void *)((uint64_t)GPIO_B << 32 | 5), + test_pull_up_pull_down); + qtest_add_data_func("stm32l4x5/gpio/test_gpio_pull_up_pull_down2", + (void *)((uint64_t)GPIO_F << 32 | 1), + test_pull_up_pull_down); + qtest_add_data_func("stm32l4x5/gpio/test_gpio_push_pull1", + (void *)((uint64_t)GPIO_G << 32 | 6), + test_push_pull); + qtest_add_data_func("stm32l4x5/gpio/test_gpio_push_pull2", + (void *)((uint64_t)GPIO_H << 32 | 3), + test_push_pull); + qtest_add_data_func("stm32l4x5/gpio/test_gpio_open_drain1", + (void *)((uint64_t)GPIO_C << 32 | 4), + test_open_drain); + qtest_add_data_func("stm32l4x5/gpio/test_gpio_open_drain2", + (void *)((uint64_t)GPIO_E << 32 | 11), + test_open_drain); + qtest_add_data_func("stm32l4x5/gpio/test_bsrr_brr1", + (void *)((uint64_t)GPIO_A << 32 | 12), + test_bsrr_brr); + qtest_add_data_func("stm32l4x5/gpio/test_bsrr_brr2", + (void *)((uint64_t)GPIO_D << 32 | 0), + test_bsrr_brr); + + qtest_start("-machine b-l475e-iot01a"); + ret =3D g_test_run(); + qtest_end(); + + return ret; +} diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index 31b9f4ede47..36c5c13a7bb 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -204,7 +204,8 @@ qtests_aspeed =3D \ qtests_stm32l4x5 =3D \ ['stm32l4x5_exti-test', 'stm32l4x5_syscfg-test', - 'stm32l4x5_rcc-test'] + 'stm32l4x5_rcc-test', + 'stm32l4x5_gpio-test'] =20 qtests_arm =3D \ (config_all_devices.has_key('CONFIG_MPS2') ? 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f2-20020adff8c2000000b0033e7a204dc7sm856080wrq.32.2024.03.08.07.50.21 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Mar 2024 07:50:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1709913022; x=1710517822; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=fVPAJQfr3UN8BQVOQpbEDXWDjmrmqgXmlBWCciOmKMk=; b=gQ9lL76VyT6JmRYqIpn+SdW8T43ZJ1aoYpSZ74Q8DJayHQSwNTpa2f1+EBhVzipIx1 jWDXjhF/VnI+px6lbJaniIy/Utc9M+UHS4ZVBemchkH5X1SGhQOyfXFW9BEw5tWauvYX Q3DTyrDEQHdzcLp2xCDwVAWP99x0c+1Tn4zypN6cUaeMs4TKQgiPNF//hTS0G9/Ro90S YSR2AN7AuqGBoGdUIdr6T53qtWw503wiKDzVGnFR1vSmrbxIxuF8FQrA6xoeEKAHYj9F qYemb1bhjj1A4zfEKF/ZbrDnH/ha94pLKpWO8xcRiV8Xdgm3d9bpLpShNG30PWXok1uF 0MCA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1709913022; x=1710517822; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fVPAJQfr3UN8BQVOQpbEDXWDjmrmqgXmlBWCciOmKMk=; b=bzT4igmMCNLsmORmF7dJGfCKHWdeIgsPdDnI0Jmcxlq2288hwsJ2YFltpcOp8y50sN ruZ7zKAYzZQUGoONRH5sc4pmRknWCp/9El/25CTZ9BzrlN5Rj74J39vFLB4csahCAhhw EUzRDSZeW/CY9ANmM3BHQ8yn9JjvF5xc4mSRITvXbIH6+jfRq6XuvHDcvbit3DW26uTE ODxdcYzyjAA7As4C2Q+Iueej/iNd3IeWvDCG+vsJ+XDgBaDf8cAxxqe0qxR2GAPKLsxL ptvqS3/npWfZgRcJ6L2j/Ra5EllZTRmWxur/vYSfrauPaoJYuutzH9UFmRp30hWnfRUg ufpA== X-Gm-Message-State: AOJu0YzCwNGFkAMQprOdGpPag3SG65SSNrSfj/rqVdCBilWkMW+lXjEE YyjY2gI77LBjNf4fxvMUkKAmNOoSejriynYJSjVenWopt6wh47oU/2UrbIhHUruN10bhJ1Gh58a C X-Google-Smtp-Source: AGHT+IHvOIfSDGqw/+2cXASyQ5cY9dasj3E5UVHzlAw0+GG2hkZyiim4hCQ3gZ0Ra0obeLzZ5thOjA== X-Received: by 2002:a05:6512:543:b0:513:816d:464f with SMTP id h3-20020a056512054300b00513816d464fmr3419606lfl.62.1709913022161; Fri, 08 Mar 2024 07:50:22 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 12/14] target/arm: Fix 32-bit SMOPA Date: Fri, 8 Mar 2024 15:50:13 +0000 Message-Id: <20240308155015.3637663-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240308155015.3637663-1-peter.maydell@linaro.org> References: <20240308155015.3637663-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::131; envelope-from=peter.maydell@linaro.org; helo=mail-lf1-x131.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1709913038491100016 From: Richard Henderson While the 8-bit input elements are sequential in the input vector, the 32-bit output elements are not sequential in the output matrix. Do not attempt to compute 2 32-bit outputs at the same time. Cc: qemu-stable@nongnu.org Fixes: 23a5e3859f5 ("target/arm: Implement SME integer outer product") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2083 Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20240305163931.242795-1-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/sme_helper.c | 77 ++++++++++++++++++------------- tests/tcg/aarch64/sme-smopa-1.c | 47 +++++++++++++++++++ tests/tcg/aarch64/sme-smopa-2.c | 54 ++++++++++++++++++++++ tests/tcg/aarch64/Makefile.target | 2 +- 4 files changed, 147 insertions(+), 33 deletions(-) create mode 100644 tests/tcg/aarch64/sme-smopa-1.c create mode 100644 tests/tcg/aarch64/sme-smopa-2.c diff --git a/target/arm/tcg/sme_helper.c b/target/arm/tcg/sme_helper.c index 904bfdac43e..e2e05750399 100644 --- a/target/arm/tcg/sme_helper.c +++ b/target/arm/tcg/sme_helper.c @@ -1083,11 +1083,32 @@ void HELPER(sme_bfmopa)(void *vza, void *vzn, void = *vzm, void *vpn, } } =20 -typedef uint64_t IMOPFn(uint64_t, uint64_t, uint64_t, uint8_t, bool); +typedef uint32_t IMOPFn32(uint32_t, uint32_t, uint32_t, uint8_t, bool); +static inline void do_imopa_s(uint32_t *za, uint32_t *zn, uint32_t *zm, + uint8_t *pn, uint8_t *pm, + uint32_t desc, IMOPFn32 *fn) +{ + intptr_t row, col, oprsz =3D simd_oprsz(desc) / 4; + bool neg =3D simd_data(desc); =20 -static inline void do_imopa(uint64_t *za, uint64_t *zn, uint64_t *zm, - uint8_t *pn, uint8_t *pm, - uint32_t desc, IMOPFn *fn) + for (row =3D 0; row < oprsz; ++row) { + uint8_t pa =3D (pn[H1(row >> 1)] >> ((row & 1) * 4)) & 0xf; + uint32_t *za_row =3D &za[tile_vslice_index(row)]; + uint32_t n =3D zn[H4(row)]; + + for (col =3D 0; col < oprsz; ++col) { + uint8_t pb =3D pm[H1(col >> 1)] >> ((col & 1) * 4); + uint32_t *a =3D &za_row[H4(col)]; + + *a =3D fn(n, zm[H4(col)], *a, pa & pb, neg); + } + } +} + +typedef uint64_t IMOPFn64(uint64_t, uint64_t, uint64_t, uint8_t, bool); +static inline void do_imopa_d(uint64_t *za, uint64_t *zn, uint64_t *zm, + uint8_t *pn, uint8_t *pm, + uint32_t desc, IMOPFn64 *fn) { intptr_t row, col, oprsz =3D simd_oprsz(desc) / 8; bool neg =3D simd_data(desc); @@ -1107,25 +1128,16 @@ static inline void do_imopa(uint64_t *za, uint64_t = *zn, uint64_t *zm, } =20 #define DEF_IMOP_32(NAME, NTYPE, MTYPE) \ -static uint64_t NAME(uint64_t n, uint64_t m, uint64_t a, uint8_t p, bool n= eg) \ +static uint32_t NAME(uint32_t n, uint32_t m, uint32_t a, uint8_t p, bool n= eg) \ { = \ - uint32_t sum0 =3D 0, sum1 =3D 0; = \ + uint32_t sum =3D 0; = \ /* Apply P to N as a mask, making the inactive elements 0. */ = \ n &=3D expand_pred_b(p); = \ - sum0 +=3D (NTYPE)(n >> 0) * (MTYPE)(m >> 0); = \ - sum0 +=3D (NTYPE)(n >> 8) * (MTYPE)(m >> 8); = \ - sum0 +=3D (NTYPE)(n >> 16) * (MTYPE)(m >> 16); = \ - sum0 +=3D (NTYPE)(n >> 24) * (MTYPE)(m >> 24); = \ - sum1 +=3D (NTYPE)(n >> 32) * (MTYPE)(m >> 32); = \ - sum1 +=3D (NTYPE)(n >> 40) * (MTYPE)(m >> 40); = \ - sum1 +=3D (NTYPE)(n >> 48) * (MTYPE)(m >> 48); = \ - sum1 +=3D (NTYPE)(n >> 56) * (MTYPE)(m >> 56); = \ - if (neg) { = \ - sum0 =3D (uint32_t)a - sum0, sum1 =3D (uint32_t)(a >> 32) - sum1; = \ - } else { = \ - sum0 =3D (uint32_t)a + sum0, sum1 =3D (uint32_t)(a >> 32) + sum1; = \ - } = \ - return ((uint64_t)sum1 << 32) | sum0; = \ + sum +=3D (NTYPE)(n >> 0) * (MTYPE)(m >> 0); = \ + sum +=3D (NTYPE)(n >> 8) * (MTYPE)(m >> 8); = \ + sum +=3D (NTYPE)(n >> 16) * (MTYPE)(m >> 16); = \ + sum +=3D (NTYPE)(n >> 24) * (MTYPE)(m >> 24); = \ + return neg ? a - sum : a + sum; = \ } =20 #define DEF_IMOP_64(NAME, NTYPE, MTYPE) \ @@ -1151,16 +1163,17 @@ DEF_IMOP_64(umopa_d, uint16_t, uint16_t) DEF_IMOP_64(sumopa_d, int16_t, uint16_t) DEF_IMOP_64(usmopa_d, uint16_t, int16_t) =20 -#define DEF_IMOPH(NAME) \ - void HELPER(sme_##NAME)(void *vza, void *vzn, void *vzm, void *vpn, = \ - void *vpm, uint32_t desc) = \ - { do_imopa(vza, vzn, vzm, vpn, vpm, desc, NAME); } +#define DEF_IMOPH(NAME, S) \ + void HELPER(sme_##NAME##_##S)(void *vza, void *vzn, void *vzm, = \ + void *vpn, void *vpm, uint32_t desc) = \ + { do_imopa_##S(vza, vzn, vzm, vpn, vpm, desc, NAME##_##S); } =20 -DEF_IMOPH(smopa_s) -DEF_IMOPH(umopa_s) -DEF_IMOPH(sumopa_s) -DEF_IMOPH(usmopa_s) -DEF_IMOPH(smopa_d) -DEF_IMOPH(umopa_d) -DEF_IMOPH(sumopa_d) -DEF_IMOPH(usmopa_d) +DEF_IMOPH(smopa, s) +DEF_IMOPH(umopa, s) +DEF_IMOPH(sumopa, s) +DEF_IMOPH(usmopa, s) + +DEF_IMOPH(smopa, d) +DEF_IMOPH(umopa, d) +DEF_IMOPH(sumopa, d) +DEF_IMOPH(usmopa, d) diff --git a/tests/tcg/aarch64/sme-smopa-1.c b/tests/tcg/aarch64/sme-smopa-= 1.c new file mode 100644 index 00000000000..c62d5e00073 --- /dev/null +++ b/tests/tcg/aarch64/sme-smopa-1.c @@ -0,0 +1,47 @@ +#include +#include + +int main() +{ + static const int cmp[4][4] =3D { + { 110, 134, 158, 182 }, + { 390, 478, 566, 654 }, + { 670, 822, 974, 1126 }, + { 950, 1166, 1382, 1598 } + }; + int dst[4][4]; + int *tmp =3D &dst[0][0]; + + asm volatile( + ".arch armv8-r+sme\n\t" + "smstart\n\t" + "index z0.b, #0, #1\n\t" + "movprfx z1, z0\n\t" + "add z1.b, z1.b, #16\n\t" + "ptrue p0.b\n\t" + "smopa za0.s, p0/m, p0/m, z0.b, z1.b\n\t" + "ptrue p0.s, vl4\n\t" + "mov w12, #0\n\t" + "st1w { za0h.s[w12, #0] }, p0, [%0]\n\t" + "add %0, %0, #16\n\t" + "st1w { za0h.s[w12, #1] }, p0, [%0]\n\t" + "add %0, %0, #16\n\t" + "st1w { za0h.s[w12, #2] }, p0, [%0]\n\t" + "add %0, %0, #16\n\t" + "st1w { za0h.s[w12, #3] }, p0, [%0]\n\t" + "smstop" + : "+r"(tmp) : : "memory"); + + if (memcmp(cmp, dst, sizeof(dst)) =3D=3D 0) { + return 0; + } + + /* See above for correct results. */ + for (int i =3D 0; i < 4; ++i) { + for (int j =3D 0; j < 4; ++j) { + printf("%6d", dst[i][j]); + } + printf("\n"); + } + return 1; +} diff --git a/tests/tcg/aarch64/sme-smopa-2.c b/tests/tcg/aarch64/sme-smopa-= 2.c new file mode 100644 index 00000000000..c9f48c3bfca --- /dev/null +++ b/tests/tcg/aarch64/sme-smopa-2.c @@ -0,0 +1,54 @@ +#include +#include + +int main() +{ + static const long cmp[4][4] =3D { + { 110, 134, 158, 182 }, + { 390, 478, 566, 654 }, + { 670, 822, 974, 1126 }, + { 950, 1166, 1382, 1598 } + }; + long dst[4][4]; + long *tmp =3D &dst[0][0]; + long svl; + + /* Validate that we have a wide enough vector for 4 elements. */ + asm(".arch armv8-r+sme-i64\n\trdsvl %0, #1" : "=3Dr"(svl)); + if (svl < 32) { + return 0; + } + + asm volatile( + "smstart\n\t" + "index z0.h, #0, #1\n\t" + "movprfx z1, z0\n\t" + "add z1.h, z1.h, #16\n\t" + "ptrue p0.b\n\t" + "smopa za0.d, p0/m, p0/m, z0.h, z1.h\n\t" + "ptrue p0.d, vl4\n\t" + "mov w12, #0\n\t" + "st1d { za0h.d[w12, #0] }, p0, [%0]\n\t" + "add %0, %0, #32\n\t" + "st1d { za0h.d[w12, #1] }, p0, [%0]\n\t" + "mov w12, #2\n\t" + "add %0, %0, #32\n\t" + "st1d { za0h.d[w12, #0] }, p0, [%0]\n\t" + "add %0, %0, #32\n\t" + "st1d { za0h.d[w12, #1] }, p0, [%0]\n\t" + "smstop" + : "+r"(tmp) : : "memory"); + + if (memcmp(cmp, dst, sizeof(dst)) =3D=3D 0) { + return 0; + } + + /* See above for correct results. */ + for (int i =3D 0; i < 4; ++i) { + for (int j =3D 0; j < 4; ++j) { + printf("%6ld", dst[i][j]); + } + printf("\n"); + } + return 1; +} diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile= .target index cded1d01fcd..ea3e232e65f 100644 --- a/tests/tcg/aarch64/Makefile.target +++ b/tests/tcg/aarch64/Makefile.target @@ -67,7 +67,7 @@ endif =20 # SME Tests ifneq ($(CROSS_AS_HAS_ARMV9_SME),) -AARCH64_TESTS +=3D sme-outprod1 +AARCH64_TESTS +=3D sme-outprod1 sme-smopa-1 sme-smopa-2 endif =20 # System Registers Tests --=20 2.34.1 From nobody Fri May 10 18:36:38 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f2-20020adff8c2000000b0033e7a204dc7sm856080wrq.32.2024.03.08.07.50.22 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Mar 2024 07:50:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1709913022; x=1710517822; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=xCyKHrVDgE4duKvrjOPXtlhJ/eSl12oKbAB88FqLRxs=; b=n2py2XLKL48r2h1l8Tg05eE8L0IzMaRqDsuVCVYHXPzavLiT23/xnrJAogNT2Kvm6p VkqeXmloPgpXdeTmJ4tsMc+8mQqSofiH7clZpj1ORqEm2P3qhlpIRiwkW1sW0Twt/qqD uaI8TncLEWTZy9zb/GQzOoqspJIvcCs/PmOokZN3ST/y0UOLKZySRSkJSE/VxRfiNW45 o7MM0bjwPTeSQC28sso38hBzJeu2hhONengimG5ItbfPPbW+xnU/mBosD8iTk0qTHVcI p1yk5kj7PRxSaiHqKizV8Vf6+yVrZG2Cn1AIAMZ4E0JIDjFce6YDih7pzSl2ILrVVJTi tYfA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1709913022; x=1710517822; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xCyKHrVDgE4duKvrjOPXtlhJ/eSl12oKbAB88FqLRxs=; b=UI/WDX2h5A4tEHRu/ztqOMhU2Wu3OwftSsI73pwmJARp2jnt9C/+MLWDdUj2tqE+0e HLz2eYIruKBCkWunscrC6IAxGPMwEORS7YVkYa4NzLDChzpHkJ6Vr4CCadCm8PZDEGs4 r/ssQe34OhC/QU5/2kh9ZSFdfUriUvH0N+LJdnVZa2GlOp9rBXR5J6tknz6u71Lf2BXl Viv1isYHdoCvZRFGdEDBt1GAJKue8+QHh2QGPVKVBYtgmU8HBZbpEv/q3IoAggzgWwS2 XodgYMXRe2XfEK0SNxPgMI6juM9qgfDIB5gJFiZJcwOqzjieJh3JdBcPf/o+eK4Wp8PN 4hFw== X-Gm-Message-State: AOJu0YwE0p+wVhf7Kg5cZJ41PoDALURRA88nduaUMpyV3Hb/XEpX0cY+ w8igiyKk4XUgGzoP46p5Y9zK60ePGR0RsJ9NNsxkfaYUx9XoF0GyGVOfrCg2P9+OvMfB6ZXGdN6 Q X-Google-Smtp-Source: AGHT+IEfkfBvQVWMgt8dCRSYT3dMtqU1gLjEAWOhwGXdkleyti3FAxugEJ1k4NZ1OYfbT2lvikohUg== X-Received: by 2002:a5d:5a03:0:b0:33e:737c:792a with SMTP id bq3-20020a5d5a03000000b0033e737c792amr3943479wrb.68.1709913022592; Fri, 08 Mar 2024 07:50:22 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 13/14] hw/rtc/sun4v-rtc: Relicense to GPLv2-or-later Date: Fri, 8 Mar 2024 15:50:14 +0000 Message-Id: <20240308155015.3637663-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240308155015.3637663-1-peter.maydell@linaro.org> References: <20240308155015.3637663-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1709913177060100011 The sun4v RTC device model added under commit a0e893039cf2ce0 in 2016 was unfortunately added with a license of GPL-v3-or-later, which is not compatible with other QEMU code which has a GPL-v2-only license. Relicense the code in the .c and the .h file to GPL-v2-or-later, to make it compatible with the rest of QEMU. Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell Signed-off-by: Paolo Bonzini (for Red Hat) Signed-off-by: Artyom Tarasenko Signed-off-by: Markus Armbruster Signed-off-by: Alex Benn=C3=A9e Signed-off-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Daniel P. Berrang=C3=A9 Acked-by: Alex Benn=C3=A9e Message-id: 20240223161300.938542-1-peter.maydell@linaro.org Signed-off-by: Peter Maydell --- include/hw/rtc/sun4v-rtc.h | 2 +- hw/rtc/sun4v-rtc.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/include/hw/rtc/sun4v-rtc.h b/include/hw/rtc/sun4v-rtc.h index fc54dfcba47..26a9eb61967 100644 --- a/include/hw/rtc/sun4v-rtc.h +++ b/include/hw/rtc/sun4v-rtc.h @@ -5,7 +5,7 @@ * * Copyright (c) 2016 Artyom Tarasenko * - * This code is licensed under the GNU GPL v3 or (at your option) any later + * This code is licensed under the GNU GPL v2 or (at your option) any later * version. */ =20 diff --git a/hw/rtc/sun4v-rtc.c b/hw/rtc/sun4v-rtc.c index e037acd1b56..ffcc0aa25d9 100644 --- a/hw/rtc/sun4v-rtc.c +++ b/hw/rtc/sun4v-rtc.c @@ -5,7 +5,7 @@ * * Copyright (c) 2016 Artyom Tarasenko * - * This code is licensed under the GNU GPL v3 or (at your option) any later + * This code is licensed under the GNU GPL v2 or (at your option) any later * version. */ =20 --=20 2.34.1 From nobody Fri May 10 18:36:38 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1709913119; cv=none; d=zohomail.com; s=zohoarc; b=gu9M53rmTi/5MmtkAop+vWoMOiG/aFdImdL0NBBlLgM2MAB3k90WKJOFUJjA2jcOxsTXvmEGDNkqojVlIsoehjulWUH9Y6P+uKtijBv7hB/FRas1eeOWXVHZMTZ/qPEupj27Zi5TlmvCoChGw2EHkloTkT/L3YFO1XrwA2NcvGk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1709913119; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=hmftZX3Zj82jjyaQWolpMdQ7OIw0Yvxx8kXPvP7QUE0=; b=NX6a49nXE+714VvU4dfjg7ghdK1IVUDEqurBhHu1bRPHlAdwToEicCnjVTDBp19MPQUer7AquwMSVUXjHwA+WUUDCJEl05TN8JDYV62N7U+mWjWzTuIDc+0wocwPM4qxLLJFxLMfyfFELOeiBtnWt9PQv3Yi4/5Yp0slE7sGBa4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1709913119336996.1882946654937; Fri, 8 Mar 2024 07:51:59 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ricUh-0000El-Ow; Fri, 08 Mar 2024 10:50:50 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ricUR-0007yq-Db for qemu-devel@nongnu.org; Fri, 08 Mar 2024 10:50:31 -0500 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ricUK-0004Ud-KP for qemu-devel@nongnu.org; Fri, 08 Mar 2024 10:50:31 -0500 Received: by mail-wr1-x430.google.com with SMTP id ffacd0b85a97d-33e76d653b5so703382f8f.3 for ; Fri, 08 Mar 2024 07:50:24 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f2-20020adff8c2000000b0033e7a204dc7sm856080wrq.32.2024.03.08.07.50.22 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Mar 2024 07:50:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1709913023; x=1710517823; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=hmftZX3Zj82jjyaQWolpMdQ7OIw0Yvxx8kXPvP7QUE0=; b=nbSE+ZkIrxBK2rPAd4u8GcJRpkg9OzeAUjkzdKLs1sWpj97lLdxhl0q6zyaZQGuc+3 awDFHj0N64hlwnozPOJNe/LRGUXlDiOaRz6QWI/NLpOaKOrAIodSjcRAobITCa5hbBL3 OKxFbg+hjxA+sZGsUdqHVbZK656TmX3WSfGvw7nIBWATxUc1utX7aNSYjhitxmZ1vTlC Ddbey/qQo1Bn7v40idkuaMKdgmi8zq5IkojxJH4k4kIamHTqhraiO9OW0c35O44BmROl glu8QqyEPR/hI9o/eVpVwDcDNKLMIQoP8A3ckVxFgY33ErpOHBXk4WSPp25H8Y1qKEAA EuUA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1709913023; x=1710517823; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hmftZX3Zj82jjyaQWolpMdQ7OIw0Yvxx8kXPvP7QUE0=; b=QnGNunRxsXK8hbD5jwfKQmSJcaql4Ew5477zpqfTrl8EvJAr4n+ai5lv/RKcx7vGNc KWwRHTz6qa9s9Mu079DBaa/SXBk5sn4LRidPQDbT6meEWZDIXw5+DugJKDpednCXwLQJ CuhwbG86Ks4LVRficijGPo8HgpY1l7QVZCP354rX+U6WE84CdnW83Qp6wQNhXxC6H7XL UwmnR672UknppzPjb/eIGxfUhtx8uEQ7UP6DLrsoeggGDLA+nwmrQxHlI+jIJmSelsb8 uyEVLLkXuJG7+DYTMabBDHAaqiwcjUImMDH0Ii4PVJ7QjBb4BsvhLKll1ivwRzeCJ0Bp hOAw== X-Gm-Message-State: AOJu0Yz7qWp6zCFQtl/VKbtanw+3uo2tpcOT4ow+SmknjMdZBpRnpX+F buPKqmBKkh+Mtha0atJRf2xpslFRVONSaM40ZS60HGoM/AfB8uPZ5yUKxRJmTSrXyc8s0xL54fZ N X-Google-Smtp-Source: AGHT+IHF52lPXJ9Om8UzQKuzjKro/htNGaelkUYeqG75Y6WDa85VeGQbE9zXORU8WX/vBS9aT8VK0A== X-Received: by 2002:adf:fc8e:0:b0:33d:284a:401 with SMTP id g14-20020adffc8e000000b0033d284a0401mr16087862wrr.68.1709913023001; Fri, 08 Mar 2024 07:50:23 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 14/14] target/arm: Move v7m-related code from cpu32.c into a separate file Date: Fri, 8 Mar 2024 15:50:15 +0000 Message-Id: <20240308155015.3637663-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240308155015.3637663-1-peter.maydell@linaro.org> References: <20240308155015.3637663-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1709913120839100001 Content-Type: text/plain; charset="utf-8" From: Thomas Huth Move the code to a separate file so that we do not have to compile it anymore if CONFIG_ARM_V7M is not set. Signed-off-by: Thomas Huth Message-id: 20240308141051.536599-2-thuth@redhat.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/tcg/cpu-v7m.c | 290 +++++++++++++++++++++++++++++++++++++ target/arm/tcg/cpu32.c | 261 --------------------------------- target/arm/meson.build | 3 + target/arm/tcg/meson.build | 3 + 4 files changed, 296 insertions(+), 261 deletions(-) create mode 100644 target/arm/tcg/cpu-v7m.c diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c new file mode 100644 index 00000000000..c059c681e94 --- /dev/null +++ b/target/arm/tcg/cpu-v7m.c @@ -0,0 +1,290 @@ +/* + * QEMU ARMv7-M TCG-only CPUs. + * + * Copyright (c) 2012 SUSE LINUX Products GmbH + * + * This code is licensed under the GNU GPL v2 or later. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "hw/core/tcg-cpu-ops.h" +#include "internals.h" + +#if !defined(CONFIG_USER_ONLY) + +#include "hw/intc/armv7m_nvic.h" + +static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request) +{ + CPUClass *cc =3D CPU_GET_CLASS(cs); + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + bool ret =3D false; + + /* + * ARMv7-M interrupt masking works differently than -A or -R. + * There is no FIQ/IRQ distinction. Instead of I and F bits + * masking FIQ and IRQ interrupts, an exception is taken only + * if it is higher priority than the current execution priority + * (which depends on state like BASEPRI, FAULTMASK and the + * currently active exception). + */ + if (interrupt_request & CPU_INTERRUPT_HARD + && (armv7m_nvic_can_take_pending_exception(env->nvic))) { + cs->exception_index =3D EXCP_IRQ; + cc->tcg_ops->do_interrupt(cs); + ret =3D true; + } + return ret; +} + +#endif /* !CONFIG_USER_ONLY */ + +static void cortex_m0_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + set_feature(&cpu->env, ARM_FEATURE_V6); + set_feature(&cpu->env, ARM_FEATURE_M); + + cpu->midr =3D 0x410cc200; + + /* + * These ID register values are not guest visible, because + * we do not implement the Main Extension. They must be set + * to values corresponding to the Cortex-M0's implemented + * features, because QEMU generally controls its emulation + * by looking at ID register fields. We use the same values as + * for the M3. + */ + cpu->isar.id_pfr0 =3D 0x00000030; + cpu->isar.id_pfr1 =3D 0x00000200; + cpu->isar.id_dfr0 =3D 0x00100000; + cpu->id_afr0 =3D 0x00000000; + cpu->isar.id_mmfr0 =3D 0x00000030; + cpu->isar.id_mmfr1 =3D 0x00000000; + cpu->isar.id_mmfr2 =3D 0x00000000; + cpu->isar.id_mmfr3 =3D 0x00000000; + cpu->isar.id_isar0 =3D 0x01141110; + cpu->isar.id_isar1 =3D 0x02111000; + cpu->isar.id_isar2 =3D 0x21112231; + cpu->isar.id_isar3 =3D 0x01111110; + cpu->isar.id_isar4 =3D 0x01310102; + cpu->isar.id_isar5 =3D 0x00000000; + cpu->isar.id_isar6 =3D 0x00000000; +} + +static void cortex_m3_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + set_feature(&cpu->env, ARM_FEATURE_V7); + set_feature(&cpu->env, ARM_FEATURE_M); + set_feature(&cpu->env, ARM_FEATURE_M_MAIN); + cpu->midr =3D 0x410fc231; + cpu->pmsav7_dregion =3D 8; + cpu->isar.id_pfr0 =3D 0x00000030; + cpu->isar.id_pfr1 =3D 0x00000200; + cpu->isar.id_dfr0 =3D 0x00100000; + cpu->id_afr0 =3D 0x00000000; + cpu->isar.id_mmfr0 =3D 0x00000030; + cpu->isar.id_mmfr1 =3D 0x00000000; + cpu->isar.id_mmfr2 =3D 0x00000000; + cpu->isar.id_mmfr3 =3D 0x00000000; + cpu->isar.id_isar0 =3D 0x01141110; + cpu->isar.id_isar1 =3D 0x02111000; + cpu->isar.id_isar2 =3D 0x21112231; + cpu->isar.id_isar3 =3D 0x01111110; + cpu->isar.id_isar4 =3D 0x01310102; + cpu->isar.id_isar5 =3D 0x00000000; + cpu->isar.id_isar6 =3D 0x00000000; +} + +static void cortex_m4_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + set_feature(&cpu->env, ARM_FEATURE_V7); + set_feature(&cpu->env, ARM_FEATURE_M); + set_feature(&cpu->env, ARM_FEATURE_M_MAIN); + set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); + cpu->midr =3D 0x410fc240; /* r0p0 */ + cpu->pmsav7_dregion =3D 8; + cpu->isar.mvfr0 =3D 0x10110021; + cpu->isar.mvfr1 =3D 0x11000011; + cpu->isar.mvfr2 =3D 0x00000000; + cpu->isar.id_pfr0 =3D 0x00000030; + cpu->isar.id_pfr1 =3D 0x00000200; + cpu->isar.id_dfr0 =3D 0x00100000; + cpu->id_afr0 =3D 0x00000000; + cpu->isar.id_mmfr0 =3D 0x00000030; + cpu->isar.id_mmfr1 =3D 0x00000000; + cpu->isar.id_mmfr2 =3D 0x00000000; + cpu->isar.id_mmfr3 =3D 0x00000000; + cpu->isar.id_isar0 =3D 0x01141110; + cpu->isar.id_isar1 =3D 0x02111000; + cpu->isar.id_isar2 =3D 0x21112231; + cpu->isar.id_isar3 =3D 0x01111110; + cpu->isar.id_isar4 =3D 0x01310102; + cpu->isar.id_isar5 =3D 0x00000000; + cpu->isar.id_isar6 =3D 0x00000000; +} + +static void cortex_m7_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + set_feature(&cpu->env, ARM_FEATURE_V7); + set_feature(&cpu->env, ARM_FEATURE_M); + set_feature(&cpu->env, ARM_FEATURE_M_MAIN); + set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); + cpu->midr =3D 0x411fc272; /* r1p2 */ + cpu->pmsav7_dregion =3D 8; + cpu->isar.mvfr0 =3D 0x10110221; + cpu->isar.mvfr1 =3D 0x12000011; + cpu->isar.mvfr2 =3D 0x00000040; + cpu->isar.id_pfr0 =3D 0x00000030; + cpu->isar.id_pfr1 =3D 0x00000200; + cpu->isar.id_dfr0 =3D 0x00100000; + cpu->id_afr0 =3D 0x00000000; + cpu->isar.id_mmfr0 =3D 0x00100030; + cpu->isar.id_mmfr1 =3D 0x00000000; + cpu->isar.id_mmfr2 =3D 0x01000000; + cpu->isar.id_mmfr3 =3D 0x00000000; + cpu->isar.id_isar0 =3D 0x01101110; + cpu->isar.id_isar1 =3D 0x02112000; + cpu->isar.id_isar2 =3D 0x20232231; + cpu->isar.id_isar3 =3D 0x01111131; + cpu->isar.id_isar4 =3D 0x01310132; + cpu->isar.id_isar5 =3D 0x00000000; + cpu->isar.id_isar6 =3D 0x00000000; +} + +static void cortex_m33_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + set_feature(&cpu->env, ARM_FEATURE_V8); + set_feature(&cpu->env, ARM_FEATURE_M); + set_feature(&cpu->env, ARM_FEATURE_M_MAIN); + set_feature(&cpu->env, ARM_FEATURE_M_SECURITY); + set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); + cpu->midr =3D 0x410fd213; /* r0p3 */ + cpu->pmsav7_dregion =3D 16; + cpu->sau_sregion =3D 8; + cpu->isar.mvfr0 =3D 0x10110021; + cpu->isar.mvfr1 =3D 0x11000011; + cpu->isar.mvfr2 =3D 0x00000040; + cpu->isar.id_pfr0 =3D 0x00000030; + cpu->isar.id_pfr1 =3D 0x00000210; + cpu->isar.id_dfr0 =3D 0x00200000; + cpu->id_afr0 =3D 0x00000000; + cpu->isar.id_mmfr0 =3D 0x00101F40; + cpu->isar.id_mmfr1 =3D 0x00000000; + cpu->isar.id_mmfr2 =3D 0x01000000; + cpu->isar.id_mmfr3 =3D 0x00000000; + cpu->isar.id_isar0 =3D 0x01101110; + cpu->isar.id_isar1 =3D 0x02212000; + cpu->isar.id_isar2 =3D 0x20232232; + cpu->isar.id_isar3 =3D 0x01111131; + cpu->isar.id_isar4 =3D 0x01310132; + cpu->isar.id_isar5 =3D 0x00000000; + cpu->isar.id_isar6 =3D 0x00000000; + cpu->clidr =3D 0x00000000; + cpu->ctr =3D 0x8000c000; +} + +static void cortex_m55_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + set_feature(&cpu->env, ARM_FEATURE_V8); + set_feature(&cpu->env, ARM_FEATURE_V8_1M); + set_feature(&cpu->env, ARM_FEATURE_M); + set_feature(&cpu->env, ARM_FEATURE_M_MAIN); + set_feature(&cpu->env, ARM_FEATURE_M_SECURITY); + set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); + cpu->midr =3D 0x410fd221; /* r0p1 */ + cpu->revidr =3D 0; + cpu->pmsav7_dregion =3D 16; + cpu->sau_sregion =3D 8; + /* These are the MVFR* values for the FPU + full MVE configuration */ + cpu->isar.mvfr0 =3D 0x10110221; + cpu->isar.mvfr1 =3D 0x12100211; + cpu->isar.mvfr2 =3D 0x00000040; + cpu->isar.id_pfr0 =3D 0x20000030; + cpu->isar.id_pfr1 =3D 0x00000230; + cpu->isar.id_dfr0 =3D 0x10200000; + cpu->id_afr0 =3D 0x00000000; + cpu->isar.id_mmfr0 =3D 0x00111040; + cpu->isar.id_mmfr1 =3D 0x00000000; + cpu->isar.id_mmfr2 =3D 0x01000000; + cpu->isar.id_mmfr3 =3D 0x00000011; + cpu->isar.id_isar0 =3D 0x01103110; + cpu->isar.id_isar1 =3D 0x02212000; + cpu->isar.id_isar2 =3D 0x20232232; + cpu->isar.id_isar3 =3D 0x01111131; + cpu->isar.id_isar4 =3D 0x01310132; + cpu->isar.id_isar5 =3D 0x00000000; + cpu->isar.id_isar6 =3D 0x00000000; + cpu->clidr =3D 0x00000000; /* caches not implemented */ + cpu->ctr =3D 0x8303c003; +} + +static const TCGCPUOps arm_v7m_tcg_ops =3D { + .initialize =3D arm_translate_init, + .synchronize_from_tb =3D arm_cpu_synchronize_from_tb, + .debug_excp_handler =3D arm_debug_excp_handler, + .restore_state_to_opc =3D arm_restore_state_to_opc, + +#ifdef CONFIG_USER_ONLY + .record_sigsegv =3D arm_cpu_record_sigsegv, + .record_sigbus =3D arm_cpu_record_sigbus, +#else + .tlb_fill =3D arm_cpu_tlb_fill, + .cpu_exec_interrupt =3D arm_v7m_cpu_exec_interrupt, + .do_interrupt =3D arm_v7m_cpu_do_interrupt, + .do_transaction_failed =3D arm_cpu_do_transaction_failed, + .do_unaligned_access =3D arm_cpu_do_unaligned_access, + .adjust_watchpoint_address =3D arm_adjust_watchpoint_address, + .debug_check_watchpoint =3D arm_debug_check_watchpoint, + .debug_check_breakpoint =3D arm_debug_check_breakpoint, +#endif /* !CONFIG_USER_ONLY */ +}; + +static void arm_v7m_class_init(ObjectClass *oc, void *data) +{ + ARMCPUClass *acc =3D ARM_CPU_CLASS(oc); + CPUClass *cc =3D CPU_CLASS(oc); + + acc->info =3D data; + cc->tcg_ops =3D &arm_v7m_tcg_ops; + cc->gdb_core_xml_file =3D "arm-m-profile.xml"; +} + +static const ARMCPUInfo arm_v7m_cpus[] =3D { + { .name =3D "cortex-m0", .initfn =3D cortex_m0_initfn, + .class_init =3D arm_v7m_class_init }, + { .name =3D "cortex-m3", .initfn =3D cortex_m3_initfn, + .class_init =3D arm_v7m_class_init }, + { .name =3D "cortex-m4", .initfn =3D cortex_m4_initfn, + .class_init =3D arm_v7m_class_init }, + { .name =3D "cortex-m7", .initfn =3D cortex_m7_initfn, + .class_init =3D arm_v7m_class_init }, + { .name =3D "cortex-m33", .initfn =3D cortex_m33_initfn, + .class_init =3D arm_v7m_class_init }, + { .name =3D "cortex-m55", .initfn =3D cortex_m55_initfn, + .class_init =3D arm_v7m_class_init }, +}; + +static void arm_v7m_cpu_register_types(void) +{ + size_t i; + + for (i =3D 0; i < ARRAY_SIZE(arm_v7m_cpus); ++i) { + arm_cpu_register(&arm_v7m_cpus[i]); + } +} + +type_init(arm_v7m_cpu_register_types) diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c index 6eb08a41b01..de8f2be9416 100644 --- a/target/arm/tcg/cpu32.c +++ b/target/arm/tcg/cpu32.c @@ -17,9 +17,6 @@ #include "hw/boards.h" #endif #include "cpregs.h" -#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) -#include "hw/intc/armv7m_nvic.h" -#endif =20 =20 /* Share AArch32 -cpu max features with AArch64. */ @@ -98,32 +95,6 @@ void aa32_max_features(ARMCPU *cpu) /* CPU models. These are not needed for the AArch64 linux-user build. */ #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) =20 -#if !defined(CONFIG_USER_ONLY) -static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request) -{ - CPUClass *cc =3D CPU_GET_CLASS(cs); - ARMCPU *cpu =3D ARM_CPU(cs); - CPUARMState *env =3D &cpu->env; - bool ret =3D false; - - /* - * ARMv7-M interrupt masking works differently than -A or -R. - * There is no FIQ/IRQ distinction. Instead of I and F bits - * masking FIQ and IRQ interrupts, an exception is taken only - * if it is higher priority than the current execution priority - * (which depends on state like BASEPRI, FAULTMASK and the - * currently active exception). - */ - if (interrupt_request & CPU_INTERRUPT_HARD - && (armv7m_nvic_can_take_pending_exception(env->nvic))) { - cs->exception_index =3D EXCP_IRQ; - cc->tcg_ops->do_interrupt(cs); - ret =3D true; - } - return ret; -} -#endif /* !CONFIG_USER_ONLY */ - static void arm926_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); @@ -571,195 +542,6 @@ static void cortex_a15_initfn(Object *obj) define_arm_cp_regs(cpu, cortexa15_cp_reginfo); } =20 -static void cortex_m0_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - set_feature(&cpu->env, ARM_FEATURE_V6); - set_feature(&cpu->env, ARM_FEATURE_M); - - cpu->midr =3D 0x410cc200; - - /* - * These ID register values are not guest visible, because - * we do not implement the Main Extension. They must be set - * to values corresponding to the Cortex-M0's implemented - * features, because QEMU generally controls its emulation - * by looking at ID register fields. We use the same values as - * for the M3. - */ - cpu->isar.id_pfr0 =3D 0x00000030; - cpu->isar.id_pfr1 =3D 0x00000200; - cpu->isar.id_dfr0 =3D 0x00100000; - cpu->id_afr0 =3D 0x00000000; - cpu->isar.id_mmfr0 =3D 0x00000030; - cpu->isar.id_mmfr1 =3D 0x00000000; - cpu->isar.id_mmfr2 =3D 0x00000000; - cpu->isar.id_mmfr3 =3D 0x00000000; - cpu->isar.id_isar0 =3D 0x01141110; - cpu->isar.id_isar1 =3D 0x02111000; - cpu->isar.id_isar2 =3D 0x21112231; - cpu->isar.id_isar3 =3D 0x01111110; - cpu->isar.id_isar4 =3D 0x01310102; - cpu->isar.id_isar5 =3D 0x00000000; - cpu->isar.id_isar6 =3D 0x00000000; -} - -static void cortex_m3_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - set_feature(&cpu->env, ARM_FEATURE_V7); - set_feature(&cpu->env, ARM_FEATURE_M); - set_feature(&cpu->env, ARM_FEATURE_M_MAIN); - cpu->midr =3D 0x410fc231; - cpu->pmsav7_dregion =3D 8; - cpu->isar.id_pfr0 =3D 0x00000030; - cpu->isar.id_pfr1 =3D 0x00000200; - cpu->isar.id_dfr0 =3D 0x00100000; - cpu->id_afr0 =3D 0x00000000; - cpu->isar.id_mmfr0 =3D 0x00000030; - cpu->isar.id_mmfr1 =3D 0x00000000; - cpu->isar.id_mmfr2 =3D 0x00000000; - cpu->isar.id_mmfr3 =3D 0x00000000; - cpu->isar.id_isar0 =3D 0x01141110; - cpu->isar.id_isar1 =3D 0x02111000; - cpu->isar.id_isar2 =3D 0x21112231; - cpu->isar.id_isar3 =3D 0x01111110; - cpu->isar.id_isar4 =3D 0x01310102; - cpu->isar.id_isar5 =3D 0x00000000; - cpu->isar.id_isar6 =3D 0x00000000; -} - -static void cortex_m4_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - set_feature(&cpu->env, ARM_FEATURE_V7); - set_feature(&cpu->env, ARM_FEATURE_M); - set_feature(&cpu->env, ARM_FEATURE_M_MAIN); - set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); - cpu->midr =3D 0x410fc240; /* r0p0 */ - cpu->pmsav7_dregion =3D 8; - cpu->isar.mvfr0 =3D 0x10110021; - cpu->isar.mvfr1 =3D 0x11000011; - cpu->isar.mvfr2 =3D 0x00000000; - cpu->isar.id_pfr0 =3D 0x00000030; - cpu->isar.id_pfr1 =3D 0x00000200; - cpu->isar.id_dfr0 =3D 0x00100000; - cpu->id_afr0 =3D 0x00000000; - cpu->isar.id_mmfr0 =3D 0x00000030; - cpu->isar.id_mmfr1 =3D 0x00000000; - cpu->isar.id_mmfr2 =3D 0x00000000; - cpu->isar.id_mmfr3 =3D 0x00000000; - cpu->isar.id_isar0 =3D 0x01141110; - cpu->isar.id_isar1 =3D 0x02111000; - cpu->isar.id_isar2 =3D 0x21112231; - cpu->isar.id_isar3 =3D 0x01111110; - cpu->isar.id_isar4 =3D 0x01310102; - cpu->isar.id_isar5 =3D 0x00000000; - cpu->isar.id_isar6 =3D 0x00000000; -} - -static void cortex_m7_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - set_feature(&cpu->env, ARM_FEATURE_V7); - set_feature(&cpu->env, ARM_FEATURE_M); - set_feature(&cpu->env, ARM_FEATURE_M_MAIN); - set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); - cpu->midr =3D 0x411fc272; /* r1p2 */ - cpu->pmsav7_dregion =3D 8; - cpu->isar.mvfr0 =3D 0x10110221; - cpu->isar.mvfr1 =3D 0x12000011; - cpu->isar.mvfr2 =3D 0x00000040; - cpu->isar.id_pfr0 =3D 0x00000030; - cpu->isar.id_pfr1 =3D 0x00000200; - cpu->isar.id_dfr0 =3D 0x00100000; - cpu->id_afr0 =3D 0x00000000; - cpu->isar.id_mmfr0 =3D 0x00100030; - cpu->isar.id_mmfr1 =3D 0x00000000; - cpu->isar.id_mmfr2 =3D 0x01000000; - cpu->isar.id_mmfr3 =3D 0x00000000; - cpu->isar.id_isar0 =3D 0x01101110; - cpu->isar.id_isar1 =3D 0x02112000; - cpu->isar.id_isar2 =3D 0x20232231; - cpu->isar.id_isar3 =3D 0x01111131; - cpu->isar.id_isar4 =3D 0x01310132; - cpu->isar.id_isar5 =3D 0x00000000; - cpu->isar.id_isar6 =3D 0x00000000; -} - -static void cortex_m33_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - set_feature(&cpu->env, ARM_FEATURE_V8); - set_feature(&cpu->env, ARM_FEATURE_M); - set_feature(&cpu->env, ARM_FEATURE_M_MAIN); - set_feature(&cpu->env, ARM_FEATURE_M_SECURITY); - set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); - cpu->midr =3D 0x410fd213; /* r0p3 */ - cpu->pmsav7_dregion =3D 16; - cpu->sau_sregion =3D 8; - cpu->isar.mvfr0 =3D 0x10110021; - cpu->isar.mvfr1 =3D 0x11000011; - cpu->isar.mvfr2 =3D 0x00000040; - cpu->isar.id_pfr0 =3D 0x00000030; - cpu->isar.id_pfr1 =3D 0x00000210; - cpu->isar.id_dfr0 =3D 0x00200000; - cpu->id_afr0 =3D 0x00000000; - cpu->isar.id_mmfr0 =3D 0x00101F40; - cpu->isar.id_mmfr1 =3D 0x00000000; - cpu->isar.id_mmfr2 =3D 0x01000000; - cpu->isar.id_mmfr3 =3D 0x00000000; - cpu->isar.id_isar0 =3D 0x01101110; - cpu->isar.id_isar1 =3D 0x02212000; - cpu->isar.id_isar2 =3D 0x20232232; - cpu->isar.id_isar3 =3D 0x01111131; - cpu->isar.id_isar4 =3D 0x01310132; - cpu->isar.id_isar5 =3D 0x00000000; - cpu->isar.id_isar6 =3D 0x00000000; - cpu->clidr =3D 0x00000000; - cpu->ctr =3D 0x8000c000; -} - -static void cortex_m55_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - set_feature(&cpu->env, ARM_FEATURE_V8); - set_feature(&cpu->env, ARM_FEATURE_V8_1M); - set_feature(&cpu->env, ARM_FEATURE_M); - set_feature(&cpu->env, ARM_FEATURE_M_MAIN); - set_feature(&cpu->env, ARM_FEATURE_M_SECURITY); - set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); - cpu->midr =3D 0x410fd221; /* r0p1 */ - cpu->revidr =3D 0; - cpu->pmsav7_dregion =3D 16; - cpu->sau_sregion =3D 8; - /* These are the MVFR* values for the FPU + full MVE configuration */ - cpu->isar.mvfr0 =3D 0x10110221; - cpu->isar.mvfr1 =3D 0x12100211; - cpu->isar.mvfr2 =3D 0x00000040; - cpu->isar.id_pfr0 =3D 0x20000030; - cpu->isar.id_pfr1 =3D 0x00000230; - cpu->isar.id_dfr0 =3D 0x10200000; - cpu->id_afr0 =3D 0x00000000; - cpu->isar.id_mmfr0 =3D 0x00111040; - cpu->isar.id_mmfr1 =3D 0x00000000; - cpu->isar.id_mmfr2 =3D 0x01000000; - cpu->isar.id_mmfr3 =3D 0x00000011; - cpu->isar.id_isar0 =3D 0x01103110; - cpu->isar.id_isar1 =3D 0x02212000; - cpu->isar.id_isar2 =3D 0x20232232; - cpu->isar.id_isar3 =3D 0x01111131; - cpu->isar.id_isar4 =3D 0x01310132; - cpu->isar.id_isar5 =3D 0x00000000; - cpu->isar.id_isar6 =3D 0x00000000; - cpu->clidr =3D 0x00000000; /* caches not implemented */ - cpu->ctr =3D 0x8303c003; -} - static const ARMCPRegInfo cortexr5_cp_reginfo[] =3D { /* Dummy the TCM region regs for the moment */ { .name =3D "ATCM", .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 1, .= opc2 =3D 0, @@ -1127,37 +909,6 @@ static void pxa270c5_initfn(Object *obj) cpu->reset_sctlr =3D 0x00000078; } =20 -static const TCGCPUOps arm_v7m_tcg_ops =3D { - .initialize =3D arm_translate_init, - .synchronize_from_tb =3D arm_cpu_synchronize_from_tb, - .debug_excp_handler =3D arm_debug_excp_handler, - .restore_state_to_opc =3D arm_restore_state_to_opc, - -#ifdef CONFIG_USER_ONLY - .record_sigsegv =3D arm_cpu_record_sigsegv, - .record_sigbus =3D arm_cpu_record_sigbus, -#else - .tlb_fill =3D arm_cpu_tlb_fill, - .cpu_exec_interrupt =3D arm_v7m_cpu_exec_interrupt, - .do_interrupt =3D arm_v7m_cpu_do_interrupt, - .do_transaction_failed =3D arm_cpu_do_transaction_failed, - .do_unaligned_access =3D arm_cpu_do_unaligned_access, - .adjust_watchpoint_address =3D arm_adjust_watchpoint_address, - .debug_check_watchpoint =3D arm_debug_check_watchpoint, - .debug_check_breakpoint =3D arm_debug_check_breakpoint, -#endif /* !CONFIG_USER_ONLY */ -}; - -static void arm_v7m_class_init(ObjectClass *oc, void *data) -{ - ARMCPUClass *acc =3D ARM_CPU_CLASS(oc); - CPUClass *cc =3D CPU_CLASS(oc); - - acc->info =3D data; - cc->tcg_ops =3D &arm_v7m_tcg_ops; - cc->gdb_core_xml_file =3D "arm-m-profile.xml"; -} - #ifndef TARGET_AARCH64 /* * -cpu max: a CPU with as many features enabled as our emulation supports. @@ -1240,18 +991,6 @@ static const ARMCPUInfo arm_tcg_cpus[] =3D { { .name =3D "cortex-a8", .initfn =3D cortex_a8_initfn }, { .name =3D "cortex-a9", .initfn =3D cortex_a9_initfn }, { .name =3D "cortex-a15", .initfn =3D cortex_a15_initfn }, - { .name =3D "cortex-m0", .initfn =3D cortex_m0_initfn, - .class_init =3D arm_v7m_class_init }, - { .name =3D "cortex-m3", .initfn =3D cortex_m3_initfn, - .class_init =3D arm_v7m_class_init }, - { .name =3D "cortex-m4", .initfn =3D cortex_m4_initfn, - .class_init =3D arm_v7m_class_init }, - { .name =3D "cortex-m7", .initfn =3D cortex_m7_initfn, - .class_init =3D arm_v7m_class_init }, - { .name =3D "cortex-m33", .initfn =3D cortex_m33_initfn, - .class_init =3D arm_v7m_class_init }, - { .name =3D "cortex-m55", .initfn =3D cortex_m55_initfn, - .class_init =3D arm_v7m_class_init }, { .name =3D "cortex-r5", .initfn =3D cortex_r5_initfn }, { .name =3D "cortex-r5f", .initfn =3D cortex_r5f_initfn }, { .name =3D "cortex-r52", .initfn =3D cortex_r52_initfn }, diff --git a/target/arm/meson.build b/target/arm/meson.build index 46b5a21eb31..2e10464dbb6 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -26,6 +26,8 @@ arm_system_ss.add(files( 'ptw.c', )) =20 +arm_user_ss =3D ss.source_set() + subdir('hvf') =20 if 'CONFIG_TCG' in config_all_accel @@ -36,3 +38,4 @@ endif =20 target_arch +=3D {'arm': arm_ss} target_system_arch +=3D {'arm': arm_system_ss} +target_user_arch +=3D {'arm': arm_user_ss} diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build index 6fca38f2ccb..3b1a9f0fc5e 100644 --- a/target/arm/tcg/meson.build +++ b/target/arm/tcg/meson.build @@ -55,3 +55,6 @@ arm_ss.add(when: 'TARGET_AARCH64', if_true: files( arm_system_ss.add(files( 'psci.c', )) + +arm_system_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('cpu-v7m.c')) +arm_user_ss.add(when: 'TARGET_AARCH64', if_false: files('cpu-v7m.c')) --=20 2.34.1