From nobody Sun Feb 8 21:28:49 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1709833483; cv=none; d=zohomail.com; s=zohoarc; b=Tg4jB+8cXaeBtgxghN/WzixOyvY6caIG/vhkrtE9QN2caqVz66EDXwq28QbJePLo+RnNkZ24/nYfr6alYPjNLMZsD8GoTZFGwWVCYirLTUWwSmPAWJ3KQhvR+TjDiIDlK1rKLkSRp8GOWbS6HnDxd3e44uGmvqxgD03gRfCPhJk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1709833483; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=SPmJU6DLj8tZZCP7Akw3R7cWOpL9VFTanRI+1Y8sK/w=; b=Lg64g8ps9FOyhctKMWA41HORh2NVKOO0vEvT+LgjwWCkuCiZ2o9O1RKAYZV0Asdsg19Gitup9JTZtULE/LvJDXuTsUu1C96d1veWyDEv9wpVox5wzfey9Fyk7Yq2QWajmeXmLBooHcT5pyJUOD6cChup1w/3LGnrUnzxYvX0cvU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1709833483866182.23080546264578; Thu, 7 Mar 2024 09:44:43 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1riHmt-0000tJ-19; Thu, 07 Mar 2024 12:44:11 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1riHmU-0000fW-1q for qemu-devel@nongnu.org; Thu, 07 Mar 2024 12:43:46 -0500 Received: from us-smtp-delivery-124.mimecast.com ([170.10.129.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1riHmS-00041C-2t for qemu-devel@nongnu.org; Thu, 07 Mar 2024 12:43:45 -0500 Received: from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-663-TCip_INrPeOj-ivF9PiuIQ-1; Thu, 07 Mar 2024 12:43:41 -0500 Received: from smtp.corp.redhat.com (int-mx10.intmail.prod.int.rdu2.redhat.com [10.11.54.10]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 041C48F8F64; Thu, 7 Mar 2024 17:43:41 +0000 (UTC) Received: from thuth-p1g4.redhat.com (unknown [10.39.192.76]) by smtp.corp.redhat.com (Postfix) with ESMTP id 487F4492BDC; Thu, 7 Mar 2024 17:43:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1709833423; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=SPmJU6DLj8tZZCP7Akw3R7cWOpL9VFTanRI+1Y8sK/w=; b=GpUdsAMBJjYlWv4Zv17dJZ0X9iwpX1vFVepW3XuKkGGcriXBO49mwrXsRqbILVAWec9C8p 6chDBMahxfALUldl3jR5EUvLfLxaIcouLMG0OQaZumjOdZN41DMhLLWQPx9H7K/5C4uURo xYdqdbA6cKel3HESjZLW3SN5WCCtrEQ= X-MC-Unique: TCip_INrPeOj-ivF9PiuIQ-1 From: Thomas Huth To: qemu-devel@nongnu.org, Artyom Tarasenko , Mark Cave-Ayland Cc: Eduardo Habkost , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , Paolo Bonzini Subject: [PATCH 2/5] target/sparc/cpu: Avoid spaces by default in the CPU names Date: Thu, 7 Mar 2024 18:43:31 +0100 Message-ID: <20240307174334.130407-3-thuth@redhat.com> In-Reply-To: <20240307174334.130407-1-thuth@redhat.com> References: <20240307174334.130407-1-thuth@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.11.54.10 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=thuth@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.583, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1709833485826100009 Content-Type: text/plain; charset="utf-8" The output of "-cpu help" is currently rather confusing to the users: It is not clear which part of the output defines the CPU names since the CPU names contain white spaces (which we later have to convert into dashes internally) For example: Sparc TI UltraSparc II IU 0017001120000000 FPU 00000000 MMU 00000000 NWINS 8 At a first glance, should the name for -cpu be "Sparc TI Ultrasparc II" or "TI UltraSparc II IU" here? Both would be wrong, the right guess is "TI UltraSparc II" only. Let's start cleaning up this mess by using dashes instead of white spaces for the CPU names, like we're doing it internally later (and like we're doing it in most other targets of QEMU). Note that it is still possible to pass the CPU names with spaces to the "-cpu" option, since sparc_cpu_type_name() still translates those to "-". Buglink: https://gitlab.com/qemu-project/qemu/-/issues/2141 Signed-off-by: Thomas Huth Reviewed-by: Mark Cave-Ayland Reviewed-by: Richard Henderson --- target/sparc/cpu.c | 56 +++++++++++++++++++++++----------------------- 1 file changed, 28 insertions(+), 28 deletions(-) diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 651e49bfeb..ae30cded22 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -208,7 +208,7 @@ void cpu_sparc_set_id(CPUSPARCState *env, unsigned int = cpu) static const sparc_def_t sparc_defs[] =3D { #ifdef TARGET_SPARC64 { - .name =3D "Fujitsu Sparc64", + .name =3D "Fujitsu-Sparc64", .iu_version =3D ((0x04ULL << 48) | (0x02ULL << 32) | (0ULL << 24)), .fpu_version =3D 0x00000000, .mmu_version =3D mmu_us_12, @@ -217,7 +217,7 @@ static const sparc_def_t sparc_defs[] =3D { .features =3D CPU_DEFAULT_FEATURES, }, { - .name =3D "Fujitsu Sparc64 III", + .name =3D "Fujitsu-Sparc64-III", .iu_version =3D ((0x04ULL << 48) | (0x03ULL << 32) | (0ULL << 24)), .fpu_version =3D 0x00000000, .mmu_version =3D mmu_us_12, @@ -226,7 +226,7 @@ static const sparc_def_t sparc_defs[] =3D { .features =3D CPU_DEFAULT_FEATURES, }, { - .name =3D "Fujitsu Sparc64 IV", + .name =3D "Fujitsu-Sparc64-IV", .iu_version =3D ((0x04ULL << 48) | (0x04ULL << 32) | (0ULL << 24)), .fpu_version =3D 0x00000000, .mmu_version =3D mmu_us_12, @@ -235,7 +235,7 @@ static const sparc_def_t sparc_defs[] =3D { .features =3D CPU_DEFAULT_FEATURES, }, { - .name =3D "Fujitsu Sparc64 V", + .name =3D "Fujitsu-Sparc64-V", .iu_version =3D ((0x04ULL << 48) | (0x05ULL << 32) | (0x51ULL << 2= 4)), .fpu_version =3D 0x00000000, .mmu_version =3D mmu_us_12, @@ -244,7 +244,7 @@ static const sparc_def_t sparc_defs[] =3D { .features =3D CPU_DEFAULT_FEATURES, }, { - .name =3D "TI UltraSparc I", + .name =3D "TI-UltraSparc-I", .iu_version =3D ((0x17ULL << 48) | (0x10ULL << 32) | (0x40ULL << 2= 4)), .fpu_version =3D 0x00000000, .mmu_version =3D mmu_us_12, @@ -253,7 +253,7 @@ static const sparc_def_t sparc_defs[] =3D { .features =3D CPU_DEFAULT_FEATURES, }, { - .name =3D "TI UltraSparc II", + .name =3D "TI-UltraSparc-II", .iu_version =3D ((0x17ULL << 48) | (0x11ULL << 32) | (0x20ULL << 2= 4)), .fpu_version =3D 0x00000000, .mmu_version =3D mmu_us_12, @@ -262,7 +262,7 @@ static const sparc_def_t sparc_defs[] =3D { .features =3D CPU_DEFAULT_FEATURES, }, { - .name =3D "TI UltraSparc IIi", + .name =3D "TI-UltraSparc-IIi", .iu_version =3D ((0x17ULL << 48) | (0x12ULL << 32) | (0x91ULL << 2= 4)), .fpu_version =3D 0x00000000, .mmu_version =3D mmu_us_12, @@ -271,7 +271,7 @@ static const sparc_def_t sparc_defs[] =3D { .features =3D CPU_DEFAULT_FEATURES, }, { - .name =3D "TI UltraSparc IIe", + .name =3D "TI-UltraSparc-IIe", .iu_version =3D ((0x17ULL << 48) | (0x13ULL << 32) | (0x14ULL << 2= 4)), .fpu_version =3D 0x00000000, .mmu_version =3D mmu_us_12, @@ -280,7 +280,7 @@ static const sparc_def_t sparc_defs[] =3D { .features =3D CPU_DEFAULT_FEATURES, }, { - .name =3D "Sun UltraSparc III", + .name =3D "Sun-UltraSparc-III", .iu_version =3D ((0x3eULL << 48) | (0x14ULL << 32) | (0x34ULL << 2= 4)), .fpu_version =3D 0x00000000, .mmu_version =3D mmu_us_12, @@ -289,7 +289,7 @@ static const sparc_def_t sparc_defs[] =3D { .features =3D CPU_DEFAULT_FEATURES, }, { - .name =3D "Sun UltraSparc III Cu", + .name =3D "Sun-UltraSparc-III-Cu", .iu_version =3D ((0x3eULL << 48) | (0x15ULL << 32) | (0x41ULL << 2= 4)), .fpu_version =3D 0x00000000, .mmu_version =3D mmu_us_3, @@ -298,7 +298,7 @@ static const sparc_def_t sparc_defs[] =3D { .features =3D CPU_DEFAULT_FEATURES, }, { - .name =3D "Sun UltraSparc IIIi", + .name =3D "Sun-UltraSparc-IIIi", .iu_version =3D ((0x3eULL << 48) | (0x16ULL << 32) | (0x34ULL << 2= 4)), .fpu_version =3D 0x00000000, .mmu_version =3D mmu_us_12, @@ -307,7 +307,7 @@ static const sparc_def_t sparc_defs[] =3D { .features =3D CPU_DEFAULT_FEATURES, }, { - .name =3D "Sun UltraSparc IV", + .name =3D "Sun-UltraSparc-IV", .iu_version =3D ((0x3eULL << 48) | (0x18ULL << 32) | (0x31ULL << 2= 4)), .fpu_version =3D 0x00000000, .mmu_version =3D mmu_us_4, @@ -316,7 +316,7 @@ static const sparc_def_t sparc_defs[] =3D { .features =3D CPU_DEFAULT_FEATURES, }, { - .name =3D "Sun UltraSparc IVp", + .name =3D "Sun-UltraSparc-IVp", .iu_version =3D ((0x3eULL << 48) | (0x19ULL << 32) | (0x22ULL << 2= 4)), .fpu_version =3D 0x00000000, .mmu_version =3D mmu_us_12, @@ -325,7 +325,7 @@ static const sparc_def_t sparc_defs[] =3D { .features =3D CPU_DEFAULT_FEATURES | CPU_FEATURE_CMT, }, { - .name =3D "Sun UltraSparc IIIip", + .name =3D "Sun-UltraSparc-IIIip", .iu_version =3D ((0x3eULL << 48) | (0x22ULL << 32) | (0ULL << 24)), .fpu_version =3D 0x00000000, .mmu_version =3D mmu_us_3, @@ -334,7 +334,7 @@ static const sparc_def_t sparc_defs[] =3D { .features =3D CPU_DEFAULT_FEATURES, }, { - .name =3D "Sun UltraSparc T1", + .name =3D "Sun-UltraSparc-T1", /* defined in sparc_ifu_fdp.v and ctu.h */ .iu_version =3D ((0x3eULL << 48) | (0x23ULL << 32) | (0x02ULL << 2= 4)), .fpu_version =3D 0x00000000, @@ -345,7 +345,7 @@ static const sparc_def_t sparc_defs[] =3D { | CPU_FEATURE_GL, }, { - .name =3D "Sun UltraSparc T2", + .name =3D "Sun-UltraSparc-T2", /* defined in tlu_asi_ctl.v and n2_revid_cust.v */ .iu_version =3D ((0x3eULL << 48) | (0x24ULL << 32) | (0x02ULL << 2= 4)), .fpu_version =3D 0x00000000, @@ -356,7 +356,7 @@ static const sparc_def_t sparc_defs[] =3D { | CPU_FEATURE_GL, }, { - .name =3D "NEC UltraSparc I", + .name =3D "NEC-UltraSparc-I", .iu_version =3D ((0x22ULL << 48) | (0x10ULL << 32) | (0x40ULL << 2= 4)), .fpu_version =3D 0x00000000, .mmu_version =3D mmu_us_12, @@ -366,7 +366,7 @@ static const sparc_def_t sparc_defs[] =3D { }, #else { - .name =3D "Fujitsu MB86904", + .name =3D "Fujitsu-MB86904", .iu_version =3D 0x04 << 24, /* Impl 0, ver 4 */ .fpu_version =3D 4 << FSR_VER_SHIFT, /* FPU version 4 (Meiko) */ .mmu_version =3D 0x04 << 24, /* Impl 0, ver 4 */ @@ -379,7 +379,7 @@ static const sparc_def_t sparc_defs[] =3D { .features =3D CPU_DEFAULT_FEATURES, }, { - .name =3D "Fujitsu MB86907", + .name =3D "Fujitsu-MB86907", .iu_version =3D 0x05 << 24, /* Impl 0, ver 5 */ .fpu_version =3D 4 << FSR_VER_SHIFT, /* FPU version 4 (Meiko) */ .mmu_version =3D 0x05 << 24, /* Impl 0, ver 5 */ @@ -392,7 +392,7 @@ static const sparc_def_t sparc_defs[] =3D { .features =3D CPU_DEFAULT_FEATURES, }, { - .name =3D "TI MicroSparc I", + .name =3D "TI-MicroSparc-I", .iu_version =3D 0x41000000, .fpu_version =3D 4 << FSR_VER_SHIFT, .mmu_version =3D 0x41000000, @@ -405,7 +405,7 @@ static const sparc_def_t sparc_defs[] =3D { .features =3D CPU_FEATURE_MUL | CPU_FEATURE_DIV, }, { - .name =3D "TI MicroSparc II", + .name =3D "TI-MicroSparc-II", .iu_version =3D 0x42000000, .fpu_version =3D 4 << FSR_VER_SHIFT, .mmu_version =3D 0x02000000, @@ -418,7 +418,7 @@ static const sparc_def_t sparc_defs[] =3D { .features =3D CPU_DEFAULT_FEATURES, }, { - .name =3D "TI MicroSparc IIep", + .name =3D "TI-MicroSparc-IIep", .iu_version =3D 0x42000000, .fpu_version =3D 4 << FSR_VER_SHIFT, .mmu_version =3D 0x04000000, @@ -431,7 +431,7 @@ static const sparc_def_t sparc_defs[] =3D { .features =3D CPU_DEFAULT_FEATURES, }, { - .name =3D "TI SuperSparc 40", /* STP1020NPGA */ + .name =3D "TI-SuperSparc-40", /* STP1020NPGA */ .iu_version =3D 0x41000000, /* SuperSPARC 2.x */ .fpu_version =3D 0 << FSR_VER_SHIFT, .mmu_version =3D 0x00000800, /* SuperSPARC 2.x, no MXCC */ @@ -444,7 +444,7 @@ static const sparc_def_t sparc_defs[] =3D { .features =3D CPU_DEFAULT_FEATURES, }, { - .name =3D "TI SuperSparc 50", /* STP1020PGA */ + .name =3D "TI-SuperSparc-50", /* STP1020PGA */ .iu_version =3D 0x40000000, /* SuperSPARC 3.x */ .fpu_version =3D 0 << FSR_VER_SHIFT, .mmu_version =3D 0x01000800, /* SuperSPARC 3.x, no MXCC */ @@ -457,7 +457,7 @@ static const sparc_def_t sparc_defs[] =3D { .features =3D CPU_DEFAULT_FEATURES, }, { - .name =3D "TI SuperSparc 51", + .name =3D "TI-SuperSparc-51", .iu_version =3D 0x40000000, /* SuperSPARC 3.x */ .fpu_version =3D 0 << FSR_VER_SHIFT, .mmu_version =3D 0x01000000, /* SuperSPARC 3.x, MXCC */ @@ -471,7 +471,7 @@ static const sparc_def_t sparc_defs[] =3D { .features =3D CPU_DEFAULT_FEATURES, }, { - .name =3D "TI SuperSparc 60", /* STP1020APGA */ + .name =3D "TI-SuperSparc-60", /* STP1020APGA */ .iu_version =3D 0x40000000, /* SuperSPARC 3.x */ .fpu_version =3D 0 << FSR_VER_SHIFT, .mmu_version =3D 0x01000800, /* SuperSPARC 3.x, no MXCC */ @@ -484,7 +484,7 @@ static const sparc_def_t sparc_defs[] =3D { .features =3D CPU_DEFAULT_FEATURES, }, { - .name =3D "TI SuperSparc 61", + .name =3D "TI-SuperSparc-61", .iu_version =3D 0x44000000, /* SuperSPARC 3.x */ .fpu_version =3D 0 << FSR_VER_SHIFT, .mmu_version =3D 0x01000000, /* SuperSPARC 3.x, MXCC */ @@ -498,7 +498,7 @@ static const sparc_def_t sparc_defs[] =3D { .features =3D CPU_DEFAULT_FEATURES, }, { - .name =3D "TI SuperSparc II", + .name =3D "TI-SuperSparc-II", .iu_version =3D 0x40000000, /* SuperSPARC II 1.x */ .fpu_version =3D 0 << FSR_VER_SHIFT, .mmu_version =3D 0x08000000, /* SuperSPARC II 1.x, MXCC */ --=20 2.44.0