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[114.35.142.126]) by smtp.gmail.com with ESMTPSA id h21-20020a17090a9c1500b0029b73f2a0besm1605497pjp.45.2024.03.06.08.10.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Mar 2024 08:10:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1709741445; x=1710346245; darn=nongnu.org; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=npEeaAAo3oCK9gf/6CQOc1KZa2+QOGbXENzn0EtNKw4=; b=NMNx874c9bSrUioPP9qsGvbQa2Cez6XKaKGewrq2nj9CS0jPSL56WmOnv5CkQ0ZIVE XP1ggEs6ycFgnLnHMd7YB1WU6FDh7EGo1RpyGa/gl4iAUDZiugtIzQZNtEr+Z+oKSfXh 9h5EIQEL4mUG4ZS9KtG0qVVbf75Wzk6l0sOxTkL6CzmL9gSDXoUZygZNeHEnrgY51itf psp674360hjW0quN8ImHjW9hK/FTZbY1rBJFcPHkVKBDNsLwJ1vpfVTPNUTegx/Yh+XY +mCovhrEypcljPCbkClVtbtdkKUV7BAFbiGF5zIFBxUZL1YZeHGTbmSFv4AKkTVzDRQl +0HQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1709741445; x=1710346245; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=npEeaAAo3oCK9gf/6CQOc1KZa2+QOGbXENzn0EtNKw4=; b=vDn+HBTrCf5zVG5eundT8wYlqRR8hP8CLAj4KWxwq2PuLpqxJjNjr4s21EJNVr2Q66 0njIhU9mbLpibaI8oTdqhYATSduwhvQAyxnsot8VZcvWSk4dZdPkTkYUiau9iu/Pw1lU gwykDvk0ADobG2ztifqo7TurOyGezxUSRlI8Mu8aDWZnznygOrTSyPMECz4ITOc//Stu BWbrELkH8sxB9l8aeh9PJW/ukQkmHW5J+CDYryyGlvKJ19WdUcRsAi4Co91uLTsfNVGh z2D7ESNHvvEO+3XmBO4qWJjjcyPbYOrWvKCRvXDce6uYOqhmvo5yjdrLyV5fHZIHg1U5 Wgpw== X-Gm-Message-State: AOJu0Yx801L6yjnFeUMdJ3HNvstCc776VSgOM4gjVz9Q9wIYh/b2YLuI k0Jv1SlkED8ZujtlCkcRHpL58wEZQ5fRV5T2kTiLOpkt7Cr5og8y5O65IdQDoI76AkBFrxqWKyS 905RelFCwAI0CZTaQibPeiaYc2LeFb+i2X1uCrVTUi76S0QWTY3HrICX+99udZyaZNNHcJSQr6B RfjbqGN5+mn4vXNLEj8buCTAvGySDBtlYG7PB4ywx/ X-Google-Smtp-Source: AGHT+IEqPnPG+bO4zBfFIKPhmTsTQGzMMvlcZQSKfqvxg3I/yda0WfXw+k5CReCmZc/fi1z/YZf+1w== X-Received: by 2002:a17:90b:711:b0:29a:9952:67b7 with SMTP id s17-20020a17090b071100b0029a995267b7mr12392900pjz.48.1709741445298; Wed, 06 Mar 2024 08:10:45 -0800 (PST) From: Max Chou To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Max Chou , Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei Subject: [PATCH] target/riscv/vector_helper.c: Avoid shifting negative in fractional LMUL checking Date: Thu, 7 Mar 2024 00:10:22 +0800 Message-Id: <20240306161036.938931-1-max.chou@sifive.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=max.chou@sifive.com; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1709741484311100001 Content-Type: text/plain; charset="utf-8" When vlmul is larger than 5, the original fractional LMUL checking may gets unexpected result. Signed-off-by: Max Chou --- target/riscv/vector_helper.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 84cec73eb20..adceec378fd 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -53,10 +53,9 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_u= long s1, * VLEN * LMUL >=3D SEW * VLEN >> (8 - lmul) >=3D sew * (vlenb << 3) >> (8 - lmul) >=3D sew - * vlenb >> (8 - 3 - lmul) >=3D sew */ if (vlmul =3D=3D 4 || - cpu->cfg.vlenb >> (8 - 3 - vlmul) < sew) { + ((cpu->cfg.vlenb << 3) >> (8 - vlmul)) < sew) { vill =3D true; } } --=20 2.34.1