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Wed, 06 Mar 2024 01:57:39 -0800 (PST) From: Anup Patel To: Peter Maydell , Palmer Dabbelt , Alistair Francis , Sagar Karandikar Cc: Richard Henderson , Daniel Henrique Barboza , Atish Patra , Anup Patel , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Anup Patel Subject: [PATCH 2/2] hw/intc/riscv_aplic: Fix in_clrip[x] read emulation Date: Wed, 6 Mar 2024 15:27:22 +0530 Message-Id: <20240306095722.463296-3-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240306095722.463296-1-apatel@ventanamicro.com> References: <20240306095722.463296-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=apatel@ventanamicro.com; helo=mail-pl1-x634.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1709719098313100001 The reads to in_clrip[x] registers return rectified input values of the interrupt sources. A rectified input value of an interrupt source is defined by the section "4.5.2 Source configurations (sourcecfg[1]=E2=80=93sourcecfg[1023])" of the= RISC-V AIA specification as: "rectified input value =3D (incoming wire value) XOR (source is inverted)" Update the riscv_aplic_read_input_word() implementation to match the above. Fixes: e8f79343cfc8 ("hw/intc: Add RISC-V AIA APLIC device emulation") Signed-off-by: Anup Patel Reviewed-by: Daniel Henrique Barboza --- hw/intc/riscv_aplic.c | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c index 775bb96164..6a7fbfa861 100644 --- a/hw/intc/riscv_aplic.c +++ b/hw/intc/riscv_aplic.c @@ -162,7 +162,7 @@ static bool is_kvm_aia(bool msimode) static uint32_t riscv_aplic_read_input_word(RISCVAPLICState *aplic, uint32_t word) { - uint32_t i, irq, ret =3D 0; + uint32_t i, irq, sourcecfg, sm, raw_input, irq_inverted, ret =3D 0; =20 for (i =3D 0; i < 32; i++) { irq =3D word * 32 + i; @@ -170,7 +170,20 @@ static uint32_t riscv_aplic_read_input_word(RISCVAPLIC= State *aplic, continue; } =20 - ret |=3D ((aplic->state[irq] & APLIC_ISTATE_INPUT) ? 1 : 0) << i; + sourcecfg =3D aplic->sourcecfg[irq]; + if (sourcecfg & APLIC_SOURCECFG_D) { + continue; + } + + sm =3D sourcecfg & APLIC_SOURCECFG_SM_MASK; + if (sm =3D=3D APLIC_SOURCECFG_SM_INACTIVE) { + continue; + } + + raw_input =3D (aplic->state[irq] & APLIC_ISTATE_INPUT) ? 1 : 0; + irq_inverted =3D (sm =3D=3D APLIC_SOURCECFG_SM_LEVEL_LOW || + sm =3D=3D APLIC_SOURCECFG_SM_EDGE_FALL) ? 1 : 0; + ret |=3D (raw_input ^ irq_inverted) << i; } =20 return ret; --=20 2.34.1