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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.15; envelope-from=fei2.wu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.589, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1709548099165100003 Content-Type: text/plain; charset="utf-8" The harts requirements of RISC-V server platform [1] require RVA23 ISA profile support, plus Sv48, Svadu, H, Sscofmpf etc. This patch provides a virt CPU type (rvsp-ref) as compliant as possible. [1] https://github.com/riscv-non-isa/riscv-server-platform/blob/main/server= _platform_requirements.adoc Signed-off-by: Fei Wu --- hw/riscv/server_platform_ref.c | 6 +++- target/riscv/cpu-qom.h | 1 + target/riscv/cpu.c | 62 ++++++++++++++++++++++++++++++++++ 3 files changed, 68 insertions(+), 1 deletion(-) diff --git a/hw/riscv/server_platform_ref.c b/hw/riscv/server_platform_ref.c index ae90c4b27a..52ec607cee 100644 --- a/hw/riscv/server_platform_ref.c +++ b/hw/riscv/server_platform_ref.c @@ -1205,11 +1205,15 @@ static void rvsp_ref_machine_class_init(ObjectClass= *oc, void *data) { char str[128]; MachineClass *mc =3D MACHINE_CLASS(oc); + static const char * const valid_cpu_types[] =3D { + TYPE_RISCV_CPU_RVSP_REF, + }; =20 mc->desc =3D "RISC-V Server SoC Reference board"; mc->init =3D rvsp_ref_machine_init; mc->max_cpus =3D RVSP_CPUS_MAX; - mc->default_cpu_type =3D TYPE_RISCV_CPU_BASE; + mc->default_cpu_type =3D TYPE_RISCV_CPU_RVSP_REF; + mc->valid_cpu_types =3D valid_cpu_types; mc->pci_allow_0_address =3D true; mc->default_nic =3D "e1000e"; mc->possible_cpu_arch_ids =3D riscv_numa_possible_cpu_arch_ids; diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h index 3670cfe6d9..adb934d19e 100644 --- a/target/riscv/cpu-qom.h +++ b/target/riscv/cpu-qom.h @@ -49,6 +49,7 @@ #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") #define TYPE_RISCV_CPU_THEAD_C906 RISCV_CPU_TYPE_NAME("thead-c906") #define TYPE_RISCV_CPU_VEYRON_V1 RISCV_CPU_TYPE_NAME("veyron-v1") +#define TYPE_RISCV_CPU_RVSP_REF RISCV_CPU_TYPE_NAME("rvsp-ref") #define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host") =20 OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 5ff0192c52..bc91be702b 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -2282,6 +2282,67 @@ static void rva22s64_profile_cpu_init(Object *obj) =20 RVA22S64.enabled =3D true; } + +static void rv64_rvsp_ref_cpu_init(Object *obj) +{ + CPURISCVState *env =3D &RISCV_CPU(obj)->env; + RISCVCPU *cpu =3D RISCV_CPU(obj); + + riscv_cpu_set_misa_ext(env, RVG | RVC | RVS | RVU | RVH | RVV); + + /* FIXME: change to 1.13 */ + env->priv_ver =3D PRIV_VERSION_1_12_0; + + /* RVA22U64 */ + cpu->cfg.mmu =3D true; + cpu->cfg.ext_zifencei =3D true; + cpu->cfg.ext_zicsr =3D true; + cpu->cfg.ext_zicntr =3D true; + cpu->cfg.ext_zihpm =3D true; + cpu->cfg.ext_zihintpause =3D true; + cpu->cfg.ext_zba =3D true; + cpu->cfg.ext_zbb =3D true; + cpu->cfg.ext_zbs =3D true; + cpu->cfg.zic64b =3D true; + cpu->cfg.ext_zicbom =3D true; + cpu->cfg.ext_zicbop =3D true; + cpu->cfg.ext_zicboz =3D true; + cpu->cfg.cbom_blocksize =3D 64; + cpu->cfg.cbop_blocksize =3D 64; + cpu->cfg.cboz_blocksize =3D 64; + cpu->cfg.ext_zfhmin =3D true; + cpu->cfg.ext_zkt =3D true; + + /* RVA23U64 */ + cpu->cfg.ext_zvfhmin =3D true; + cpu->cfg.ext_zvbb =3D true; + cpu->cfg.ext_zvkt =3D true; + cpu->cfg.ext_zihintntl =3D true; + cpu->cfg.ext_zicond =3D true; + cpu->cfg.ext_zcb =3D true; + cpu->cfg.ext_zfa =3D true; + cpu->cfg.ext_zawrs =3D true; + + /* RVA23S64 */ + cpu->cfg.ext_zifencei =3D true; + cpu->cfg.svade =3D true; + cpu->cfg.ext_svpbmt =3D true; + cpu->cfg.ext_svinval =3D true; + cpu->cfg.ext_svnapot =3D true; + cpu->cfg.ext_sstc =3D true; + cpu->cfg.ext_sscofpmf =3D true; + cpu->cfg.ext_smstateen =3D true; + + cpu->cfg.ext_smaia =3D true; + cpu->cfg.ext_ssaia =3D true; + + /* Server Platform */ +#ifndef CONFIG_USER_ONLY + set_satp_mode_max_supported(cpu, VM_1_10_SV48); +#endif + cpu->cfg.ext_svadu =3D true; + cpu->cfg.ext_zkr =3D true; +} #endif =20 static const gchar *riscv_gdb_arch_name(CPUState *cs) @@ -2547,6 +2608,7 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV64E, MXL_RV64, rv64e_bare_cpu= _init), DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22U64, MXL_RV64, rva22u64_profi= le_cpu_init), DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22S64, MXL_RV64, rva22s64_profi= le_cpu_init), + DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_RVSP_REF, MXL_RV64, rv64_rvsp_ref_= cpu_init), #endif }; =20 --=20 2.34.1