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Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help: List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=zRpUS3NzcFDLz/P2IvCqiWZMmhZ7r0QriGkPN0Sh05M=; b=eCXXMZXHvEBpCwIbf7TSa4Z5JJ ULPd9S0NhneFFrFjlQPEKJ7hKG+lOHeA5oSSlIvtEcuirBuvew4bXuPsC1ux24KgVfXA+d5o1+Nrq lgr3dMzqqOwoT3QaUSgNg0wXwLEB1iDjKoQobL0pVk+qReCnX6Di0bihOOBEef3R6goLelJcsdm3Q C3Er5UhzeIaUuzieO4FGAwWLUwJUDaML2JAxzhBR6bp8iY6Y9R2HtJCVXPu9gYUcpV0dqNVubEMEl SL0ZHizfSSABDicNfg9GnwZzUYIVRXVfV69BLs0xNJ0yMhKVSzAOPlcvoYb99JAICpYpwVVvDapAg YgcTUqEQ==; From: Sven Schnelle To: Richard Henderson Cc: deller@gmx.de, qemu-devel@nongnu.org, Sven Schnelle Subject: [PATCH] target/hppa: add assemble_16() Date: Sat, 2 Mar 2024 18:21:55 +0100 Message-ID: <20240302172727.2035011-2-svens@stackframe.org> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240302172727.2035011-1-svens@stackframe.org> References: <20240302172727.2035011-1-svens@stackframe.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=23.83.209.21; envelope-from=svens@stackframe.org; helo=bongo.birch.relay.mailchannels.net X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @stackframe.org) X-ZM-MESSAGEID: 1709400576364100006 Content-Type: text/plain; charset="utf-8" Signed-off-by: Sven Schnelle --- target/hppa/insns.decode | 99 ++++++++++++++++++++-------------------- target/hppa/translate.c | 22 +++++++++ 2 files changed, 72 insertions(+), 49 deletions(-) diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode index f5a3f02fd1..8f17e18cd0 100644 --- a/target/hppa/insns.decode +++ b/target/hppa/insns.decode @@ -62,7 +62,7 @@ #### =20 # All insns that need to form a virtual address should use this set. -&ldst t b x disp sp m scale size +&ldst t b x disp sp m scale size w16 =20 &rr_cf_d t r cf d &rrr t r1 r2 @@ -138,7 +138,7 @@ getshadowregs 1111 1111 1111 1101 1110 1010 1101 0010 #### =20 @addrx ...... b:5 x:5 .. ........ m:1 ..... \ - &ldst disp=3D0 scale=3D0 t=3D0 sp=3D0 size=3D0 + &ldst disp=3D0 scale=3D0 t=3D0 sp=3D0 size=3D0 w16=3D0 =20 nop 000001 ----- ----- -- 11001010 0 ----- # fdc, disp nop_addrx 000001 ..... ..... -- 01001010 . ----- @addrx # fdc, index @@ -163,24 +163,24 @@ ixtlbt 000001 r2:5 r1:5 000 data:1 100000 0 = 00000 # idtlbt =20 # pdtlb, pitlb pxtlb 000001 b:5 x:5 sp:2 01001000 m:1 ----- \ - &ldst disp=3D0 scale=3D0 size=3D0 t=3D0 + &ldst disp=3D0 scale=3D0 size=3D0 t=3D0 w16=3D0 pxtlb 000001 b:5 x:5 ... 0001000 m:1 ----- \ - &ldst disp=3D0 scale=3D0 size=3D0 t=3D0 sp=3D%assemble_sr3x + &ldst disp=3D0 scale=3D0 size=3D0 t=3D0 sp=3D%assemble_sr3= x w16=3D0 =20 # ... pa20 local pxtlb_l 000001 b:5 x:5 sp:2 01011000 m:1 ----- \ - &ldst disp=3D0 scale=3D0 size=3D0 t=3D0 + &ldst disp=3D0 scale=3D0 size=3D0 t=3D0 w16=3D0 pxtlb_l 000001 b:5 x:5 ... 0011000 m:1 ----- \ - &ldst disp=3D0 scale=3D0 size=3D0 t=3D0 sp=3D%assemble_sr3x + &ldst disp=3D0 scale=3D0 size=3D0 t=3D0 sp=3D%assemble_sr3= x w16=3D0 =20 # pdtlbe, pitlbe pxtlbe 000001 b:5 x:5 sp:2 01001001 m:1 ----- \ - &ldst disp=3D0 scale=3D0 size=3D0 t=3D0 + &ldst disp=3D0 scale=3D0 size=3D0 t=3D0 w16=3D0 pxtlbe 000001 b:5 x:5 ... 0001001 m:1 ----- \ - &ldst disp=3D0 scale=3D0 size=3D0 t=3D0 sp=3D%assemble_sr3x + &ldst disp=3D0 scale=3D0 size=3D0 t=3D0 sp=3D%assemble_sr3= x w16=3D0 =20 lpa 000001 b:5 x:5 sp:2 01001101 m:1 t:5 \ - &ldst disp=3D0 scale=3D0 size=3D0 + &ldst disp=3D0 scale=3D0 size=3D0 w16=3D0 =20 lci 000001 ----- ----- -- 01001100 0 t:5 =20 @@ -221,7 +221,7 @@ sub_b_tsv 000010 ..... ..... .... 110100 . ..... = @rrr_cf_d =20 ldil 001000 t:5 ..................... i=3D%assemble_21 addil 001010 r:5 ..................... i=3D%assemble_21 -ldo 001101 b:5 t:5 -- .............. i=3D%lowsign_14 +ldo 001101 b:5 t:5 s:2 .............. i=3D%lowsign_14 w= 16=3D1 =20 addi 101101 ..... ..... .... 0 ........... @rri_cf addi_tsv 101101 ..... ..... .... 1 ........... @rri_cf @@ -264,19 +264,19 @@ permh 111110 r1:5 r2:5 0 c0:2 0 c1:2 c2:2= c3:2 0 t:5 @stim5 ...... b:5 t:5 sp:2 ......... ..... \ &ldst disp=3D%im5_0 x=3D0 scale=3D0 m=3D%ma_to_m =20 -ld 000011 ..... ..... .. . 1 -- 00 size:2 ...... @ldim5 -ld 000011 ..... ..... .. . 0 -- 00 size:2 ...... @ldstx -st 000011 ..... ..... .. . 1 -- 10 size:2 ...... @stim5 -ldc 000011 ..... ..... .. . 1 -- 0111 ...... @ldim5 siz= e=3D2 -ldc 000011 ..... ..... .. . 0 -- 0111 ...... @ldstx siz= e=3D2 -ldc 000011 ..... ..... .. . 1 -- 0101 ...... @ldim5 siz= e=3D3 -ldc 000011 ..... ..... .. . 0 -- 0101 ...... @ldstx siz= e=3D3 -lda 000011 ..... ..... .. . 1 -- 0110 ...... @ldim5 siz= e=3D2 -lda 000011 ..... ..... .. . 0 -- 0110 ...... @ldstx siz= e=3D2 -lda 000011 ..... ..... .. . 1 -- 0100 ...... @ldim5 siz= e=3D3 -lda 000011 ..... ..... .. . 0 -- 0100 ...... @ldstx siz= e=3D3 -sta 000011 ..... ..... .. . 1 -- 1110 ...... @stim5 siz= e=3D2 -sta 000011 ..... ..... .. . 1 -- 1111 ...... @stim5 siz= e=3D3 +ld 000011 ..... ..... .. . 1 -- 00 size:2 ...... @ldim5 w16= =3D0 +ld 000011 ..... ..... .. . 0 -- 00 size:2 ...... @ldstx w16= =3D0 +st 000011 ..... ..... .. . 1 -- 10 size:2 ...... @stim5 w16= =3D0 +ldc 000011 ..... ..... .. . 1 -- 0111 ...... @ldim5 siz= e=3D2 w16=3D0 +ldc 000011 ..... ..... .. . 0 -- 0111 ...... @ldstx siz= e=3D2 w16=3D0 +ldc 000011 ..... ..... .. . 1 -- 0101 ...... @ldim5 siz= e=3D3 w16=3D0 +ldc 000011 ..... ..... .. . 0 -- 0101 ...... @ldstx siz= e=3D3 w16=3D0 +lda 000011 ..... ..... .. . 1 -- 0110 ...... @ldim5 siz= e=3D2 w16=3D0 +lda 000011 ..... ..... .. . 0 -- 0110 ...... @ldstx siz= e=3D2 w16=3D0 +lda 000011 ..... ..... .. . 1 -- 0100 ...... @ldim5 siz= e=3D3 w16=3D0 +lda 000011 ..... ..... .. . 0 -- 0100 ...... @ldstx siz= e=3D3 w16=3D0 +sta 000011 ..... ..... .. . 1 -- 1110 ...... @stim5 siz= e=3D2 w16=3D0 +sta 000011 ..... ..... .. . 1 -- 1111 ...... @stim5 siz= e=3D3 w16=3D0 stby 000011 b:5 r:5 sp:2 a:1 1 -- 1100 m:1 ..... disp=3D%im= 5_0 stdby 000011 b:5 r:5 sp:2 a:1 1 -- 1101 m:1 ..... disp=3D%im= 5_0 =20 @@ -285,20 +285,20 @@ stdby 000011 b:5 r:5 sp:2 a:1 1 -- 1101 m:1= ..... disp=3D%im5_0 @fldstwi ...... b:5 ..... sp:2 . ....... . ..... \ &ldst t=3D%rt64 disp=3D%im5_16 m=3D%ma_to_m x=3D0 scale=3D= 0 size=3D2 =20 -fldw 001001 ..... ..... .. . 0 -- 000 . . ..... @fldstwx -fldw 001001 ..... ..... .. . 1 -- 000 . . ..... @fldstwi -fstw 001001 ..... ..... .. . 0 -- 100 . . ..... @fldstwx -fstw 001001 ..... ..... .. . 1 -- 100 . . ..... @fldstwi +fldw 001001 ..... ..... .. . 0 -- 000 . . ..... @fldstwx w= 16=3D0 +fldw 001001 ..... ..... .. . 1 -- 000 . . ..... @fldstwi w= 16=3D0 +fstw 001001 ..... ..... .. . 0 -- 100 . . ..... @fldstwx w= 16=3D0 +fstw 001001 ..... ..... .. . 1 -- 100 . . ..... @fldstwi w= 16=3D0 =20 @fldstdx ...... b:5 x:5 sp:2 scale:1 ....... m:1 t:5 \ &ldst disp=3D0 size=3D3 @fldstdi ...... b:5 ..... sp:2 . ....... . t:5 \ &ldst disp=3D%im5_16 m=3D%ma_to_m x=3D0 scale=3D0 size=3D3 =20 -fldd 001011 ..... ..... .. . 0 -- 000 0 . ..... @fldstdx -fldd 001011 ..... ..... .. . 1 -- 000 0 . ..... @fldstdi -fstd 001011 ..... ..... .. . 0 -- 100 0 . ..... @fldstdx -fstd 001011 ..... ..... .. . 1 -- 100 0 . ..... @fldstdi +fldd 001011 ..... ..... .. . 0 -- 000 0 . ..... @fldstdx w= 16=3D0 +fldd 001011 ..... ..... .. . 1 -- 000 0 . ..... @fldstdi w= 16=3D0 +fstd 001011 ..... ..... .. . 0 -- 100 0 . ..... @fldstdx w= 16=3D0 +fstd 001011 ..... ..... .. . 1 -- 100 0 . ..... @fldstdi w= 16=3D0 =20 #### # Offset Mem @@ -314,34 +314,35 @@ fstd 001011 ..... ..... .. . 1 -- 100 0 . = ..... @fldstdi &ldst disp=3D%assemble_12a x=3D0 scale=3D0 m=3D%pos_to_m =20 # LDB, LDH, LDW, LDWM -ld 010000 ..... ..... .. .............. @ldstim14 size=3D0 -ld 010001 ..... ..... .. .............. @ldstim14 size=3D1 -ld 010010 ..... ..... .. .............. @ldstim14 size=3D2 -ld 010011 ..... ..... .. .............. @ldstim14m size=3D2 -ld 010111 ..... ..... .. ...........10. @ldstim12m size=3D2 +ld 010000 ..... ..... .. .............. @ldstim14 size=3D= 0 w16=3D1 +ld 010001 ..... ..... .. .............. @ldstim14 size=3D= 1 w16=3D1 +ld 010010 ..... ..... .. .............. @ldstim14 size=3D= 2 w16=3D1 +ld 010011 ..... ..... .. .............. @ldstim14m size=3D= 2 w16=3D1 +ld 010111 ..... ..... .. ...........10. @ldstim12m size=3D= 2 w16=3D1 =20 # STB, STH, STW, STWM -st 011000 ..... ..... .. .............. @ldstim14 size=3D0 -st 011001 ..... ..... .. .............. @ldstim14 size=3D1 -st 011010 ..... ..... .. .............. @ldstim14 size=3D2 -st 011011 ..... ..... .. .............. @ldstim14m size=3D2 -st 011111 ..... ..... .. ...........10. @ldstim12m size=3D2 +st 011000 ..... ..... .. .............. @ldstim14 size=3D= 0 w16=3D1 +st 011001 ..... ..... .. .............. @ldstim14 size=3D= 1 w16=3D1 +st 011010 ..... ..... .. .............. @ldstim14 size=3D= 2 w16=3D1 +st 011011 ..... ..... .. .............. @ldstim14m size=3D= 2 w16=3D1 +st 011111 ..... ..... .. ...........10. @ldstim12m size=3D= 2 w16=3D1 + =20 fldw 010110 b:5 ..... sp:2 .............. \ - &ldst disp=3D%assemble_12a t=3D%rm64 m=3D%a_to_m x=3D0 sca= le=3D0 size=3D2 + &ldst disp=3D%assemble_12a t=3D%rm64 m=3D%a_to_m x=3D0 sca= le=3D0 size=3D2 w16=3D1 fldw 010111 b:5 ..... sp:2 ...........0.. \ - &ldst disp=3D%assemble_12a t=3D%rm64 m=3D0 x=3D0 scale=3D0= size=3D2 + &ldst disp=3D%assemble_12a t=3D%rm64 m=3D0 x=3D0 scale=3D0= size=3D2 w16=3D1 =20 fstw 011110 b:5 ..... sp:2 .............. \ - &ldst disp=3D%assemble_12a t=3D%rm64 m=3D%a_to_m x=3D0 sca= le=3D0 size=3D2 + &ldst disp=3D%assemble_12a t=3D%rm64 m=3D%a_to_m x=3D0 sca= le=3D0 size=3D2 w16=3D1 fstw 011111 b:5 ..... sp:2 ...........0.. \ - &ldst disp=3D%assemble_12a t=3D%rm64 m=3D0 x=3D0 scale=3D0= size=3D2 + &ldst disp=3D%assemble_12a t=3D%rm64 m=3D0 x=3D0 scale=3D0= size=3D2 w16=3D1 =20 -ld 010100 ..... ..... .. ............0. @ldstim11 -fldd 010100 ..... ..... .. ............1. @ldstim11 +ld 010100 ..... ..... .. ............0. @ldstim11 w16=3D1 +fldd 010100 ..... ..... .. ............1. @ldstim11 w16=3D1 =20 -st 011100 ..... ..... .. ............0. @ldstim11 -fstd 011100 ..... ..... .. ............1. @ldstim11 +st 011100 ..... ..... .. ............0. @ldstim11 w16=3D1 +fstd 011100 ..... ..... .. ............1. @ldstim11 w16=3D1 =20 #### # Floating-point Multiply Add diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 01f3188656..b13334e763 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -144,6 +144,14 @@ static int assemble_6(DisasContext *ctx, int val) return (val ^ 31) + 1; } =20 +static int64_t assemble_16(DisasContext *ctx, int64_t i, int64_t s) +{ + if (ctx->tb_flags & PSW_W) { + i ^=3D s << 13; + } + return i; +} + /* Translate CMPI doubleword conditions to standard. */ static int cmpbid_c(DisasContext *ctx, int val) { @@ -3052,6 +3060,11 @@ static bool trans_ld(DisasContext *ctx, arg_ldst *a) } else if (a->size > MO_32) { return gen_illegal(ctx); } + if (a->w16) { + a->disp =3D assemble_16(ctx, a->disp, a->sp); + a->sp =3D 0; + } + return do_load(ctx, a->t, a->b, a->x, a->scale ? a->size : 0, a->disp, a->sp, a->m, a->size | MO_TE); } @@ -3062,6 +3075,11 @@ static bool trans_st(DisasContext *ctx, arg_ldst *a) if (!ctx->is_pa20 && a->size > MO_32) { return gen_illegal(ctx); } + if (a->w16) { + a->disp =3D assemble_16(ctx, a->disp, a->sp); + a->sp =3D 0; + } + return do_store(ctx, a->t, a->b, a->disp, a->sp, a->m, a->size | MO_TE= ); } =20 @@ -3220,6 +3238,10 @@ static bool trans_ldo(DisasContext *ctx, arg_ldo *a) { TCGv_i64 tcg_rt =3D dest_gpr(ctx, a->t); =20 + if (a->w16) { + a->i =3D assemble_16(ctx, a->i, a->s); + } + /* Special case rb =3D=3D 0, for the LDI pseudo-op. The COPY pseudo-op is handled for free within tcg_gen_addi_i64. */ if (a->b =3D=3D 0) { --=20 2.43.2