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[98.147.55.211]) by smtp.gmail.com with ESMTPSA id v8-20020a17090a458800b0029af67d4fd0sm4034901pjg.44.2024.03.01.21.16.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Mar 2024 21:16:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1709356616; x=1709961416; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=VsIJr6QEnw4W2YvjzGDYdqQcqjL5PLIBf0yL49rbXJU=; b=FoJLqy5XVz9JIkzfG4sDjxEN0SxtXefwPgH22QXSYR5oGI5Cn0gsILDlBE8IjBxAoN ZpskAm0JhtalfUYHTBTgr/E8nWWYk/pqzcVowCciZ7XedrJx1Iv6jLhls2AOiWO45PpK 96qtUkfSDM2EvumkI3hOsPrtDO250cZxxLska+9zPZienSD5IDsZQf0R7L23bLh9YdOB Z5O2S82VYyccrTtlM1gLY5Xn6FcoSn0vaoyIMZ2KJpHF/JpvzfM49b1wz9MIqRpBHYU5 GKcdD7PUznprKErPXTw5QpRrLMCvYL5RqRmoyJDoUnFc1f4+ZN6SfdOCCCGi2WV+U2K3 yxzA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1709356616; x=1709961416; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VsIJr6QEnw4W2YvjzGDYdqQcqjL5PLIBf0yL49rbXJU=; b=r1INtZejZEndV++cJGwMjxnmByR9hyXQKHEFZiHg/EONA2gLGPB1KxD7r/g/rP9zMC oY7J+uBQFuDUTGO+iO/CISX1TG6HiIr0vmNrMHDihrKwG4vRHJxNcsGxewGolcKu+6nf aYFMYU4URuZXjaOOEsUhIvkltKDPoc0HNdxpbEmhCfqqlhd1cM6jZ8Jyu8jehvc5jzGY WXj55GSxb1KjOui8jmuT7Ksov2MMYTSgHRgqAoHCsxZrRmlPTIbZji5FUETKfk2LjO2c ApbdZe0xGvF0aKL2fp6XhsqqDJEjKmO/2fgX/JwrrS0ZWHCx0yH+VD84/vKz4/L7OQQV tijQ== X-Gm-Message-State: AOJu0Yx2Xlggx7lh16K6AGuTr9HjnvHkjuznaBRGcPrqcg7MCIW3JPXG omEYGPyfhndey8G5iPX6GJ15wVxx4xTffBSV6Ru0xjP1ni6SL4c/ZjRHZfWoRNmFYfL7r2AkMEA R X-Google-Smtp-Source: AGHT+IEVhDktlnrdfQKspxKxy4mVdMQKj4TAT2bRwX+kYajLNyB3xZYbTHpCWKvYV1L1nHMt+rMx0g== X-Received: by 2002:a17:90a:de8c:b0:296:530:996e with SMTP id n12-20020a17090ade8c00b002960530996emr5028429pjv.20.1709356616645; Fri, 01 Mar 2024 21:16:56 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com Subject: [PATCH 33/41] target/sparc: Add feature bit for VIS4 Date: Fri, 1 Mar 2024 19:15:53 -1000 Message-Id: <20240302051601.53649-34-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240302051601.53649-1-richard.henderson@linaro.org> References: <20240302051601.53649-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1709356847455100014 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/sparc/translate.c | 2 ++ target/sparc/cpu-feature.h.inc | 1 + 2 files changed, 3 insertions(+) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 56ee3927af..77b53cbf3b 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -2402,6 +2402,7 @@ static int extract_qfpreg(DisasContext *dc, int x) # define avail_VIS2(C) ((C)->def->features & CPU_FEATURE_VIS2) # define avail_VIS3(C) ((C)->def->features & CPU_FEATURE_VIS3) # define avail_VIS3B(C) avail_VIS3(C) +# define avail_VIS4(C) ((C)->def->features & CPU_FEATURE_VIS4) #else # define avail_32(C) true # define avail_ASR17(C) ((C)->def->features & CPU_FEATURE_ASR17) @@ -2418,6 +2419,7 @@ static int extract_qfpreg(DisasContext *dc, int x) # define avail_VIS2(C) false # define avail_VIS3(C) false # define avail_VIS3B(C) false +# define avail_VIS4(C) false #endif =20 /* Default case for non jump instructions. */ diff --git a/target/sparc/cpu-feature.h.inc b/target/sparc/cpu-feature.h.inc index e2e6de9144..be81005237 100644 --- a/target/sparc/cpu-feature.h.inc +++ b/target/sparc/cpu-feature.h.inc @@ -15,3 +15,4 @@ FEATURE(CASA) FEATURE(FMAF) FEATURE(VIS3) FEATURE(IMA) +FEATURE(VIS4) --=20 2.34.1