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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id u2-20020adfeb42000000b0033b483d1abcsm5158934wrn.53.2024.03.01.10.32.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Mar 2024 10:32:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1709317943; x=1709922743; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9JEZmlz8rcZzNAyfALikSOUnOYbC8gIs8wauxLnIi0o=; b=Z5js9U12/Dkpl5Kpn6ukVxb8HgTdViDDB4vV6AWSCQmArVZ5lxZkqOBlLlljOwamlN MFMNtGH+g6Hvt+CBo8o8o8v7ih+Fdt2Dq+vLulSBB1JybVD48Jv3jdWXXIRDtOQDo8P/ xbVY1HMATvpcE3Ywqie1W/ejHAQDWxvcNeUl0bynEBgxb6IR35kESNW/Wv50aAklGwA5 5dvSeN+F4o5eftP14L27Eb7QkMsR1gntpTJe+50UwTFRY0kvz0z2vJAFzfv4J3iO8sIM Y+wvSDPvTTNPMFK2Ddnx9wupZ6PluEZijEuxIujUL/7nUn32XQ6Bl1++GvOEV6Uz3wCP pvKQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1709317943; x=1709922743; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9JEZmlz8rcZzNAyfALikSOUnOYbC8gIs8wauxLnIi0o=; b=klgYBfJWZzIXTuJ4EbEn+QDAnPas1IYYAitzgHpY0D0BVHD3182hai3yqRHNFLqG1V //pQhXcFuUxahEvGviAmfrPpJMDR5IdziNFxRwfuV6qlWI7oyGs/eqEKVijr9ySfZ3vO K5IByBrYh3TSJRKF2SNm3InD61oWlfAhAgWjznin3cnEI/qOxDhf0PUBaQmdS0kk480o nyM4/V4Pw0yhppA3VP7yX6igsb6o18oG1DXAXZjrMRsmteMeNx08noqnG3sfiyhdqTmc HDJRF3wwV0DqFNSP+m68mnr4Wpo2AEqS0OKZ9EhMPuPA2sph//Dw2W89GZCq/PVukl1W XURg== X-Forwarded-Encrypted: i=1; AJvYcCVZfHGHdfw6tWXsHGqzLPLTS104K03Us1lL4qa1u1dncCagR2N3tGXWk5D0UZAdnaVCdw4WIc0Tq6ob9cV9tGruAvWfEt4= X-Gm-Message-State: AOJu0Yw8OWPSDUp/61YGAYI3SnUwLJ2hJcUkZ0N4EDk6sWig8yMGYUu/ 04io+GIuq3SccbyH5T8Ow0RJszoWGjGyAbem2xSgf97E2d/RwEVcRtjPhwLJl0I= X-Google-Smtp-Source: AGHT+IFtdV07smIPQ+fubdtE0ivuotzxIquW43aG8eSvLGm92NLYPxlLv3U63nB+AiG5R55zIdnQlg== X-Received: by 2002:adf:a11e:0:b0:33d:b2fe:763c with SMTP id o30-20020adfa11e000000b0033db2fe763cmr1662534wro.33.1709317942908; Fri, 01 Mar 2024 10:32:22 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jean-Philippe Brucker Subject: [PATCH 4/8] target/arm: Don't allow RES0 CNTHCTL_EL2 bits to be written Date: Fri, 1 Mar 2024 18:32:15 +0000 Message-Id: <20240301183219.2424889-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240301183219.2424889-1-peter.maydell@linaro.org> References: <20240301183219.2424889-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1709318021634100003 Content-Type: text/plain; charset="utf-8" Don't allow the guest to write CNTHCTL_EL2 bits which don't exist. This is not strictly architecturally required, but it is how we've tended to implement registers more recently. In particular, bits [19:18] are only present with FEAT_RME, and bits [17:12] will only be present with FEAT_ECV. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index 1c82d12a883..8ec61c12440 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2968,6 +2968,24 @@ static void gt_cnthctl_write(CPUARMState *env, const= ARMCPRegInfo *ri, { ARMCPU *cpu =3D env_archcpu(env); uint32_t oldval =3D env->cp15.cnthctl_el2; + uint32_t valid_mask =3D + R_CNTHCTL_EL0PCTEN_MASK | + R_CNTHCTL_EL0VCTEN_MASK | + R_CNTHCTL_EVNTEN_MASK | + R_CNTHCTL_EVNTDIR_MASK | + R_CNTHCTL_EVNTI_MASK | + R_CNTHCTL_EL0VTEN_MASK | + R_CNTHCTL_EL0PTEN_MASK | + R_CNTHCTL_EL1PCTEN_MASK | + R_CNTHCTL_EL1PTEN_MASK; + + if (cpu_isar_feature(aa64_rme, cpu)) { + valid_mask |=3D R_CNTHCTL_CNTVMASK_MASK | R_CNTHCTL_CNTPMASK_MASK; + } + + /* Clear RES0 bits */ + value &=3D valid_mask; + raw_write(env, ri, value); =20 if ((oldval ^ value) & R_CNTHCTL_CNTVMASK_MASK) { --=20 2.34.1