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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id u2-20020adfeb42000000b0033b483d1abcsm5158934wrn.53.2024.03.01.10.32.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Mar 2024 10:32:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1709317942; x=1709922742; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=vW+yQ7fC5/gtJ1ZucfqHiSEvlgkB6rWP3jPeBXaxNb0=; b=JLoz1I6AG+0qpUWT/EX1Y4CFcs0ZXgZtvj7mfpdQo8+Ncb1pj9ABk4G/dkZsVQrR4E 3qD4azI82NF0hjjQe0VgWQjqDsHcz72Cu1/SVKdDUb51ZKin6cZ+/DfKbBh/2TEFNBHl iIHuq6AbjwS6Sj/1Sm9JX1viKi4t5HlKB+BgIxoOlvul0FNMkL88401RwG7t1Loabo9D Fao4j3eJLA6ZurGUavCJDG666A5Z8tAV/dbySZ5hGPNhn+F7i+JBaKHSMgSa6zmBvBsi QGQ0drOiqvQdWvIzakjI5bSttm1g1RUv13aL9ggnmRtDOkHrOzBUQpWkK2Y4jb5akYdG ZydQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1709317942; x=1709922742; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vW+yQ7fC5/gtJ1ZucfqHiSEvlgkB6rWP3jPeBXaxNb0=; b=OJe1Z60MhkIHE6CAuW3FgLlPNfqcvX5UMKGYVl6bLqvYLu2S4yZ3Jd7yIVP0cWY8YZ PovA6nvYf2fSopVUwi3G/U7aQ+OyIxLwZ6rV9wOYmnJNwS3CUrUPaKn6gxHEodN6b5/n 4aT7xOWC/3WMy1yqi0392iLwruKX9EjjosN9hSsWewC2WnzvC8dBGrc1tcCQQIfyqprz 1lRgqZizc8+9MPMlo6DUPuSSInzQ3SHrRFHw0BxuNWNh+EnBinpWLtbk+tFnSg0jH/rE tyDNq97ThDt9du3hPvGOFUBpqPkEz312JX+LiyCDrmpBCejDY7Pq9+YhyycafHIn01uQ 1h6A== X-Forwarded-Encrypted: i=1; AJvYcCXQg0ysZpOqMmOkcn73Q2N8TFT7idbDtx0aBKTJcxUCQkFQmTLFLWYBc19shruUMvRIMDIgHUrF/Hs4GGAKyjc3FgT3+50= X-Gm-Message-State: AOJu0Yy4Jb6M7MbLhHw/x4rFFkYBKBXsiMUgu1X1NyHosV3iPK2zyUcP Rqdu3D4HPhCiFzUlclC1A+uD2tFAR0RMWY+FAcDHZW4JBlQutwCuZv7kwVQEb+k= X-Google-Smtp-Source: AGHT+IEIA/FbsBKxj9M9gSUuyxKtd9MNADHamFJhCCVXfOUjaqdKEIGObmfmud5o3lUYGBFRl5zlSA== X-Received: by 2002:a05:600c:35d5:b0:412:ad64:cc64 with SMTP id r21-20020a05600c35d500b00412ad64cc64mr2174371wmq.1.1709317941622; Fri, 01 Mar 2024 10:32:21 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jean-Philippe Brucker Subject: [PATCH 1/8] target/arm: Move some register related defines to internals.h Date: Fri, 1 Mar 2024 18:32:12 +0000 Message-Id: <20240301183219.2424889-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240301183219.2424889-1-peter.maydell@linaro.org> References: <20240301183219.2424889-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1709318085993100001 Content-Type: text/plain; charset="utf-8" cpu.h has a lot of #defines relating to CPU register fields. Most of these aren't actually used outside target/arm code, so there's no point in cluttering up the cpu.h file with them. Move some easy ones to internals.h. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- I want to add some more CNTHCTL_* values, and don't really want to put more into cpu.h. There's obviously more that could be moved here, but I don't want to get into doing too much all at once. I pondered having a different file for these, but probably we'd end up pulling it in everywhere we do internals.h. --- target/arm/cpu.h | 128 ----------------------------------------- target/arm/internals.h | 128 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 128 insertions(+), 128 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 63f31e0d984..3cbfd4f9a74 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -141,11 +141,6 @@ typedef struct ARMGenericTimer { uint64_t ctl; /* Timer Control register */ } ARMGenericTimer; =20 -#define VTCR_NSW (1u << 29) -#define VTCR_NSA (1u << 30) -#define VSTCR_SW VTCR_NSW -#define VSTCR_SA VTCR_NSA - /* Define a maximum sized vector register. * For 32-bit, this is a 128-bit NEON/AdvSIMD register. * For 64-bit, this is a 2048-bit SVE register. @@ -1382,73 +1377,6 @@ void pmu_init(ARMCPU *cpu); #define SCTLR_SPINTMASK (1ULL << 62) /* FEAT_NMI */ #define SCTLR_TIDCP (1ULL << 63) /* FEAT_TIDCP1 */ =20 -/* Bit definitions for CPACR (AArch32 only) */ -FIELD(CPACR, CP10, 20, 2) -FIELD(CPACR, CP11, 22, 2) -FIELD(CPACR, TRCDIS, 28, 1) /* matches CPACR_EL1.TTA */ -FIELD(CPACR, D32DIS, 30, 1) /* up to v7; RAZ in v8 */ -FIELD(CPACR, ASEDIS, 31, 1) - -/* Bit definitions for CPACR_EL1 (AArch64 only) */ -FIELD(CPACR_EL1, ZEN, 16, 2) -FIELD(CPACR_EL1, FPEN, 20, 2) -FIELD(CPACR_EL1, SMEN, 24, 2) -FIELD(CPACR_EL1, TTA, 28, 1) /* matches CPACR.TRCDIS */ - -/* Bit definitions for HCPTR (AArch32 only) */ -FIELD(HCPTR, TCP10, 10, 1) -FIELD(HCPTR, TCP11, 11, 1) -FIELD(HCPTR, TASE, 15, 1) -FIELD(HCPTR, TTA, 20, 1) -FIELD(HCPTR, TAM, 30, 1) /* matches CPTR_EL2.TAM */ -FIELD(HCPTR, TCPAC, 31, 1) /* matches CPTR_EL2.TCPAC */ - -/* Bit definitions for CPTR_EL2 (AArch64 only) */ -FIELD(CPTR_EL2, TZ, 8, 1) /* !E2H */ -FIELD(CPTR_EL2, TFP, 10, 1) /* !E2H, matches HCPTR.TCP10 */ -FIELD(CPTR_EL2, TSM, 12, 1) /* !E2H */ -FIELD(CPTR_EL2, ZEN, 16, 2) /* E2H */ -FIELD(CPTR_EL2, FPEN, 20, 2) /* E2H */ -FIELD(CPTR_EL2, SMEN, 24, 2) /* E2H */ -FIELD(CPTR_EL2, TTA, 28, 1) -FIELD(CPTR_EL2, TAM, 30, 1) /* matches HCPTR.TAM */ -FIELD(CPTR_EL2, TCPAC, 31, 1) /* matches HCPTR.TCPAC */ - -/* Bit definitions for CPTR_EL3 (AArch64 only) */ -FIELD(CPTR_EL3, EZ, 8, 1) -FIELD(CPTR_EL3, TFP, 10, 1) -FIELD(CPTR_EL3, ESM, 12, 1) -FIELD(CPTR_EL3, TTA, 20, 1) -FIELD(CPTR_EL3, TAM, 30, 1) -FIELD(CPTR_EL3, TCPAC, 31, 1) - -#define MDCR_MTPME (1U << 28) -#define MDCR_TDCC (1U << 27) -#define MDCR_HLP (1U << 26) /* MDCR_EL2 */ -#define MDCR_SCCD (1U << 23) /* MDCR_EL3 */ -#define MDCR_HCCD (1U << 23) /* MDCR_EL2 */ -#define MDCR_EPMAD (1U << 21) -#define MDCR_EDAD (1U << 20) -#define MDCR_TTRF (1U << 19) -#define MDCR_STE (1U << 18) /* MDCR_EL3 */ -#define MDCR_SPME (1U << 17) /* MDCR_EL3 */ -#define MDCR_HPMD (1U << 17) /* MDCR_EL2 */ -#define MDCR_SDD (1U << 16) -#define MDCR_SPD (3U << 14) -#define MDCR_TDRA (1U << 11) -#define MDCR_TDOSA (1U << 10) -#define MDCR_TDA (1U << 9) -#define MDCR_TDE (1U << 8) -#define MDCR_HPME (1U << 7) -#define MDCR_TPM (1U << 6) -#define MDCR_TPMCR (1U << 5) -#define MDCR_HPMN (0x1fU) - -/* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */ -#define SDCR_VALID_MASK (MDCR_MTPME | MDCR_TDCC | MDCR_SCCD | \ - MDCR_EPMAD | MDCR_EDAD | MDCR_TTRF | \ - MDCR_STE | MDCR_SPME | MDCR_SPD) - #define CPSR_M (0x1fU) #define CPSR_T (1U << 5) #define CPSR_F (1U << 6) @@ -1495,41 +1423,6 @@ FIELD(CPTR_EL3, TCPAC, 31, 1) #define XPSR_NZCV CPSR_NZCV #define XPSR_IT CPSR_IT =20 -#define TTBCR_N (7U << 0) /* TTBCR.EAE=3D=3D0 */ -#define TTBCR_T0SZ (7U << 0) /* TTBCR.EAE=3D=3D1 */ -#define TTBCR_PD0 (1U << 4) -#define TTBCR_PD1 (1U << 5) -#define TTBCR_EPD0 (1U << 7) -#define TTBCR_IRGN0 (3U << 8) -#define TTBCR_ORGN0 (3U << 10) -#define TTBCR_SH0 (3U << 12) -#define TTBCR_T1SZ (3U << 16) -#define TTBCR_A1 (1U << 22) -#define TTBCR_EPD1 (1U << 23) -#define TTBCR_IRGN1 (3U << 24) -#define TTBCR_ORGN1 (3U << 26) -#define TTBCR_SH1 (1U << 28) -#define TTBCR_EAE (1U << 31) - -FIELD(VTCR, T0SZ, 0, 6) -FIELD(VTCR, SL0, 6, 2) -FIELD(VTCR, IRGN0, 8, 2) -FIELD(VTCR, ORGN0, 10, 2) -FIELD(VTCR, SH0, 12, 2) -FIELD(VTCR, TG0, 14, 2) -FIELD(VTCR, PS, 16, 3) -FIELD(VTCR, VS, 19, 1) -FIELD(VTCR, HA, 21, 1) -FIELD(VTCR, HD, 22, 1) -FIELD(VTCR, HWU59, 25, 1) -FIELD(VTCR, HWU60, 26, 1) -FIELD(VTCR, HWU61, 27, 1) -FIELD(VTCR, HWU62, 28, 1) -FIELD(VTCR, NSW, 29, 1) -FIELD(VTCR, NSA, 30, 1) -FIELD(VTCR, DS, 32, 1) -FIELD(VTCR, SL2, 33, 1) - /* Bit definitions for ARMv8 SPSR (PSTATE) format. * Only these are valid when in AArch64 mode; in * AArch32 mode SPSRs are basically CPSR-format. @@ -1737,21 +1630,6 @@ static inline void xpsr_write(CPUARMState *env, uint= 32_t val, uint32_t mask) #define HCR_TWEDEN (1ULL << 59) #define HCR_TWEDEL MAKE_64BIT_MASK(60, 4) =20 -#define HCRX_ENAS0 (1ULL << 0) -#define HCRX_ENALS (1ULL << 1) -#define HCRX_ENASR (1ULL << 2) -#define HCRX_FNXS (1ULL << 3) -#define HCRX_FGTNXS (1ULL << 4) -#define HCRX_SMPME (1ULL << 5) -#define HCRX_TALLINT (1ULL << 6) -#define HCRX_VINMI (1ULL << 7) -#define HCRX_VFNMI (1ULL << 8) -#define HCRX_CMOW (1ULL << 9) -#define HCRX_MCE2 (1ULL << 10) -#define HCRX_MSCEN (1ULL << 11) - -#define HPFAR_NS (1ULL << 63) - #define SCR_NS (1ULL << 0) #define SCR_IRQ (1ULL << 1) #define SCR_FIQ (1ULL << 2) @@ -1790,12 +1668,6 @@ static inline void xpsr_write(CPUARMState *env, uint= 32_t val, uint32_t mask) #define SCR_GPF (1ULL << 48) #define SCR_NSE (1ULL << 62) =20 -#define HSTR_TTEE (1 << 16) -#define HSTR_TJDBX (1 << 17) - -#define CNTHCTL_CNTVMASK (1 << 18) -#define CNTHCTL_CNTPMASK (1 << 19) - /* Return the current FPSCR value. */ uint32_t vfp_get_fpscr(CPUARMState *env); void vfp_set_fpscr(CPUARMState *env, uint32_t val); diff --git a/target/arm/internals.h b/target/arm/internals.h index 50bff445494..c93acb270cc 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -99,6 +99,134 @@ FIELD(DBGWCR, WT, 20, 1) FIELD(DBGWCR, MASK, 24, 5) FIELD(DBGWCR, SSCE, 29, 1) =20 +#define VTCR_NSW (1u << 29) +#define VTCR_NSA (1u << 30) +#define VSTCR_SW VTCR_NSW +#define VSTCR_SA VTCR_NSA + +/* Bit definitions for CPACR (AArch32 only) */ +FIELD(CPACR, CP10, 20, 2) +FIELD(CPACR, CP11, 22, 2) +FIELD(CPACR, TRCDIS, 28, 1) /* matches CPACR_EL1.TTA */ +FIELD(CPACR, D32DIS, 30, 1) /* up to v7; RAZ in v8 */ +FIELD(CPACR, ASEDIS, 31, 1) + +/* Bit definitions for CPACR_EL1 (AArch64 only) */ +FIELD(CPACR_EL1, ZEN, 16, 2) +FIELD(CPACR_EL1, FPEN, 20, 2) +FIELD(CPACR_EL1, SMEN, 24, 2) +FIELD(CPACR_EL1, TTA, 28, 1) /* matches CPACR.TRCDIS */ + +/* Bit definitions for HCPTR (AArch32 only) */ +FIELD(HCPTR, TCP10, 10, 1) +FIELD(HCPTR, TCP11, 11, 1) +FIELD(HCPTR, TASE, 15, 1) +FIELD(HCPTR, TTA, 20, 1) +FIELD(HCPTR, TAM, 30, 1) /* matches CPTR_EL2.TAM */ +FIELD(HCPTR, TCPAC, 31, 1) /* matches CPTR_EL2.TCPAC */ + +/* Bit definitions for CPTR_EL2 (AArch64 only) */ +FIELD(CPTR_EL2, TZ, 8, 1) /* !E2H */ +FIELD(CPTR_EL2, TFP, 10, 1) /* !E2H, matches HCPTR.TCP10 */ +FIELD(CPTR_EL2, TSM, 12, 1) /* !E2H */ +FIELD(CPTR_EL2, ZEN, 16, 2) /* E2H */ +FIELD(CPTR_EL2, FPEN, 20, 2) /* E2H */ +FIELD(CPTR_EL2, SMEN, 24, 2) /* E2H */ +FIELD(CPTR_EL2, TTA, 28, 1) +FIELD(CPTR_EL2, TAM, 30, 1) /* matches HCPTR.TAM */ +FIELD(CPTR_EL2, TCPAC, 31, 1) /* matches HCPTR.TCPAC */ + +/* Bit definitions for CPTR_EL3 (AArch64 only) */ +FIELD(CPTR_EL3, EZ, 8, 1) +FIELD(CPTR_EL3, TFP, 10, 1) +FIELD(CPTR_EL3, ESM, 12, 1) +FIELD(CPTR_EL3, TTA, 20, 1) +FIELD(CPTR_EL3, TAM, 30, 1) +FIELD(CPTR_EL3, TCPAC, 31, 1) + +#define MDCR_MTPME (1U << 28) +#define MDCR_TDCC (1U << 27) +#define MDCR_HLP (1U << 26) /* MDCR_EL2 */ +#define MDCR_SCCD (1U << 23) /* MDCR_EL3 */ +#define MDCR_HCCD (1U << 23) /* MDCR_EL2 */ +#define MDCR_EPMAD (1U << 21) +#define MDCR_EDAD (1U << 20) +#define MDCR_TTRF (1U << 19) +#define MDCR_STE (1U << 18) /* MDCR_EL3 */ +#define MDCR_SPME (1U << 17) /* MDCR_EL3 */ +#define MDCR_HPMD (1U << 17) /* MDCR_EL2 */ +#define MDCR_SDD (1U << 16) +#define MDCR_SPD (3U << 14) +#define MDCR_TDRA (1U << 11) +#define MDCR_TDOSA (1U << 10) +#define MDCR_TDA (1U << 9) +#define MDCR_TDE (1U << 8) +#define MDCR_HPME (1U << 7) +#define MDCR_TPM (1U << 6) +#define MDCR_TPMCR (1U << 5) +#define MDCR_HPMN (0x1fU) + +/* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */ +#define SDCR_VALID_MASK (MDCR_MTPME | MDCR_TDCC | MDCR_SCCD | \ + MDCR_EPMAD | MDCR_EDAD | MDCR_TTRF | \ + MDCR_STE | MDCR_SPME | MDCR_SPD) + +#define TTBCR_N (7U << 0) /* TTBCR.EAE=3D=3D0 */ +#define TTBCR_T0SZ (7U << 0) /* TTBCR.EAE=3D=3D1 */ +#define TTBCR_PD0 (1U << 4) +#define TTBCR_PD1 (1U << 5) +#define TTBCR_EPD0 (1U << 7) +#define TTBCR_IRGN0 (3U << 8) +#define TTBCR_ORGN0 (3U << 10) +#define TTBCR_SH0 (3U << 12) +#define TTBCR_T1SZ (3U << 16) +#define TTBCR_A1 (1U << 22) +#define TTBCR_EPD1 (1U << 23) +#define TTBCR_IRGN1 (3U << 24) +#define TTBCR_ORGN1 (3U << 26) +#define TTBCR_SH1 (1U << 28) +#define TTBCR_EAE (1U << 31) + +FIELD(VTCR, T0SZ, 0, 6) +FIELD(VTCR, SL0, 6, 2) +FIELD(VTCR, IRGN0, 8, 2) +FIELD(VTCR, ORGN0, 10, 2) +FIELD(VTCR, SH0, 12, 2) +FIELD(VTCR, TG0, 14, 2) +FIELD(VTCR, PS, 16, 3) +FIELD(VTCR, VS, 19, 1) +FIELD(VTCR, HA, 21, 1) +FIELD(VTCR, HD, 22, 1) +FIELD(VTCR, HWU59, 25, 1) +FIELD(VTCR, HWU60, 26, 1) +FIELD(VTCR, HWU61, 27, 1) +FIELD(VTCR, HWU62, 28, 1) +FIELD(VTCR, NSW, 29, 1) +FIELD(VTCR, NSA, 30, 1) +FIELD(VTCR, DS, 32, 1) +FIELD(VTCR, SL2, 33, 1) + +#define HCRX_ENAS0 (1ULL << 0) +#define HCRX_ENALS (1ULL << 1) +#define HCRX_ENASR (1ULL << 2) +#define HCRX_FNXS (1ULL << 3) +#define HCRX_FGTNXS (1ULL << 4) +#define HCRX_SMPME (1ULL << 5) +#define HCRX_TALLINT (1ULL << 6) +#define HCRX_VINMI (1ULL << 7) +#define HCRX_VFNMI (1ULL << 8) +#define HCRX_CMOW (1ULL << 9) +#define HCRX_MCE2 (1ULL << 10) +#define HCRX_MSCEN (1ULL << 11) + +#define HPFAR_NS (1ULL << 63) + +#define HSTR_TTEE (1 << 16) +#define HSTR_TJDBX (1 << 17) + +#define CNTHCTL_CNTVMASK (1 << 18) +#define CNTHCTL_CNTPMASK (1 << 19) + /* We use a few fake FSR values for internal purposes in M profile. * M profile cores don't have A/R format FSRs, but currently our * get_phys_addr() code assumes A/R profile and reports failures via --=20 2.34.1 From nobody Tue Nov 26 06:33:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id u2-20020adfeb42000000b0033b483d1abcsm5158934wrn.53.2024.03.01.10.32.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Mar 2024 10:32:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1709317942; x=1709922742; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ug89tsgOuUzq4MSu20MZm19VI4nBxO1N6UPUttck1FU=; b=BQWWLHIHzvh68hMEDDX9/mbZCmafIcS0q6ZDaWOYJZrtDJnClNV3cTuBP1z+6ZXS2B ydjMIdWq1pC/uqu9HrHE5jifA6J9aJ7lfm1fwaFObezQOwDJ0lgxYj0fqI4oHrwEC3Zl zJD7dleaH8snaQ4xkWL1bI/QuXJkqugPxLrS3IypMMMLgI9melY4UHWQn+WjmT4cfvc9 VqRKiXa7AtFVsYMn/x28URTDIuLphXKjxORBOAtu77Onc2FAqagUye7hbEdOLwO6WFSg kEHue9AKseQzSo7z3xogZznI3pGCHmGHaTFv/6Axqytlpa1OoD+UJBXAmkrTxqkFg1g5 jKkg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1709317942; x=1709922742; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ug89tsgOuUzq4MSu20MZm19VI4nBxO1N6UPUttck1FU=; b=XFjLYXgMJsg9OWwlXr2gdtdrcHSFZLr2cIoo16C8ZrpDg26Vz9ziR3b+ejz81JzVDp 1u6d7l/IhN7Cbsi4Mal2HpUYLoaS1Oay4e6ya+VLlj44oux9ERKETi/ekg692LHlw3vm yAfGgfbHcOUn9okEstpCk5nONHTVC01pfC+pL/G7SD6Cwt+E5NB72sRo92AjrNK20A3S /R2ku0IUrGtLC5rMz5oovMQgjqeWGX8c96gBK/yRiXmBgbMwmuhYmAoLsp56vz62Xlb6 b18VsaDS5NCAHQd/A6I1jsdyrpcYo4T9/1WQakM/cNY/mgfmy1LfEjOh/qKvo3bX9E4G i/QA== X-Forwarded-Encrypted: i=1; AJvYcCV69bG6YxxHKU6yMv66JVhoJotnMRISOn0sta+061wD8WupmoK65ZfOIGbwTW4jPEVkV6QVpicJ6PrVcez5K+7CyV12PRs= X-Gm-Message-State: AOJu0YxfXX6JxExsZluBp25KHfysZ7CMuPIEvTwE1VhQc+/+HOAeo+w9 gZ8u0ervpNsK7xYKPllxlJEH1ln5aGsSyqolZQWytWJOmRgwMa9K82rjJuGKWcg= X-Google-Smtp-Source: AGHT+IGSxIVHkn5oIZjsAY1kslwbRl5malwilqxnbBQ/2xTGZdMT4X8W280rHhHqp3cmm07IK9o/Fg== X-Received: by 2002:adf:ec90:0:b0:33d:746b:f365 with SMTP id z16-20020adfec90000000b0033d746bf365mr1762332wrn.52.1709317942051; Fri, 01 Mar 2024 10:32:22 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jean-Philippe Brucker Subject: [PATCH 2/8] target/arm: Timer _EL02 registers UNDEF for E2H == 0 Date: Fri, 1 Mar 2024 18:32:13 +0000 Message-Id: <20240301183219.2424889-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240301183219.2424889-1-peter.maydell@linaro.org> References: <20240301183219.2424889-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1709318071860100001 Content-Type: text/plain; charset="utf-8" The timer _EL02 registers should UNDEF for invalid accesses from EL2 or EL3 when HCR_EL2.E2H =3D=3D 0, not take a cp access trap. We were delivering the exception to EL2 with the wrong syndrome. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 90c4fb72ce4..978df6f2823 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6551,7 +6551,7 @@ static CPAccessResult e2h_access(CPUARMState *env, co= nst ARMCPRegInfo *ri, return CP_ACCESS_OK; } if (!(arm_hcr_el2_eff(env) & HCR_E2H)) { - return CP_ACCESS_TRAP; + return CP_ACCESS_TRAP_UNCATEGORIZED; } return CP_ACCESS_OK; } --=20 2.34.1 From nobody Tue Nov 26 06:33:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1709318036; cv=none; d=zohomail.com; s=zohoarc; b=gAQsKDGKJw6ak7W6nthsPaL8FfBfgA/Z6EEylg2Sn5XlhfFEdp1Pp6c3G1ciRs1/zF9zaRwX7by1W+6fG2nQBv+rgniEOcC4GPEPjNbSd5hFHy3aXCrAU63rAjZmqnXp4AVnUbT+NJJSMk4mt9MICgwOLLeO7Qi5Uh+oMlww4y8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1709318036; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=D3Hu107iW344nRvBUzZVDNr0+oMATVeZKj7eB9sfDUQ=; b=mH++ahi6lj/H+AUEDXHWRkNJvMblaDR2dbO1DbDJKMSgoH3WfkX4mCgi7dAQ9olbVf7IqPH/di/99rhitWwNN5xs6kInu8y257ThuuNlbI8X/LNonDRYXd7hXdLjmRs/bEIRS8lCdaxuDX/UtiScchT2fDZSFK4sQI3roy/rJR0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1709318036401840.4140206213755; Fri, 1 Mar 2024 10:33:56 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rg7gS-0006T0-F9; Fri, 01 Mar 2024 13:32:36 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rg7gK-0006PU-5Z for qemu-devel@nongnu.org; Fri, 01 Mar 2024 13:32:29 -0500 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rg7gF-0008KF-PC for qemu-devel@nongnu.org; Fri, 01 Mar 2024 13:32:27 -0500 Received: by mail-wm1-x32d.google.com with SMTP id 5b1f17b1804b1-412bb23e5c5so13708415e9.1 for ; Fri, 01 Mar 2024 10:32:23 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id u2-20020adfeb42000000b0033b483d1abcsm5158934wrn.53.2024.03.01.10.32.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Mar 2024 10:32:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1709317942; x=1709922742; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=D3Hu107iW344nRvBUzZVDNr0+oMATVeZKj7eB9sfDUQ=; b=gIpRDTRAz2yB//DGQ5YAGb+i+UOHB/RGIuIqyrm4hmxuX/uHsW9+A2qTaZ4r+6QaiC Jmpe1awuIcP8tGSm0Feh3CsbzRONpSPpcfUiDKNPUFWFPNMQf+yGONlPLjyCFMc1Wm01 TRJst+4lh0kryfydqYb3St3c+tSbyc4MIEgpulc3IMiZRkR1bpcNYyNhqCoKpmYzGpkT hZx6JHqOkpTDPyDBSzE38s5iRv1dSZkfK4f9sosP/XcoLGV1Jam99+1OaylthiX3S1me +uK9oQJCuiwxO/TI41jMtYYLyIwoSl/yA+QhdQV9ZTCLwyjUTX4MFfvIDFx5xXQGT5uJ 3IMw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1709317942; x=1709922742; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=D3Hu107iW344nRvBUzZVDNr0+oMATVeZKj7eB9sfDUQ=; b=k6l4q8/7j15ZJvzKICWONtao+qbF9HRgxGTTpuJm3d6+jYCJJKcXm8japtFXL9pQvR /zgfYnHKn0sXrl+Dqtk3yCKUIfy6REF1I2DQ4sYaL4t1EQ9IwCbnFFizd5p540G5sLrb cBTKZwlOatZq1SjqJcKNzqSTOD5bLbko8FmIEeuZOAgZrVoQR1oa8ba/I+JlbjpP+MBl ZMJkAsTHftVsG7mQ1UNeDGFvkuvpl/YM/4U4tHcXkdX/pHDrM8cEQNabQQORzSjmG7ys IabxbMmm2V4ZFVTcNUKFADy15nny79Rb1bVe4TxHmyetNbZxXr0k/+uVwt9mF13sxmco yVkw== X-Forwarded-Encrypted: i=1; AJvYcCUOmgth+f0GL1M4TcIcDvNnqazW8mbfOotQ7pL9torQ8WVwuZOtUSh1WDQWba9jOidGhjFpaquALZBwDJD8Y8ZUYoOfPhQ= X-Gm-Message-State: AOJu0YwbKn5t+QjXHoNvs/m85XQFJuC/gNtUyaDAcLNCxa7cmyncJqc5 Zkk1829q0AZ2E8xuEhj9jiemUw37ifUWMqrwGwAH9q4FP3bZgHIkiW8wyQj92Iw= X-Google-Smtp-Source: AGHT+IEMyhUzMydCiWsZmKoX8F79c0mzD0sZrJ7tZlm4jyRXvFJdFhMqkmVXqsjIH8Ok114zAyFeZA== X-Received: by 2002:a05:600c:4fcc:b0:412:b8ce:a0f7 with SMTP id o12-20020a05600c4fcc00b00412b8cea0f7mr3095242wmq.5.1709317942482; Fri, 01 Mar 2024 10:32:22 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jean-Philippe Brucker Subject: [PATCH 3/8] target/arm: use FIELD macro for CNTHCTL bit definitions Date: Fri, 1 Mar 2024 18:32:14 +0000 Message-Id: <20240301183219.2424889-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240301183219.2424889-1-peter.maydell@linaro.org> References: <20240301183219.2424889-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1709318037692100001 Content-Type: text/plain; charset="utf-8" We prefer the FIELD macro over ad-hoc #defines for register bits; switch CNTHCTL to that style before we add any more bits. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/arm/internals.h | 19 +++++++++++++++++-- target/arm/helper.c | 9 ++++----- 2 files changed, 21 insertions(+), 7 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index c93acb270cc..6553e414934 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -224,8 +224,23 @@ FIELD(VTCR, SL2, 33, 1) #define HSTR_TTEE (1 << 16) #define HSTR_TJDBX (1 << 17) =20 -#define CNTHCTL_CNTVMASK (1 << 18) -#define CNTHCTL_CNTPMASK (1 << 19) +FIELD(CNTHCTL, EL0PCTEN, 0, 1) +FIELD(CNTHCTL, EL0VCTEN, 1, 1) +FIELD(CNTHCTL, EVNTEN, 2, 1) +FIELD(CNTHCTL, EVNTDIR, 3, 1) +FIELD(CNTHCTL, EVNTI, 4, 4) +FIELD(CNTHCTL, EL0VTEN, 8, 1) +FIELD(CNTHCTL, EL0PTEN, 9, 1) +FIELD(CNTHCTL, EL1PCTEN, 10, 1) +FIELD(CNTHCTL, EL1PTEN, 11, 1) +FIELD(CNTHCTL, ECV, 12, 1) +FIELD(CNTHCTL, EL1TVT, 13, 1) +FIELD(CNTHCTL, EL1TVCT, 14, 1) +FIELD(CNTHCTL, EL1NVPCT, 15, 1) +FIELD(CNTHCTL, EL1NVVCT, 16, 1) +FIELD(CNTHCTL, EVNTIS, 17, 1) +FIELD(CNTHCTL, CNTVMASK, 18, 1) +FIELD(CNTHCTL, CNTPMASK, 19, 1) =20 /* We use a few fake FSR values for internal purposes in M profile. * M profile cores don't have A/R format FSRs, but currently our diff --git a/target/arm/helper.c b/target/arm/helper.c index 978df6f2823..1c82d12a883 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2652,8 +2652,8 @@ static void gt_update_irq(ARMCPU *cpu, int timeridx) * It is RES0 in Secure and NonSecure state. */ if ((ss =3D=3D ARMSS_Root || ss =3D=3D ARMSS_Realm) && - ((timeridx =3D=3D GTIMER_VIRT && (cnthctl & CNTHCTL_CNTVMASK)) || - (timeridx =3D=3D GTIMER_PHYS && (cnthctl & CNTHCTL_CNTPMASK)))) { + ((timeridx =3D=3D GTIMER_VIRT && (cnthctl & R_CNTHCTL_CNTVMASK_MAS= K)) || + (timeridx =3D=3D GTIMER_PHYS && (cnthctl & R_CNTHCTL_CNTPMASK_MAS= K)))) { irqstate =3D 0; } =20 @@ -2968,12 +2968,11 @@ static void gt_cnthctl_write(CPUARMState *env, cons= t ARMCPRegInfo *ri, { ARMCPU *cpu =3D env_archcpu(env); uint32_t oldval =3D env->cp15.cnthctl_el2; - raw_write(env, ri, value); =20 - if ((oldval ^ value) & CNTHCTL_CNTVMASK) { + if ((oldval ^ value) & R_CNTHCTL_CNTVMASK_MASK) { gt_update_irq(cpu, GTIMER_VIRT); - } else if ((oldval ^ value) & CNTHCTL_CNTPMASK) { + } else if ((oldval ^ value) & R_CNTHCTL_CNTPMASK_MASK) { gt_update_irq(cpu, GTIMER_PHYS); } } --=20 2.34.1 From nobody Tue Nov 26 06:33:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1709318019; cv=none; d=zohomail.com; s=zohoarc; b=Sr/5epFr0DNFkyf4SXA5EKB6xcqyjHym3kquddgKmW7oqlnp9MLZhFhrGnGD4gzL5sgauzMMgUfZ796M+0K63sjzr9pNV18C01tq+9DBrNPSLUVyDeI8Nj+hRZwoHWPwZadkw/gSmMwzXNQA1WnIZlcz4TjD2UWjhf/OhrOxbCM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1709318019; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=9JEZmlz8rcZzNAyfALikSOUnOYbC8gIs8wauxLnIi0o=; b=FtOYGU1J2iwgAOjW21O1ytyboG0e06406iFFW54fTeMuNPXWJxVSpfNk4JRRRRhro2ZXf/b4gNtiid4wYVDoVeb/WQQnN3w5O19rIyBVR/wryADSki8SRLyc0vaSgRWcHz/2tdrVStFvIXdSK2p0TfvoKdBrKk506Nf7a9A3NNA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1709318019796464.0510190846338; Fri, 1 Mar 2024 10:33:39 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rg7gU-0006Ue-74; Fri, 01 Mar 2024 13:32:38 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rg7gK-0006PW-Cy for qemu-devel@nongnu.org; Fri, 01 Mar 2024 13:32:30 -0500 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rg7gG-0008Kq-LO for qemu-devel@nongnu.org; Fri, 01 Mar 2024 13:32:28 -0500 Received: by mail-wm1-x333.google.com with SMTP id 5b1f17b1804b1-412c780464dso7339215e9.0 for ; Fri, 01 Mar 2024 10:32:24 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id u2-20020adfeb42000000b0033b483d1abcsm5158934wrn.53.2024.03.01.10.32.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Mar 2024 10:32:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1709317943; x=1709922743; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9JEZmlz8rcZzNAyfALikSOUnOYbC8gIs8wauxLnIi0o=; b=Z5js9U12/Dkpl5Kpn6ukVxb8HgTdViDDB4vV6AWSCQmArVZ5lxZkqOBlLlljOwamlN MFMNtGH+g6Hvt+CBo8o8o8v7ih+Fdt2Dq+vLulSBB1JybVD48Jv3jdWXXIRDtOQDo8P/ xbVY1HMATvpcE3Ywqie1W/ejHAQDWxvcNeUl0bynEBgxb6IR35kESNW/Wv50aAklGwA5 5dvSeN+F4o5eftP14L27Eb7QkMsR1gntpTJe+50UwTFRY0kvz0z2vJAFzfv4J3iO8sIM Y+wvSDPvTTNPMFK2Ddnx9wupZ6PluEZijEuxIujUL/7nUn32XQ6Bl1++GvOEV6Uz3wCP pvKQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1709317943; x=1709922743; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9JEZmlz8rcZzNAyfALikSOUnOYbC8gIs8wauxLnIi0o=; b=klgYBfJWZzIXTuJ4EbEn+QDAnPas1IYYAitzgHpY0D0BVHD3182hai3yqRHNFLqG1V //pQhXcFuUxahEvGviAmfrPpJMDR5IdziNFxRwfuV6qlWI7oyGs/eqEKVijr9ySfZ3vO K5IByBrYh3TSJRKF2SNm3InD61oWlfAhAgWjznin3cnEI/qOxDhf0PUBaQmdS0kk480o nyM4/V4Pw0yhppA3VP7yX6igsb6o18oG1DXAXZjrMRsmteMeNx08noqnG3sfiyhdqTmc HDJRF3wwV0DqFNSP+m68mnr4Wpo2AEqS0OKZ9EhMPuPA2sph//Dw2W89GZCq/PVukl1W XURg== X-Forwarded-Encrypted: i=1; AJvYcCVZfHGHdfw6tWXsHGqzLPLTS104K03Us1lL4qa1u1dncCagR2N3tGXWk5D0UZAdnaVCdw4WIc0Tq6ob9cV9tGruAvWfEt4= X-Gm-Message-State: AOJu0Yw8OWPSDUp/61YGAYI3SnUwLJ2hJcUkZ0N4EDk6sWig8yMGYUu/ 04io+GIuq3SccbyH5T8Ow0RJszoWGjGyAbem2xSgf97E2d/RwEVcRtjPhwLJl0I= X-Google-Smtp-Source: AGHT+IFtdV07smIPQ+fubdtE0ivuotzxIquW43aG8eSvLGm92NLYPxlLv3U63nB+AiG5R55zIdnQlg== X-Received: by 2002:adf:a11e:0:b0:33d:b2fe:763c with SMTP id o30-20020adfa11e000000b0033db2fe763cmr1662534wro.33.1709317942908; Fri, 01 Mar 2024 10:32:22 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jean-Philippe Brucker Subject: [PATCH 4/8] target/arm: Don't allow RES0 CNTHCTL_EL2 bits to be written Date: Fri, 1 Mar 2024 18:32:15 +0000 Message-Id: <20240301183219.2424889-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240301183219.2424889-1-peter.maydell@linaro.org> References: <20240301183219.2424889-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1709318021634100003 Content-Type: text/plain; charset="utf-8" Don't allow the guest to write CNTHCTL_EL2 bits which don't exist. This is not strictly architecturally required, but it is how we've tended to implement registers more recently. In particular, bits [19:18] are only present with FEAT_RME, and bits [17:12] will only be present with FEAT_ECV. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index 1c82d12a883..8ec61c12440 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2968,6 +2968,24 @@ static void gt_cnthctl_write(CPUARMState *env, const= ARMCPRegInfo *ri, { ARMCPU *cpu =3D env_archcpu(env); uint32_t oldval =3D env->cp15.cnthctl_el2; + uint32_t valid_mask =3D + R_CNTHCTL_EL0PCTEN_MASK | + R_CNTHCTL_EL0VCTEN_MASK | + R_CNTHCTL_EVNTEN_MASK | + R_CNTHCTL_EVNTDIR_MASK | + R_CNTHCTL_EVNTI_MASK | + R_CNTHCTL_EL0VTEN_MASK | + R_CNTHCTL_EL0PTEN_MASK | + R_CNTHCTL_EL1PCTEN_MASK | + R_CNTHCTL_EL1PTEN_MASK; + + if (cpu_isar_feature(aa64_rme, cpu)) { + valid_mask |=3D R_CNTHCTL_CNTVMASK_MASK | R_CNTHCTL_CNTPMASK_MASK; + } + + /* Clear RES0 bits */ + value &=3D valid_mask; + raw_write(env, ri, value); =20 if ((oldval ^ value) & R_CNTHCTL_CNTVMASK_MASK) { --=20 2.34.1 From nobody Tue Nov 26 06:33:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1709318021; cv=none; d=zohomail.com; s=zohoarc; b=TJruFwPVNH1Os/uPqWJ3vwTJvQ88q9oiX0KEojt+ZbGrt9aHFxeQtEr+oUKEvaWHRrdAnyKfmzOqrw3+UtNJ+JJ+CsdqX3vNh6sWUHHXI87oIBwN8HciKr1DtkiSZs0kjYBQmIG4pFhI/FiFQaSAnPKO3zcH2w5r24g4uZcGi50= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1709318021; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=UNDEo4dAsr/AT3VVoZZKQQgUvPjllXjX2BLfBSLR17k=; b=KllOVLcCN9kUC8gGA+SaizOj+G8fxnSthbdqWqxIWOuF3jw8RRgavvX7hHgmip8xtFhc8PCtCqmRKSyeRKKkeCm46A/3LraZYSLdxpQ4Z5ubMOfQmxuPhXqaW4LZsFpdeb4znWVzRX0FOOK6Df1Y3fkBuFPlqSqWB3ZAz8rUcXw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1709318021537548.6878243904621; Fri, 1 Mar 2024 10:33:41 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rg7gS-0006Sw-5x; Fri, 01 Mar 2024 13:32:36 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rg7gM-0006Pm-2p for qemu-devel@nongnu.org; Fri, 01 Mar 2024 13:32:31 -0500 Received: from mail-lf1-x129.google.com ([2a00:1450:4864:20::129]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rg7gH-0008L1-4t for qemu-devel@nongnu.org; Fri, 01 Mar 2024 13:32:29 -0500 Received: by mail-lf1-x129.google.com with SMTP id 2adb3069b0e04-51323dfce59so2189137e87.3 for ; Fri, 01 Mar 2024 10:32:24 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id u2-20020adfeb42000000b0033b483d1abcsm5158934wrn.53.2024.03.01.10.32.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Mar 2024 10:32:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1709317943; x=1709922743; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UNDEo4dAsr/AT3VVoZZKQQgUvPjllXjX2BLfBSLR17k=; b=aXdzVT++PLr+PjxLQx3c1QKVP1/m1hmvhh4JPTQremNfKvBZVLg0pRY0riAZhG2AUM 6wnFlsmlsPb8seOSO5uvlELAey+XTWWfSFrn8DwG/9Z+5hKQ4NVN35ohZbwUmjcOWoSw LgeOXJ1rOkGmHimRD7v7SFntFyfPKZUkhonwUJ18HT5yMU6W12q7hPXFzs4UmdJIv6Z1 WFEALF/fiOC/OWq6YgGJzS9H04vRM4qS5/Bdtg/ML2SM0wYwa6MDP4ZTMUJccpMZNmd1 D1B0JdjoHm0bEBaiY07hXWRDGH6WKTmuILutwM9X3IVEFADl+5LBpVFIl2Wb6LwnoxC8 3VYw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1709317943; x=1709922743; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UNDEo4dAsr/AT3VVoZZKQQgUvPjllXjX2BLfBSLR17k=; b=AwV6Vsr42qiA/8CMyKXdcDexs30FK9AhBOhZLc7EnAszdtjI04u9xb/gEQ/LHJS67I AcDQkNjAZMBLyIHEopiswrIkr47cptj56gKzAPrf5uz+OgPmwZwIYEK/CYw2Z5rU1w57 jwwDAPO89czyRmuyv7h+RwUaAitd09Gyg2CLC71iq32XbdomkjazXoILHlp4q1v7qvX0 Dk9A2Pp3xYOEs0hS2onuv4rUuVsU2JlgwBiiQsrZd/9sF3DkRfLdBuGJF77B8U1zxiKA vzNUNgANWt/Z6VR++G3Wh9lcqVTzLeKFjNnfjZHsvxKfL2d7ZLxjYGKWiCZjb0pbDHOv MATQ== X-Forwarded-Encrypted: i=1; AJvYcCXMDY4xdQNxsN1sdGzgd/7acTZiWLJBNLTGMS7/+l0YjR92yOKxQq3tyDxsJNwbN7Zh4T6CEpkyJBCduVKdtlPGgNgDa9A= X-Gm-Message-State: AOJu0YzO5J5ebCAi+8rSTSBm0yT+yRQdadWp91TpwSg7RXva5Iiotl2A 0Lql2u7c5SkXnyw9O/srrojqS5wW2McrAeDmyrKBiHoZuPCIS2OExudT+jjzRaI= X-Google-Smtp-Source: AGHT+IGhu5yb6FSHuzKNlz1MdLMO+WnScCHuxsWgSuZ7kk8Cs1B/fV7uDE8/NA0aTqzNj++E/m4tnA== X-Received: by 2002:a05:6512:3a85:b0:513:360d:fe7b with SMTP id q5-20020a0565123a8500b00513360dfe7bmr1154114lfu.51.1709317943463; Fri, 01 Mar 2024 10:32:23 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jean-Philippe Brucker Subject: [PATCH 5/8] target/arm: Implement new FEAT_ECV trap bits Date: Fri, 1 Mar 2024 18:32:16 +0000 Message-Id: <20240301183219.2424889-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240301183219.2424889-1-peter.maydell@linaro.org> References: <20240301183219.2424889-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::129; envelope-from=peter.maydell@linaro.org; helo=mail-lf1-x129.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1709318023720100011 Content-Type: text/plain; charset="utf-8" The functionality defined by ID_AA64MMFR0_EL1.ECV =3D=3D 1 is: * four new trap bits for various counter and timer registers * the CNTHCTL_EL2.EVNTIS and CNTKCTL_EL1.EVNTIS bits which control scaling of the event stream. This is a no-op for us, because we don't implement the event stream (our WFE is a NOP): all we need to do is allow CNTHCTL_EL2.ENVTIS to be read and written. * extensions to PMSCR_EL1.PCT, PMSCR_EL2.PCT, TRFCR_EL1.TS and TRFCR_EL2.TS: these are all no-ops for us, because we don't implement FEAT_SPE or FEAT_TRF. * new registers CNTPCTSS_EL0 and NCTVCTSS_EL0 which are "self-sychronizing" views of the CNTPCT_EL0 and CNTVCT_EL0, meaning that no barriers are needed around their accesses. For us these are just the same as the normal views, because all our sysregs are inherently self-sychronizing. In this commit we implement the trap handling and permit the new CNTHCTL_EL2 bits to be written. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu-features.h | 5 ++++ target/arm/helper.c | 51 +++++++++++++++++++++++++++++++++++---- 2 files changed, 51 insertions(+), 5 deletions(-) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index 7567854db63..b447ec5c0e6 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -741,6 +741,11 @@ static inline bool isar_feature_aa64_fgt(const ARMISAR= egisters *id) return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, FGT) !=3D 0; } =20 +static inline bool isar_feature_aa64_ecv_traps(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, ECV) > 0; +} + static inline bool isar_feature_aa64_vh(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, VH) !=3D 0; diff --git a/target/arm/helper.c b/target/arm/helper.c index 8ec61c12440..6c528903a9a 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2530,6 +2530,11 @@ static CPAccessResult gt_counter_access(CPUARMState = *env, int timeridx, : !extract32(env->cp15.cnthctl_el2, 0, 1))) { return CP_ACCESS_TRAP_EL2; } + if (has_el2 && timeridx =3D=3D GTIMER_VIRT) { + if (FIELD_EX64(env->cp15.cnthctl_el2, CNTHCTL, EL1TVCT)) { + return CP_ACCESS_TRAP_EL2; + } + } break; } return CP_ACCESS_OK; @@ -2573,6 +2578,11 @@ static CPAccessResult gt_timer_access(CPUARMState *e= nv, int timeridx, } } } + if (has_el2 && timeridx =3D=3D GTIMER_VIRT) { + if (FIELD_EX64(env->cp15.cnthctl_el2, CNTHCTL, EL1TVT)) { + return CP_ACCESS_TRAP_EL2; + } + } break; } return CP_ACCESS_OK; @@ -2982,6 +2992,14 @@ static void gt_cnthctl_write(CPUARMState *env, const= ARMCPRegInfo *ri, if (cpu_isar_feature(aa64_rme, cpu)) { valid_mask |=3D R_CNTHCTL_CNTVMASK_MASK | R_CNTHCTL_CNTPMASK_MASK; } + if (cpu_isar_feature(aa64_ecv_traps, cpu)) { + valid_mask |=3D + R_CNTHCTL_EL1TVT_MASK | + R_CNTHCTL_EL1TVCT_MASK | + R_CNTHCTL_EL1NVPCT_MASK | + R_CNTHCTL_EL1NVVCT_MASK | + R_CNTHCTL_EVNTIS_MASK; + } =20 /* Clear RES0 bits */ value &=3D valid_mask; @@ -6564,7 +6582,6 @@ static CPAccessResult e2h_access(CPUARMState *env, co= nst ARMCPRegInfo *ri, { if (arm_current_el(env) =3D=3D 1) { /* This must be a FEAT_NV access */ - /* TODO: FEAT_ECV will need to check CNTHCTL_EL2 here */ return CP_ACCESS_OK; } if (!(arm_hcr_el2_eff(env) & HCR_E2H)) { @@ -6573,6 +6590,30 @@ static CPAccessResult e2h_access(CPUARMState *env, c= onst ARMCPRegInfo *ri, return CP_ACCESS_OK; } =20 +static CPAccessResult access_el1nvpct(CPUARMState *env, const ARMCPRegInfo= *ri, + bool isread) +{ + if (arm_current_el(env) =3D=3D 1) { + /* This must be a FEAT_NV access with NVx =3D=3D 101 */ + if (FIELD_EX64(env->cp15.cnthctl_el2, CNTHCTL, EL1NVPCT)) { + return CP_ACCESS_TRAP_EL2; + } + } + return e2h_access(env, ri, isread); +} + +static CPAccessResult access_el1nvvct(CPUARMState *env, const ARMCPRegInfo= *ri, + bool isread) +{ + if (arm_current_el(env) =3D=3D 1) { + /* This must be a FEAT_NV access with NVx =3D=3D 101 */ + if (FIELD_EX64(env->cp15.cnthctl_el2, CNTHCTL, EL1NVVCT)) { + return CP_ACCESS_TRAP_EL2; + } + } + return e2h_access(env, ri, isread); +} + /* Test if system register redirection is to occur in the current state. = */ static bool redirect_for_e2h(CPUARMState *env) { @@ -8398,14 +8439,14 @@ static const ARMCPRegInfo vhe_reginfo[] =3D { { .name =3D "CNTP_CTL_EL02", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 5, .crn =3D 14, .crm =3D 2, .opc2 =3D 1, .type =3D ARM_CP_IO | ARM_CP_ALIAS, - .access =3D PL2_RW, .accessfn =3D e2h_access, + .access =3D PL2_RW, .accessfn =3D access_el1nvpct, .nv2_redirect_offset =3D 0x180 | NV2_REDIR_NO_NV1, .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].c= tl), .writefn =3D gt_phys_ctl_write, .raw_writefn =3D raw_write }, { .name =3D "CNTV_CTL_EL02", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 5, .crn =3D 14, .crm =3D 3, .opc2 =3D 1, .type =3D ARM_CP_IO | ARM_CP_ALIAS, - .access =3D PL2_RW, .accessfn =3D e2h_access, + .access =3D PL2_RW, .accessfn =3D access_el1nvvct, .nv2_redirect_offset =3D 0x170 | NV2_REDIR_NO_NV1, .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].c= tl), .writefn =3D gt_virt_ctl_write, .raw_writefn =3D raw_write }, @@ -8424,14 +8465,14 @@ static const ARMCPRegInfo vhe_reginfo[] =3D { .type =3D ARM_CP_IO | ARM_CP_ALIAS, .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].c= val), .nv2_redirect_offset =3D 0x178 | NV2_REDIR_NO_NV1, - .access =3D PL2_RW, .accessfn =3D e2h_access, + .access =3D PL2_RW, .accessfn =3D access_el1nvpct, .writefn =3D gt_phys_cval_write, .raw_writefn =3D raw_write }, { .name =3D "CNTV_CVAL_EL02", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 5, .crn =3D 14, .crm =3D 3, .opc2 =3D 2, .type =3D ARM_CP_IO | ARM_CP_ALIAS, .nv2_redirect_offset =3D 0x168 | NV2_REDIR_NO_NV1, .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].c= val), - .access =3D PL2_RW, .accessfn =3D e2h_access, + .access =3D PL2_RW, .accessfn =3D access_el1nvvct, .writefn =3D gt_virt_cval_write, .raw_writefn =3D raw_write }, #endif }; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id u2-20020adfeb42000000b0033b483d1abcsm5158934wrn.53.2024.03.01.10.32.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Mar 2024 10:32:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1709317944; x=1709922744; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=8Rb0Z7zjLpv30F7lDtK7tZWHoJA0TmXTubgs4mA4pQs=; b=MDWAURfxkz8z3ktjdnS8WzraE7ZAIszwTYbmzISy8n8MOddPCu7nm5jeHXR1JZvHsW 3n42knSqliKeV4F77qRWUW9orQzMcS2Eag1rDOrf3xkr+EzJNIiSij8EB1NGqG8WxHTC Dx8ZG3xANL1VoKHujV+fl8ZIT9z5Fg8hQhZd8d7oSHyp9avHsIc8jDaVJTOp5WzlESs9 PCfJSwod2PQo5NocnA60FWhWFTbFXKQgMMzukmK4q3afIGpjH5GAB4bCzmPL4Td/esXm n1sTQTexbXwJLKQdc5TTEOK8PoeDV7Trtt+lNgSl+dC+vDM9av6xbUCF7WmtiQVYRVMd RRUQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1709317944; x=1709922744; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8Rb0Z7zjLpv30F7lDtK7tZWHoJA0TmXTubgs4mA4pQs=; b=BjkPL9dR7ppo6LGwYBweNUZlWtPj8qbZsGBbLPiWV6uEn7ompPkVXWkwCpyz7Va7zx BuoDH5WENprvdfNjDsbgVPTnIEGto7UZRYDB7EjePUnLBJ53FVk0o060hzN6UiDuR3aT wjk2zFjL7SPhrxUp7jE4+D6Q+4UM3OYdT8th1Gk/Mosde109IBrQjVaZNrMCCSTy51xL 8KlHuDzVSUK57FroUaF4xndGyPjnjIfzBtPkYy2VNLCYVmDrjp4aqsvkQu4XaEwjYLDw H+kjB8nsNnrKrN2xHWn6DRFj8F09LCBgzyhsKskpF+KdFVV4lp6P+MxkXfmSXm0Atfvg 6o7Q== X-Forwarded-Encrypted: i=1; AJvYcCUYA1Nu9T2tLv9cfU3euWTBunhenygtSxiCj3Jv8RiIlj1rsDZEA0RIG5WLr0LSAqYsaEc/+9nXsEKsV9212szR5heTzR8= X-Gm-Message-State: AOJu0YyBVLEW/iyCiW6eC79uP1o5/AWM+mtfri/CDLcLEyW3Bx0WpGU+ 5Ee0RI2HjBgQPSJ7vnUTjZbmmJegOsR1pJnAhohjKYDUHnM1d+xjVIKiuvWIzDE= X-Google-Smtp-Source: AGHT+IGfEB9m/9/1BS3zGkUXOndMR4YofG/scuEAWoSoKR9sudNP8Cx4Lem6J186k2KgwBT7SpAoGw== X-Received: by 2002:adf:9ccd:0:b0:33e:1f94:c493 with SMTP id h13-20020adf9ccd000000b0033e1f94c493mr2214804wre.65.1709317943986; Fri, 01 Mar 2024 10:32:23 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jean-Philippe Brucker Subject: [PATCH 6/8] target/arm: Define CNTPCTSS_EL0 and CNTVCTSS_EL0 Date: Fri, 1 Mar 2024 18:32:17 +0000 Message-Id: <20240301183219.2424889-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240301183219.2424889-1-peter.maydell@linaro.org> References: <20240301183219.2424889-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1709318057777100001 Content-Type: text/plain; charset="utf-8" For FEAT_ECV, new registers CNTPCTSS_EL0 and CNTVCTSS_EL0 are defined, which are "self-synchronized" views of the physical and virtual counts as seen in the CNTPCT_EL0 and CNTVCT_EL0 registers (meaning that no barriers are needed around accesses to them to ensure that reads of them do not occur speculatively and out-of-order with other instructions). For QEMU, all our system registers are self-synchronized, so we can simply copy the existing implementation of CNTPCT_EL0 and CNTVCT_EL0 to the new register encodings. This means we now implement all the functionality required for ID_AA64MMFR0_EL1.ECV =3D=3D 0b0001. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper.c | 43 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index 6c528903a9a..3441b14ba39 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3389,6 +3389,34 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[]= =3D { }, }; =20 +/* + * FEAT_ECV adds extra views of CNTVCT_EL0 and CNTPCT_EL0 which + * are "self-synchronizing". For QEMU all sysregs are self-synchronizing, + * so our implementations here are identical to the normal registers. + */ +static const ARMCPRegInfo gen_timer_ecv_cp_reginfo[] =3D { + { .name =3D "CNTVCTSS", .cp =3D 15, .crm =3D 14, .opc1 =3D 9, + .access =3D PL0_R, .type =3D ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_I= O, + .accessfn =3D gt_vct_access, + .readfn =3D gt_virt_cnt_read, .resetfn =3D arm_cp_reset_ignore, + }, + { .name =3D "CNTVCTSS_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 0, .opc2 =3D 6, + .access =3D PL0_R, .type =3D ARM_CP_NO_RAW | ARM_CP_IO, + .accessfn =3D gt_vct_access, .readfn =3D gt_virt_cnt_read, + }, + { .name =3D "CNTPCTSS", .cp =3D 15, .crm =3D 14, .opc1 =3D 8, + .access =3D PL0_R, .type =3D ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_I= O, + .accessfn =3D gt_pct_access, + .readfn =3D gt_cnt_read, .resetfn =3D arm_cp_reset_ignore, + }, + { .name =3D "CNTPCTSS_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 0, .opc2 =3D 5, + .access =3D PL0_R, .type =3D ARM_CP_NO_RAW | ARM_CP_IO, + .accessfn =3D gt_pct_access, .readfn =3D gt_cnt_read, + }, +}; + #else =20 /* @@ -3422,6 +3450,18 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[]= =3D { }, }; =20 +/* + * CNTVCTSS_EL0 has the same trap conditions as CNTVCT_EL0, so it also + * is exposed to userspace by Linux. + */ +static const ARMCPRegInfo gen_timer_ecv_cp_reginfo[] =3D { + { .name =3D "CNTVCTSS_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 0, .opc2 =3D 6, + .access =3D PL0_R, .type =3D ARM_CP_NO_RAW | ARM_CP_IO, + .readfn =3D gt_virt_cnt_read, + }, +}; + #endif =20 static void par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t v= alue) @@ -9258,6 +9298,9 @@ void register_cp_regs_for_features(ARMCPU *cpu) if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { define_arm_cp_regs(cpu, generic_timer_cp_reginfo); } + if (cpu_isar_feature(aa64_ecv_traps, cpu)) { + define_arm_cp_regs(cpu, gen_timer_ecv_cp_reginfo); + } if (arm_feature(env, ARM_FEATURE_VAPA)) { ARMCPRegInfo vapa_cp_reginfo[] =3D { { .name =3D "PAR", .cp =3D 15, .crn =3D 7, .crm =3D 4, .opc1 = =3D 0, .opc2 =3D 0, --=20 2.34.1 From nobody Tue Nov 26 06:33:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1709318052; cv=none; d=zohomail.com; s=zohoarc; b=ihV9Ssw4/6beNWTnU3MROtz252NpoJFaR9yrHDsWylGBIQ3BDYzBv9bzqbgFW1zq4M6T1ieFe3tR76RYduHEQlQYPJBlBYSeOkd81D/BA4Lanq2zuFuF05YgO7UW2bshFJi9gIOMGqsoRTwYO8+Y3TZ8y95oMuSYo1r9q5HVc44= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1709318052; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=hVVKscQ5vCUHxCMh3/cOUoLf8I/F9iPoQ7drxX5MzdQ=; b=mkGfiOabdLYm3h60Ef1Aixc8HpsgUo2NtGdI5hnYYcEaoeo6lptptzoYHNaGGY3c5K8/Oegm7NWXyXQTGNMqidyqznE0Sc1+kfHaTAXF0ifLeIZWj3CdX5QGZLkntqrFUYXhKaGUTdbpjgC1C3EIDiCWESdFX+syCKi3ttujv8o= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1709318052094281.8519079100223; Fri, 1 Mar 2024 10:34:12 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rg7gT-0006U2-Lt; Fri, 01 Mar 2024 13:32:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rg7gN-0006RU-W5 for qemu-devel@nongnu.org; Fri, 01 Mar 2024 13:32:33 -0500 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rg7gJ-0008LP-HU for qemu-devel@nongnu.org; Fri, 01 Mar 2024 13:32:31 -0500 Received: by mail-wm1-x335.google.com with SMTP id 5b1f17b1804b1-412ce4f62f8so2106845e9.0 for ; Fri, 01 Mar 2024 10:32:26 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id u2-20020adfeb42000000b0033b483d1abcsm5158934wrn.53.2024.03.01.10.32.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Mar 2024 10:32:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1709317944; x=1709922744; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=hVVKscQ5vCUHxCMh3/cOUoLf8I/F9iPoQ7drxX5MzdQ=; b=nS0ChmGQ2DyuJQm9Mtnr8QGv2Es55jFanHbLy/j55jlXev1aqwRsMCkWao+qAEiYUn KOdj6QZdhTXfZ9Fgp4TjTAsXVEudSLB1nn7wu2P4egdyI4nMkwOeHVntjiJ8VWbP1pDD tKlEvWKsi+csxGfTTSCeeEAyUwSQivNVyFUDwvAga0w5AWUXDAPhZchDWIJwI7r9wY/D Mzpan9jtYLS7svAKwPeO+o/BbS515RSsRxcD82eTNPPxXWnJlES1B5Z0eDsjYLWTwzVd 5oS9qkjXR0pw6cF+/dpcQiXyGUtSvzojwrx6Dk5cu1A5j3W308fv1MSy1V2/U7hqhN4l 8MgQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1709317944; x=1709922744; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hVVKscQ5vCUHxCMh3/cOUoLf8I/F9iPoQ7drxX5MzdQ=; b=AqTKmpKAAH9iOGdAmlTI0MzSuVJupix5Pm/HG74/VRwYF0FOaWG0rgWt9aaczW/xkk k6wURrNBIKACPbzTCnsEzJ/s46nRJ4xVBMFcbJjCbgv0/qLKzXx4cpqrfS0DkByNntl3 IOy/IJwxaIBktUU2oGQxFRGKyZ94vFcJNoTIiZWH63rSWonPg/WlzERXtZMhomR/OyGk eJzQSx2YyqPjA5TBMtw5UlaJLJtY+iTdQCLuHHOK8OflY/E+32wq69mIqkzC0DnNEIkG OUExLyCMrwPL6FFTxUG+L0uUaIjahMBcgdZERdWhNT2Vc4gKQ91x//SZ0hFwx3dsFBS4 klkw== X-Forwarded-Encrypted: i=1; AJvYcCV5mcvoUYZK7EbkRAtwo1q4mrWuQETD9MyKqVQjuj06/5eI+uJY2G19XwmoMVhfaRv545A2Ttd+3MQ2S3Qc34UK307vOOc= X-Gm-Message-State: AOJu0YyBFjB4Ifk0KUHQq239ghBjVNaWU3bv75gGFXz1Cw54IQnpWOp9 cCt8dt2kAfevi2jfy2lufSgM1kZ35GoSTUr7kkeVEo0d8TFW+8Dt7Y0Xw4oHEVs= X-Google-Smtp-Source: AGHT+IF1Cob9zTiI5DEDo58tyNws/gB/cba8T1mphYQVnAs4hpEGzT6r2iKHDg/iRk5TF1annX4Rcg== X-Received: by 2002:adf:9ccb:0:b0:33c:deed:6745 with SMTP id h11-20020adf9ccb000000b0033cdeed6745mr2146626wre.13.1709317944481; Fri, 01 Mar 2024 10:32:24 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jean-Philippe Brucker Subject: [PATCH 7/8] target/arm: Implement FEAT_ECV CNTPOFF_EL2 handling Date: Fri, 1 Mar 2024 18:32:18 +0000 Message-Id: <20240301183219.2424889-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240301183219.2424889-1-peter.maydell@linaro.org> References: <20240301183219.2424889-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1709318053798100001 Content-Type: text/plain; charset="utf-8" When ID_AA64MMFR0_EL1.ECV is 0b0010, a new register CNTPOFF_EL2 is implemented. This is similar to the existing CNTVOFF_EL2, except that it controls a hypervisor-adjustable offset made to the physical counter and timer. Implement the handling for this register, which includes control/trap bits in SCR_EL3 and CNTHCTL_EL2. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu-features.h | 5 +++ target/arm/cpu.h | 1 + target/arm/helper.c | 68 +++++++++++++++++++++++++++++++++++++-- target/arm/trace-events | 1 + 4 files changed, 73 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index b447ec5c0e6..e5758d9fbc8 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -746,6 +746,11 @@ static inline bool isar_feature_aa64_ecv_traps(const A= RMISARegisters *id) return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, ECV) > 0; } =20 +static inline bool isar_feature_aa64_ecv(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, ECV) > 1; +} + static inline bool isar_feature_aa64_vh(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, VH) !=3D 0; diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 3cbfd4f9a74..262ebbf1c19 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -453,6 +453,7 @@ typedef struct CPUArchState { uint64_t c14_cntkctl; /* Timer Control register */ uint64_t cnthctl_el2; /* Counter/Timer Hyp Control register */ uint64_t cntvoff_el2; /* Counter Virtual Offset register */ + uint64_t cntpoff_el2; /* Counter Physical Offset register */ ARMGenericTimer c14_timer[NUM_GTIMERS]; uint32_t c15_cpar; /* XScale Coprocessor Access Register */ uint32_t c15_ticonfig; /* TI925T configuration byte. */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 3441b14ba39..f590bdf0f7e 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1923,6 +1923,9 @@ static void scr_write(CPUARMState *env, const ARMCPRe= gInfo *ri, uint64_t value) if (cpu_isar_feature(aa64_rme, cpu)) { valid_mask |=3D SCR_NSE | SCR_GPF; } + if (cpu_isar_feature(aa64_ecv, cpu)) { + valid_mask |=3D SCR_ECVEN; + } } else { valid_mask &=3D ~(SCR_RW | SCR_ST); if (cpu_isar_feature(aa32_ras, cpu)) { @@ -2682,6 +2685,25 @@ void gt_rme_post_el_change(ARMCPU *cpu, void *ignore= d) gt_update_irq(cpu, GTIMER_PHYS); } =20 +static uint64_t gt_phys_raw_cnt_offset(CPUARMState *env) +{ + if ((env->cp15.scr_el3 & SCR_ECVEN) && + FIELD_EX64(env->cp15.cnthctl_el2, CNTHCTL, ECV) && + arm_is_el2_enabled(env) && + (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) !=3D (HCR_E2H | HCR_T= GE)) { + return env->cp15.cntpoff_el2; + } + return 0; +} + +static uint64_t gt_phys_cnt_offset(CPUARMState *env) +{ + if (arm_current_el(env) >=3D 2) { + return 0; + } + return gt_phys_raw_cnt_offset(env); +} + static void gt_recalc_timer(ARMCPU *cpu, int timeridx) { ARMGenericTimer *gt =3D &cpu->env.cp15.c14_timer[timeridx]; @@ -2692,7 +2714,7 @@ static void gt_recalc_timer(ARMCPU *cpu, int timeridx) * reset timer to when ISTATUS next has to change */ uint64_t offset =3D timeridx =3D=3D GTIMER_VIRT ? - cpu->env.cp15.cntvoff_el2 : 0; + cpu->env.cp15.cntvoff_el2 : gt_phys_raw_cnt_offset(&cpu->env); uint64_t count =3D gt_get_countervalue(&cpu->env); /* Note that this must be unsigned 64 bit arithmetic: */ int istatus =3D count - offset >=3D gt->cval; @@ -2755,7 +2777,7 @@ static void gt_timer_reset(CPUARMState *env, const AR= MCPRegInfo *ri, =20 static uint64_t gt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri) { - return gt_get_countervalue(env); + return gt_get_countervalue(env) - gt_phys_cnt_offset(env); } =20 static uint64_t gt_virt_cnt_offset(CPUARMState *env) @@ -2804,6 +2826,9 @@ static uint64_t gt_tval_read(CPUARMState *env, const = ARMCPRegInfo *ri, case GTIMER_HYPVIRT: offset =3D gt_virt_cnt_offset(env); break; + case GTIMER_PHYS: + offset =3D gt_phys_cnt_offset(env); + break; } =20 return (uint32_t)(env->cp15.c14_timer[timeridx].cval - @@ -2821,6 +2846,9 @@ static void gt_tval_write(CPUARMState *env, const ARM= CPRegInfo *ri, case GTIMER_HYPVIRT: offset =3D gt_virt_cnt_offset(env); break; + case GTIMER_PHYS: + offset =3D gt_phys_cnt_offset(env); + break; } =20 trace_arm_gt_tval_write(timeridx, value); @@ -3000,6 +3028,9 @@ static void gt_cnthctl_write(CPUARMState *env, const = ARMCPRegInfo *ri, R_CNTHCTL_EL1NVVCT_MASK | R_CNTHCTL_EVNTIS_MASK; } + if (cpu_isar_feature(aa64_ecv, cpu)) { + valid_mask |=3D R_CNTHCTL_ECV_MASK; + } =20 /* Clear RES0 bits */ value &=3D valid_mask; @@ -3417,6 +3448,34 @@ static const ARMCPRegInfo gen_timer_ecv_cp_reginfo[]= =3D { }, }; =20 +static CPAccessResult gt_cntpoff_access(CPUARMState *env, + const ARMCPRegInfo *ri, + bool isread) +{ + if (arm_current_el(env) =3D=3D 2 && !(env->cp15.scr_el3 & SCR_ECVEN)) { + return CP_ACCESS_TRAP_EL3; + } + return CP_ACCESS_OK; +} + +static void gt_cntpoff_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + ARMCPU *cpu =3D env_archcpu(env); + + trace_arm_gt_cntpoff_write(value); + raw_write(env, ri, value); + gt_recalc_timer(cpu, GTIMER_PHYS); +} + +static const ARMCPRegInfo gen_timer_cntpoff_reginfo =3D { + .name =3D "CNTPOFF_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 14, .crm =3D 0, .opc2 =3D 6, + .access =3D PL2_RW, .type =3D ARM_CP_IO, .resetvalue =3D 0, + .accessfn =3D gt_cntpoff_access, .writefn =3D gt_cntpoff_write, + .nv2_redirect_offset =3D 0x1a8, + .fieldoffset =3D offsetof(CPUARMState, cp15.cntpoff_el2), +}; #else =20 /* @@ -9301,6 +9360,11 @@ void register_cp_regs_for_features(ARMCPU *cpu) if (cpu_isar_feature(aa64_ecv_traps, cpu)) { define_arm_cp_regs(cpu, gen_timer_ecv_cp_reginfo); } +#ifndef CONFIG_USER_ONLY + if (cpu_isar_feature(aa64_ecv, cpu)) { + define_one_arm_cp_reg(cpu, &gen_timer_cntpoff_reginfo); + } +#endif if (arm_feature(env, ARM_FEATURE_VAPA)) { ARMCPRegInfo vapa_cp_reginfo[] =3D { { .name =3D "PAR", .cp =3D 15, .crn =3D 7, .crm =3D 4, .opc1 = =3D 0, .opc2 =3D 0, diff --git a/target/arm/trace-events b/target/arm/trace-events index 48cc0512dbe..4438dce7bec 100644 --- a/target/arm/trace-events +++ b/target/arm/trace-events @@ -8,6 +8,7 @@ arm_gt_tval_write(int timer, uint64_t value) "gt_tval_write= : timer %d value 0x%" arm_gt_ctl_write(int timer, uint64_t value) "gt_ctl_write: timer %d value = 0x%" PRIx64 arm_gt_imask_toggle(int timer) "gt_ctl_write: timer %d IMASK toggle" arm_gt_cntvoff_write(uint64_t value) "gt_cntvoff_write: value 0x%" PRIx64 +arm_gt_cntpoff_write(uint64_t value) "gt_cntpoff_write: value 0x%" PRIx64 arm_gt_update_irq(int timer, int irqstate) "gt_update_irq: timer %d irqsta= te %d" =20 # kvm.c --=20 2.34.1 From nobody Tue Nov 26 06:33:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id u2-20020adfeb42000000b0033b483d1abcsm5158934wrn.53.2024.03.01.10.32.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Mar 2024 10:32:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1709317945; x=1709922745; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=p+dys/cioNoZhTZtInFG+2Of2YnqX5s/i4q/n08XiVo=; b=d7bfaO/DwNC7mpCcQBZFHIioi6hZ4fuHU68ZIioIddceV5UNwRCcjUNjGSivrYO5Ss 9VAr33G5Vi2/379arO4gW6q1AFHpmRWAK1hAMSONhxQ2tNMHOWvQqGv5lP9zvqYW3E+0 q2tPJLFyl5mhvZuzyp+cM0WDJgCxqvCwUjnmu8WnnQLvHhxkesKIzGDJH/gSoI3j7IK1 6pDDG/4mIxDOtv7dFqskZl6RYVTBT0o7cH6x5eZG1rfg2B4ovcKZz4KpHUG5yH5V3DMM HUeyq9/oVl9WRP1WpPwt20F9oKT/R+AMir7ldFogE2esXsIYPb01nEKX4nJIj9YXByxn yqBw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1709317945; x=1709922745; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=p+dys/cioNoZhTZtInFG+2Of2YnqX5s/i4q/n08XiVo=; b=sGYjSpklQViSgyYPp2Zc8O2wYCNl3LsCINMOpwqhtMjmCezJhfOQbhvM13sx7qOqIN 53iaHCS49nvRp8kBDHjVCg1If4oPpfWc1BgAP6ubb5coc6WWDy2GCBWp9rX0cXYPq/Y/ Ph35dLpYkCijQ1XG86tAJBw+Bsy0lXwo42Fdw25QxUOq/A7bkA6XaJCsVjXsA3OS4/Tt LSuqmZmfaUbP+VgB6sd0zutc8jvZulT1tZHqj5p/AgW7Zf9Dh8Zmq6GMgH/uIgae2TFq 2tyMXzzn3poHMktsKQaH400VgfbXFD8/TzOatR4L1x0adAsxO4AOCt14w7HRkTrzWk/d 3WYQ== X-Forwarded-Encrypted: i=1; AJvYcCUl3/TdE+YWCP01BArBfJLL5ZPoVrvlBcRchTV8gMz7Fp71RiQfccztu3FHTBlfSPqMwR7WrFVZc65iTHVqMyKK+NJStN8= X-Gm-Message-State: AOJu0YxHoreWiL4OeNptPW7qcFTyf3LrRY06lBlxAnSiLLnXL8bIH/yE eSmcSGbgk1g4TTXtaMn/KfXK0pacK2XACtbQORpi26dTdfypPKrrJ3zD+T82X8c= X-Google-Smtp-Source: AGHT+IEgUHu/xZbIv13m1FIFX3u5GcnIRWoOOKgSZR7SlQUgv46qsabqOHMfvFw6p8ory+BS3X4asA== X-Received: by 2002:ac2:5e24:0:b0:513:2010:6d93 with SMTP id o4-20020ac25e24000000b0051320106d93mr1762866lfg.56.1709317944962; Fri, 01 Mar 2024 10:32:24 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jean-Philippe Brucker Subject: [PATCH 8/8] target/arm: Enable FEAT_ECV for 'max' CPU Date: Fri, 1 Mar 2024 18:32:19 +0000 Message-Id: <20240301183219.2424889-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240301183219.2424889-1-peter.maydell@linaro.org> References: <20240301183219.2424889-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::12b; envelope-from=peter.maydell@linaro.org; helo=mail-lf1-x12b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1709318021653100004 Content-Type: text/plain; charset="utf-8" Enable all FEAT_ECV features on the 'max' CPU. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- docs/system/arm/emulation.rst | 1 + target/arm/tcg/cpu64.c | 1 + 2 files changed, 2 insertions(+) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index f67aea2d836..2a7bbb82dc4 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -28,6 +28,7 @@ the following architecture extensions: - FEAT_DotProd (Advanced SIMD dot product instructions) - FEAT_DoubleFault (Double Fault Extension) - FEAT_E0PD (Preventing EL0 access to halves of address maps) +- FEAT_ECV (Enhanced Counter Virtualization) - FEAT_EPAC (Enhanced pointer authentication) - FEAT_ETS (Enhanced Translation Synchronization) - FEAT_EVT (Enhanced Virtualization Traps) diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 5fba2c0f040..9f7a9f3d2cc 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -1184,6 +1184,7 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64MMFR0, TGRAN64_2, 2); /* 64k stage2 support= ed */ t =3D FIELD_DP64(t, ID_AA64MMFR0, TGRAN4_2, 2); /* 4k stage2 support= ed */ t =3D FIELD_DP64(t, ID_AA64MMFR0, FGT, 1); /* FEAT_FGT */ + t =3D FIELD_DP64(t, ID_AA64MMFR0, ECV, 2); /* FEAT_ECV */ cpu->isar.id_aa64mmfr0 =3D t; =20 t =3D cpu->isar.id_aa64mmfr1; --=20 2.34.1