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Wed, 28 Feb 2024 10:51:54 -0800 (PST) From: Atish Patra To: Cc: Daniel Henrique Barboza , Atish Patra , Alistair Francis , Bin Meng , Liu Zhiwei , Palmer Dabbelt , qemu-devel@nongnu.org, qemu-riscv@nongnu.org, Weiwei Li , kaiwenxue1@gmail.com Subject: [PATCH v5 5/5] target/riscv: Implement privilege mode filtering for cycle/instret Date: Wed, 28 Feb 2024 10:51:16 -0800 Message-Id: <20240228185116.1321730-6-atishp@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240228185116.1321730-1-atishp@rivosinc.com> References: <20240228185116.1321730-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=atishp@rivosinc.com; helo=mail-pf1-x429.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1709146361337100007 Content-Type: text/plain; charset="utf-8" Privilege mode filtering can also be emulated for cycle/instret by tracking host_ticks/icount during each privilege mode switch. This patch implements that for both cycle/instret and mhpmcounters. The first one requires Smcntrpmf while the other one requires Sscofpmf to be enabled. The cycle/instret are still computed using host ticks when icount is not enabled. Otherwise, they are computed using raw icount which is more accurate in icount mode. Reviewed-by: Daniel Henrique Barboza Signed-off-by: Atish Patra --- target/riscv/cpu.h | 11 +++++ target/riscv/cpu_bits.h | 5 ++ target/riscv/cpu_helper.c | 17 ++++++- target/riscv/csr.c | 96 ++++++++++++++++++++++++++++++--------- target/riscv/pmu.c | 64 ++++++++++++++++++++++++++ target/riscv/pmu.h | 2 + 6 files changed, 171 insertions(+), 24 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 174e8ba8e847..9e21d7f7d635 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -157,6 +157,15 @@ typedef struct PMUCTRState { target_ulong irq_overflow_left; } PMUCTRState; =20 +typedef struct PMUFixedCtrState { + /* Track cycle and icount for each privilege mode */ + uint64_t counter[4]; + uint64_t counter_prev[4]; + /* Track cycle and icount for each privilege mode when V =3D 1*/ + uint64_t counter_virt[2]; + uint64_t counter_virt_prev[2]; +} PMUFixedCtrState; + struct CPUArchState { target_ulong gpr[32]; target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */ @@ -353,6 +362,8 @@ struct CPUArchState { /* PMU event selector configured values for RV32 */ target_ulong mhpmeventh_val[RV_MAX_MHPMEVENTS]; =20 + PMUFixedCtrState pmu_fixed_ctrs[2]; + target_ulong sscratch; target_ulong mscratch; =20 diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index e866c60a400c..5fe349e313dc 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -920,6 +920,11 @@ typedef enum RISCVException { #define MHPMEVENT_BIT_VUINH BIT_ULL(58) #define MHPMEVENTH_BIT_VUINH BIT(26) =20 +#define MHPMEVENT_FILTER_MASK (MHPMEVENT_BIT_MINH | \ + MHPMEVENT_BIT_SINH | \ + MHPMEVENT_BIT_UINH | \ + MHPMEVENT_BIT_VSINH | \ + MHPMEVENT_BIT_VUINH) #define MHPMEVENT_SSCOF_MASK _ULL(0xFFFF000000000000) #define MHPMEVENT_IDX_MASK 0xFFFFF #define MHPMEVENT_SSCOF_RESVD 16 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index d462d95ee165..33965d843d46 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -718,8 +718,21 @@ void riscv_cpu_set_mode(CPURISCVState *env, target_ulo= ng newpriv) { g_assert(newpriv <=3D PRV_M && newpriv !=3D PRV_RESERVED); =20 - if (icount_enabled() && newpriv !=3D env->priv) { - riscv_itrigger_update_priv(env); + /* + * Invoke cycle/instret update between priv mode changes or + * VS->HS mode transition is SPV bit must be set + * HS->VS mode transition where virt_enabled must be set + * In both cases, priv will S mode only. + */ + if (newpriv !=3D env->priv || + (env->priv =3D=3D PRV_S && newpriv =3D=3D PRV_S && + (env->virt_enabled || get_field(env->hstatus, HSTATUS_SPV)))) { + if (icount_enabled()) { + riscv_itrigger_update_priv(env); + riscv_pmu_icount_update_priv(env, newpriv); + } else { + riscv_pmu_cycle_update_priv(env, newpriv); + } } /* tlb_flush is unnecessary as mode is contained in mmu_idx */ env->priv =3D newpriv; diff --git a/target/riscv/csr.c b/target/riscv/csr.c index ff9bac537593..482e212c5f74 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -788,32 +788,16 @@ static RISCVException write_vcsr(CPURISCVState *env, = int csrno, return RISCV_EXCP_NONE; } =20 +#if defined(CONFIG_USER_ONLY) /* User Timers and Counters */ static target_ulong get_ticks(bool shift) { - int64_t val; - target_ulong result; - -#if !defined(CONFIG_USER_ONLY) - if (icount_enabled()) { - val =3D icount_get(); - } else { - val =3D cpu_get_host_ticks(); - } -#else - val =3D cpu_get_host_ticks(); -#endif - - if (shift) { - result =3D val >> 32; - } else { - result =3D val; - } + int64_t val =3D cpu_get_host_ticks(); + target_ulong result =3D shift ? val >> 32 : val; =20 return result; } =20 -#if defined(CONFIG_USER_ONLY) static RISCVException read_time(CPURISCVState *env, int csrno, target_ulong *val) { @@ -952,6 +936,71 @@ static RISCVException write_mhpmeventh(CPURISCVState *= env, int csrno, return RISCV_EXCP_NONE; } =20 +static target_ulong riscv_pmu_ctr_get_fixed_counters_val(CPURISCVState *en= v, + int counter_idx, + bool upper_half) +{ + uint64_t curr_val =3D 0; + target_ulong result =3D 0; + uint64_t *counter_arr =3D icount_enabled() ? env->pmu_fixed_ctrs[1].co= unter : + env->pmu_fixed_ctrs[0].counter; + uint64_t *counter_arr_virt =3D icount_enabled() ? + env->pmu_fixed_ctrs[1].counter_virt : + env->pmu_fixed_ctrs[0].counter_virt; + uint64_t cfg_val =3D 0; + + if (counter_idx =3D=3D 0) { + cfg_val =3D upper_half ? ((uint64_t)env->mcyclecfgh << 32) : + env->mcyclecfg; + } else if (counter_idx =3D=3D 2) { + cfg_val =3D upper_half ? ((uint64_t)env->minstretcfgh << 32) : + env->minstretcfg; + } else { + cfg_val =3D upper_half ? + ((uint64_t)env->mhpmeventh_val[counter_idx] << 32) : + env->mhpmevent_val[counter_idx]; + cfg_val &=3D MHPMEVENT_FILTER_MASK; + } + + if (!cfg_val) { + if (icount_enabled()) { + curr_val =3D icount_get_raw(); + } else { + curr_val =3D cpu_get_host_ticks(); + } + goto done; + } + + if (!(cfg_val & MCYCLECFG_BIT_MINH)) { + curr_val +=3D counter_arr[PRV_M]; + } + + if (!(cfg_val & MCYCLECFG_BIT_SINH)) { + curr_val +=3D counter_arr[PRV_S]; + } + + if (!(cfg_val & MCYCLECFG_BIT_UINH)) { + curr_val +=3D counter_arr[PRV_U]; + } + + if (!(cfg_val & MCYCLECFG_BIT_VSINH)) { + curr_val +=3D counter_arr_virt[PRV_S]; + } + + if (!(cfg_val & MCYCLECFG_BIT_VUINH)) { + curr_val +=3D counter_arr_virt[PRV_U]; + } + +done: + if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { + result =3D upper_half ? curr_val >> 32 : curr_val; + } else { + result =3D curr_val; + } + + return result; +} + static RISCVException write_mhpmcounter(CPURISCVState *env, int csrno, target_ulong val) { @@ -962,7 +1011,8 @@ static RISCVException write_mhpmcounter(CPURISCVState = *env, int csrno, counter->mhpmcounter_val =3D val; if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) || riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) { - counter->mhpmcounter_prev =3D get_ticks(false); + counter->mhpmcounter_prev =3D riscv_pmu_ctr_get_fixed_counters_val= (env, + ctr_idx, f= alse); if (ctr_idx > 2) { if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { mhpmctr_val =3D mhpmctr_val | @@ -990,7 +1040,8 @@ static RISCVException write_mhpmcounterh(CPURISCVState= *env, int csrno, mhpmctr_val =3D mhpmctr_val | (mhpmctrh_val << 32); if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) || riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) { - counter->mhpmcounterh_prev =3D get_ticks(true); + counter->mhpmcounterh_prev =3D riscv_pmu_ctr_get_fixed_counters_va= l(env, + ctr_idx, = true); if (ctr_idx > 2) { riscv_pmu_setup_timer(env, mhpmctr_val, ctr_idx); } @@ -1031,7 +1082,8 @@ static RISCVException riscv_pmu_read_ctr(CPURISCVStat= e *env, target_ulong *val, */ if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) || riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) { - *val =3D get_ticks(upper_half) - ctr_prev + ctr_val; + *val =3D riscv_pmu_ctr_get_fixed_counters_val(env, ctr_idx, upper_= half) - + ctr_prev + ctr_val; } else { *val =3D ctr_val; } diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c index 0e7d58b8a5c2..37309ff64cb6 100644 --- a/target/riscv/pmu.c +++ b/target/riscv/pmu.c @@ -19,6 +19,7 @@ #include "qemu/osdep.h" #include "qemu/log.h" #include "qemu/error-report.h" +#include "qemu/timer.h" #include "cpu.h" #include "pmu.h" #include "sysemu/cpu-timers.h" @@ -176,6 +177,69 @@ static int riscv_pmu_incr_ctr_rv64(RISCVCPU *cpu, uint= 32_t ctr_idx) return 0; } =20 +void riscv_pmu_icount_update_priv(CPURISCVState *env, target_ulong newpriv) +{ + uint64_t delta; + uint64_t *counter_arr; + uint64_t *counter_arr_prev; + uint64_t current_icount =3D icount_get_raw(); + + if (env->virt_enabled) { + counter_arr =3D env->pmu_fixed_ctrs[1].counter_virt; + counter_arr_prev =3D env->pmu_fixed_ctrs[1].counter_virt_prev; + } else { + counter_arr =3D env->pmu_fixed_ctrs[1].counter; + counter_arr_prev =3D env->pmu_fixed_ctrs[1].counter_prev; + } + + if (newpriv !=3D env->priv) { + delta =3D current_icount - counter_arr_prev[env->priv]; + counter_arr_prev[newpriv] =3D current_icount; + } else { + delta =3D current_icount - counter_arr_prev[env->priv]; + if (env->virt_enabled) { + /* HS->VS transition.The previous value should correspond to H= S. */ + env->pmu_fixed_ctrs[1].counter_prev[PRV_S] =3D current_icount; + } else if (get_field(env->hstatus, HSTATUS_SPV)) { + /* VS->HS transition.The previous value should correspond to V= S. */ + env->pmu_fixed_ctrs[1].counter_virt_prev[PRV_S] =3D current_ic= ount; + } + } + + counter_arr[env->priv] +=3D delta; +} + +void riscv_pmu_cycle_update_priv(CPURISCVState *env, target_ulong newpriv) +{ + uint64_t delta; + uint64_t *counter_arr; + uint64_t *counter_arr_prev; + uint64_t current_host_ticks =3D cpu_get_host_ticks(); + + if (env->virt_enabled) { + counter_arr =3D env->pmu_fixed_ctrs[0].counter_virt; + counter_arr_prev =3D env->pmu_fixed_ctrs[0].counter_virt_prev; + } else { + counter_arr =3D env->pmu_fixed_ctrs[0].counter; + counter_arr_prev =3D env->pmu_fixed_ctrs[0].counter_prev; + } + + if (newpriv !=3D env->priv) { + delta =3D current_host_ticks - counter_arr_prev[env->priv]; + counter_arr_prev[newpriv] =3D current_host_ticks; + } else { + delta =3D current_host_ticks - counter_arr_prev[env->priv]; + if (env->virt_enabled) { + env->pmu_fixed_ctrs[0].counter_prev[PRV_S] =3D current_host_ti= cks; + } else if (get_field(env->hstatus, HSTATUS_SPV)) { + env->pmu_fixed_ctrs[0].counter_virt_prev[PRV_S] =3D + current_host_ticks; + } + } + + counter_arr[env->priv] +=3D delta; +} + int riscv_pmu_incr_ctr(RISCVCPU *cpu, enum riscv_pmu_event_idx event_idx) { uint32_t ctr_idx; diff --git a/target/riscv/pmu.h b/target/riscv/pmu.h index 505fc850d38e..50de6031a730 100644 --- a/target/riscv/pmu.h +++ b/target/riscv/pmu.h @@ -31,3 +31,5 @@ int riscv_pmu_incr_ctr(RISCVCPU *cpu, enum riscv_pmu_even= t_idx event_idx); void riscv_pmu_generate_fdt_node(void *fdt, uint32_t cmask, char *pmu_name= ); int riscv_pmu_setup_timer(CPURISCVState *env, uint64_t value, uint32_t ctr_idx); +void riscv_pmu_icount_update_priv(CPURISCVState *env, target_ulong newpriv= ); +void riscv_pmu_cycle_update_priv(CPURISCVState *env, target_ulong newpriv); --=20 2.34.1