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Wed, 28 Feb 2024 03:57:10 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: Akihiko Odaki , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , qemu-riscv@nongnu.org (open list:RISC-V TCG CPUs) Subject: [PULL 07/29] target/riscv: Use GDBFeature for dynamic XML Date: Wed, 28 Feb 2024 11:56:39 +0000 Message-Id: <20240228115701.1416107-8-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240228115701.1416107-1-alex.bennee@linaro.org> References: <20240228115701.1416107-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1709121588010100003 From: Akihiko Odaki In preparation for a change to use GDBFeature as a parameter of gdb_register_coprocessor(), convert the internal representation of dynamic feature from plain XML to GDBFeature. Signed-off-by: Akihiko Odaki Message-Id: <20231213-gdb-v17-3-777047380591@daynix.com> Signed-off-by: Alex Benn=C3=A9e Message-Id: <20240227144335.1196131-8-alex.bennee@linaro.org> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index f52dce78baa..5d291a70925 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -24,6 +24,7 @@ #include "hw/registerfields.h" #include "hw/qdev-properties.h" #include "exec/cpu-defs.h" +#include "exec/gdbstub.h" #include "qemu/cpu-float.h" #include "qom/object.h" #include "qemu/int128.h" @@ -445,8 +446,8 @@ struct ArchCPU { =20 CPURISCVState env; =20 - char *dyn_csr_xml; - char *dyn_vreg_xml; + GDBFeature dyn_csr_feature; + GDBFeature dyn_vreg_feature; =20 /* Configuration Settings */ RISCVCPUConfig cfg; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1b8d001d237..1b62e269b90 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -2305,9 +2305,9 @@ static const char *riscv_gdb_get_dynamic_xml(CPUState= *cs, const char *xmlname) RISCVCPU *cpu =3D RISCV_CPU(cs); =20 if (strcmp(xmlname, "riscv-csr.xml") =3D=3D 0) { - return cpu->dyn_csr_xml; + return cpu->dyn_csr_feature.xml; } else if (strcmp(xmlname, "riscv-vector.xml") =3D=3D 0) { - return cpu->dyn_vreg_xml; + return cpu->dyn_vreg_feature.xml; } =20 return NULL; diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index ca9b71f7bbc..d8da84fa52e 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -214,14 +214,15 @@ static int riscv_gdb_set_virtual(CPURISCVState *cs, u= int8_t *mem_buf, int n) return 0; } =20 -static int riscv_gen_dynamic_csr_xml(CPUState *cs, int base_reg) +static GDBFeature *riscv_gen_dynamic_csr_feature(CPUState *cs, int base_re= g) { RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(cs); RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; - GString *s =3D g_string_new(NULL); + GDBFeatureBuilder builder; riscv_csr_predicate_fn predicate; int bitsize =3D riscv_cpu_max_xlen(mcc); + const char *name; int i; =20 #if !defined(CONFIG_USER_ONLY) @@ -233,9 +234,9 @@ static int riscv_gen_dynamic_csr_xml(CPUState *cs, int = base_reg) bitsize =3D 64; } =20 - g_string_printf(s, ""); - g_string_append_printf(s, ""); - g_string_append_printf(s, ""= ); + gdb_feature_builder_init(&builder, &cpu->dyn_csr_feature, + "org.gnu.gdb.riscv.csr", "riscv-csr.xml", + base_reg); =20 for (i =3D 0; i < CSR_TABLE_SIZE; i++) { if (env->priv_ver < csr_ops[i].min_priv_ver) { @@ -243,72 +244,64 @@ static int riscv_gen_dynamic_csr_xml(CPUState *cs, in= t base_reg) } predicate =3D csr_ops[i].predicate; if (predicate && (predicate(env, i) =3D=3D RISCV_EXCP_NONE)) { - if (csr_ops[i].name) { - g_string_append_printf(s, "", base_reg + i); + + gdb_feature_builder_append_reg(&builder, name, bitsize, i, + "int", NULL); } } =20 - g_string_append_printf(s, ""); - - cpu->dyn_csr_xml =3D g_string_free(s, false); + gdb_feature_builder_end(&builder); =20 #if !defined(CONFIG_USER_ONLY) env->debugger =3D false; #endif =20 - return CSR_TABLE_SIZE; + return &cpu->dyn_csr_feature; } =20 -static int ricsv_gen_dynamic_vector_xml(CPUState *cs, int base_reg) +static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base= _reg) { RISCVCPU *cpu =3D RISCV_CPU(cs); - GString *s =3D g_string_new(NULL); - g_autoptr(GString) ts =3D g_string_new(""); - int reg_width =3D cpu->cfg.vlenb << 3; - int num_regs =3D 0; + int reg_width =3D cpu->cfg.vlenb; + GDBFeatureBuilder builder; int i; =20 - g_string_printf(s, ""); - g_string_append_printf(s, "= "); - g_string_append_printf(s, ""); + gdb_feature_builder_init(&builder, &cpu->dyn_vreg_feature, + "org.gnu.gdb.riscv.vector", "riscv-vector.xml= ", + base_reg); =20 /* First define types and totals in a whole VL */ for (i =3D 0; i < ARRAY_SIZE(vec_lanes); i++) { int count =3D reg_width / vec_lanes[i].size; - g_string_printf(ts, "%s", vec_lanes[i].id); - g_string_append_printf(s, - "", - ts->str, vec_lanes[i].gdb_type, count); + gdb_feature_builder_append_tag( + &builder, "", + vec_lanes[i].id, vec_lanes[i].gdb_type, count); } =20 /* Define unions */ - g_string_append_printf(s, ""); + gdb_feature_builder_append_tag(&builder, ""); for (i =3D 0; i < ARRAY_SIZE(vec_lanes); i++) { - g_string_append_printf(s, "", - vec_lanes[i].suffix, - vec_lanes[i].id); + gdb_feature_builder_append_tag(&builder, + "", + vec_lanes[i].suffix, vec_lanes[i].i= d); } - g_string_append(s, ""); + gdb_feature_builder_append_tag(&builder, ""); =20 /* Define vector registers */ for (i =3D 0; i < 32; i++) { - g_string_append_printf(s, - "", - i, reg_width, base_reg++); - num_regs++; + gdb_feature_builder_append_reg(&builder, g_strdup_printf("v%d", i), + reg_width, i, "riscv_vector", "vect= or"); } =20 - g_string_append_printf(s, ""); + gdb_feature_builder_end(&builder); =20 - cpu->dyn_vreg_xml =3D g_string_free(s, false); - return num_regs; + return &cpu->dyn_vreg_feature; } =20 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs) @@ -324,10 +317,9 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState= *cs) 32, "riscv-32bit-fpu.xml", 0); } if (env->misa_ext & RVV) { - int base_reg =3D cs->gdb_num_regs; gdb_register_coprocessor(cs, riscv_gdb_get_vector, riscv_gdb_set_vector, - ricsv_gen_dynamic_vector_xml(cs, base_reg= ), + ricsv_gen_dynamic_vector_feature(cs, cs->= gdb_num_regs)->num_regs, "riscv-vector.xml", 0); } switch (mcc->misa_mxl_max) { @@ -347,9 +339,8 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState = *cs) } =20 if (cpu->cfg.ext_zicsr) { - int base_reg =3D cs->gdb_num_regs; gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr, - riscv_gen_dynamic_csr_xml(cs, base_reg), + riscv_gen_dynamic_csr_feature(cs, cs->gdb= _num_regs)->num_regs, "riscv-csr.xml", 0); } } --=20 2.39.2