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Wed, 28 Feb 2024 03:11:56 -0800 (PST) X-Google-Smtp-Source: AGHT+IGd6l3IV++Garq8LNTghNvXUWGaaYs3683iYhinNRSy6U/kgbKGUANq0V+iXD9qpPe6gJ0HWQ== X-Received: by 2002:a17:906:7b50:b0:a43:ef3d:e42e with SMTP id n16-20020a1709067b5000b00a43ef3de42emr1070660ejo.18.1709118715685; Wed, 28 Feb 2024 03:11:55 -0800 (PST) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org Subject: [PATCH 1/4] target/i386: use TSTEQ/TSTNE to test low bits Date: Wed, 28 Feb 2024 12:11:48 +0100 Message-ID: <20240228111151.287738-2-pbonzini@redhat.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240228111151.287738-1-pbonzini@redhat.com> References: <20240228111151.287738-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.088, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1709118821058100003 Content-Type: text/plain; charset="utf-8" When testing the sign bit or equality to zero of a partial register, it is useful to use a single TSTEQ or TSTNE operation. It can also be used to test the parity flag, using bit 0 of the population count. Do not do this for 32- and 64-bit values however, to avoid large immediates. Signed-off-by: Paolo Bonzini Reviewed-by: Richard Henderson --- target/i386/tcg/translate.c | 28 ++++++++++++++++++++-------- target/i386/tcg/emit.c.inc | 5 ++--- 2 files changed, 22 insertions(+), 11 deletions(-) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 07f642dc9e9..fe9021833e3 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -927,11 +927,21 @@ typedef struct CCPrepare { bool no_setcond; } CCPrepare; =20 +static CCPrepare gen_prepare_sign_nz(TCGv src, MemOp size) +{ + if (size =3D=3D MO_TL) { + return (CCPrepare) { .cond =3D TCG_COND_LT, .reg =3D src, .mask = =3D -1 }; + } else { + return (CCPrepare) { .cond =3D TCG_COND_TSTNE, .reg =3D src, .mask= =3D -1, + .imm =3D 1ull << ((8 << size) - 1) }; + } +} + /* compute eflags.C to reg */ static CCPrepare gen_prepare_eflags_c(DisasContext *s, TCGv reg) { TCGv t0, t1; - int size, shift; + MemOp size; =20 switch (s->cc_op) { case CC_OP_SUBB ... CC_OP_SUBQ: @@ -966,9 +976,7 @@ static CCPrepare gen_prepare_eflags_c(DisasContext *s, = TCGv reg) case CC_OP_SHLB ... CC_OP_SHLQ: /* (CC_SRC >> (DATA_BITS - 1)) & 1 */ size =3D s->cc_op - CC_OP_SHLB; - shift =3D (8 << size) - 1; - return (CCPrepare) { .cond =3D TCG_COND_NE, .reg =3D cpu_cc_src, - .mask =3D (target_ulong)1 << shift }; + return gen_prepare_sign_nz(cpu_cc_src, size); =20 case CC_OP_MULB ... CC_OP_MULQ: return (CCPrepare) { .cond =3D TCG_COND_NE, @@ -1028,8 +1036,7 @@ static CCPrepare gen_prepare_eflags_s(DisasContext *s= , TCGv reg) default: { MemOp size =3D (s->cc_op - CC_OP_ADDB) & 3; - TCGv t0 =3D gen_ext_tl(reg, cpu_cc_dst, size, true); - return (CCPrepare) { .cond =3D TCG_COND_LT, .reg =3D t0, .mask= =3D -1 }; + return gen_prepare_sign_nz(cpu_cc_dst, size); } } } @@ -1076,8 +1083,13 @@ static CCPrepare gen_prepare_eflags_z(DisasContext *= s, TCGv reg) default: { MemOp size =3D (s->cc_op - CC_OP_ADDB) & 3; - TCGv t0 =3D gen_ext_tl(reg, cpu_cc_dst, size, false); - return (CCPrepare) { .cond =3D TCG_COND_EQ, .reg =3D t0, .mask= =3D -1 }; + if (size =3D=3D MO_TL) { + return (CCPrepare) { .cond =3D TCG_COND_EQ, .reg =3D cpu_c= c_dst, + .mask =3D -1 }; + } else { + return (CCPrepare) { .cond =3D TCG_COND_TSTEQ, .reg =3D cp= u_cc_dst, + .mask =3D -1, .imm =3D (1ull << (8 <<= size)) - 1 }; + } } } } diff --git a/target/i386/tcg/emit.c.inc b/target/i386/tcg/emit.c.inc index 6bcf88ecd71..0e00f6635dd 100644 --- a/target/i386/tcg/emit.c.inc +++ b/target/i386/tcg/emit.c.inc @@ -1209,7 +1209,7 @@ static void gen_CMPccXADD(DisasContext *s, CPUX86Stat= e *env, X86DecodedInsn *dec [JCC_Z] =3D TCG_COND_EQ, [JCC_BE] =3D TCG_COND_LEU, [JCC_S] =3D TCG_COND_LT, /* test sign bit by comparing against 0 = */ - [JCC_P] =3D TCG_COND_EQ, /* even parity - tests low bit of popcou= nt */ + [JCC_P] =3D TCG_COND_TSTEQ, /* even parity - tests low bit of pop= count */ [JCC_L] =3D TCG_COND_LT, [JCC_LE] =3D TCG_COND_LE, }; @@ -1260,8 +1260,7 @@ static void gen_CMPccXADD(DisasContext *s, CPUX86Stat= e *env, X86DecodedInsn *dec case JCC_P: tcg_gen_ext8u_tl(s->tmp0, s->T0); tcg_gen_ctpop_tl(s->tmp0, s->tmp0); - tcg_gen_andi_tl(s->tmp0, s->tmp0, 1); - cmp_lhs =3D s->tmp0, cmp_rhs =3D tcg_constant_tl(0); + cmp_lhs =3D s->tmp0, cmp_rhs =3D tcg_constant_tl(1); break; =20 case JCC_S: --=20 2.43.2