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Wed, 28 Feb 2024 03:06:28 -0800 (PST) X-Google-Smtp-Source: AGHT+IEpBWxXpzP8EEJCHrLUIRTgRRnQlyjxGy8yr6eghDCHdIjd8Cxj7liIrqkv2tuu0mYXKoQIVQ== X-Received: by 2002:a17:906:ad5:b0:a44:da2:11b6 with SMTP id z21-20020a1709060ad500b00a440da211b6mr601608ejf.67.1709118388451; Wed, 28 Feb 2024 03:06:28 -0800 (PST) From: Paolo Bonzini To: qemu-devel@nongnu.org Subject: [PATCH] tcg/optimize: lower some ANDs to two shifts Date: Wed, 28 Feb 2024 12:06:26 +0100 Message-ID: <20240228110626.287178-1-pbonzini@redhat.com> X-Mailer: git-send-email 2.43.2 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.088, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1709118441993100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: Paolo Bonzini --- tcg/optimize.c | 60 +++++++++++++++++++++++++++++++++++++++++++------- 1 file changed, 52 insertions(+), 8 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index 3995bc047db..8ea1f287788 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -1281,6 +1281,43 @@ static bool fold_add2(OptContext *ctx, TCGOp *op) return fold_addsub2(ctx, op, true); } =20 +static bool fold_and_to_shifts(OptContext *ctx, uint64_t c, TCGOp *op) +{ + TCGOpcode shl_opc =3D tcg->type =3D=3D TCG_TYPE_I32 ? INDEX_op_shl_i32= : INDEX_op_shl_i64; + TCGOpcode shr_opc =3D tcg->type =3D=3D TCG_TYPE_I32 ? INDEX_op_shr_i32= : INDEX_op_shr_i64; + + TCGOpcode first, second; + int count; + TCGOp *op2; + + unsigned_c =3D tcg->type =3D=3D TCG_TYPE_I32 ? (uint32_t) c : c; + if (is_power_of_2(-c) && + !tcg_op_imm_match(op->opc, c)) { + /* AND with 11...11000, shift right then left. */ + count =3D ctz64(c); + first =3D shr_opc; + } else if (is_power_of_2(c + 1) && + !tcg_op_imm_match(INDEX_op_and_i64, c)) { + /* AND with 00...00111, shift left then right. */ + int bits =3D tcg->type =3D=3D TCG_TYPE_I32 ? 32 : 64; + count =3D bits - cto64(c); + first =3D shl_opc; + } else { + return false; + } + + + op->opc =3D first; + op->args[2] =3D arg_new_constant(ctx, count); + + second =3D shl_opc ^ shr_opc ^ first; + op2 =3D tcg_op_insert_after(ctx->tcg, op, second, 3); + op2->args[0] =3D op->args[0]; + op2->args[1] =3D op->args[0]; + op2->args[2] =3D arg_new_constant(ctx, count); + return true; +} + static bool fold_and(OptContext *ctx, TCGOp *op) { uint64_t z1, z2; @@ -1294,6 +1331,18 @@ static bool fold_and(OptContext *ctx, TCGOp *op) =20 z1 =3D arg_info(op->args[1])->z_mask; z2 =3D arg_info(op->args[2])->z_mask; + + /* + * Known-zeros does not imply known-ones. Therefore unless + * arg2 is constant, we can't infer affected bits from it. + */ + if (arg_is_const(op->args[2])) { + if (fold_and_to_shifts(ctx, z2, op)) { + return true; + } + ctx->a_mask =3D z1 & ~z2; + } + ctx->z_mask =3D z1 & z2; =20 /* @@ -1303,14 +1352,6 @@ static bool fold_and(OptContext *ctx, TCGOp *op) ctx->s_mask =3D arg_info(op->args[1])->s_mask & arg_info(op->args[2])->s_mask; =20 - /* - * Known-zeros does not imply known-ones. Therefore unless - * arg2 is constant, we can't infer affected bits from it. - */ - if (arg_is_const(op->args[2])) { - ctx->a_mask =3D z1 & ~z2; - } - return fold_masks(ctx, op); } =20 @@ -1333,6 +1374,9 @@ static bool fold_andc(OptContext *ctx, TCGOp *op) */ if (arg_is_const(op->args[2])) { uint64_t z2 =3D ~arg_info(op->args[2])->z_mask; + if (fold_and_to_shifts(ctx, z2, op)) { + return true; + } ctx->a_mask =3D z1 & ~z2; z1 &=3D z2; } --=20 2.43.2