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Wed, 28 Feb 2024 00:07:12 -0800 (PST) X-Google-Smtp-Source: AGHT+IFtNxyecOQn8+QzP+khnduSvVcUXo8KLTi58N0a+Vuyd9EhjCEbYWQr4OdOMY/4U8rKUyR54Q== X-Received: by 2002:a05:6402:713:b0:566:348:fc4a with SMTP id w19-20020a056402071300b005660348fc4amr5072160edx.32.1709107632447; Wed, 28 Feb 2024 00:07:12 -0800 (PST) From: Paolo Bonzini To: qemu-devel@nongnu.org Subject: [PULL 05/10] target/i386: use separate MMU indexes for 32-bit accesses Date: Wed, 28 Feb 2024 09:06:41 +0100 Message-ID: <20240228080646.261365-6-pbonzini@redhat.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240228080646.261365-1-pbonzini@redhat.com> References: <20240228080646.261365-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.088, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1709107724603100001 Content-Type: text/plain; charset="utf-8" Accesses from a 32-bit environment (32-bit code segment for instruction accesses, EFER.LMA=3D=3D0 for processor accesses) have to mask away the upper 32 bits of the address. While a bit wasteful, the easiest way to do so is to use separate MMU indexes. These days, QEMU anyway is compiled with a fixed value for NB_MMU_MODES. Split MMU_USER_IDX, MMU_KSMAP_IDX and MMU_KNOSMAP_IDX in two. Signed-off-by: Paolo Bonzini --- target/i386/cpu.h | 34 ++++++++++++++++++++-------- target/i386/cpu.c | 11 +++++---- target/i386/tcg/sysemu/excp_helper.c | 3 ++- 3 files changed, 33 insertions(+), 15 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 8c271ca62e5..ee4ad372021 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2299,27 +2299,41 @@ uint64_t cpu_get_tsc(CPUX86State *env); #define cpu_list x86_cpu_list =20 /* MMU modes definitions */ -#define MMU_KSMAP_IDX 0 -#define MMU_USER_IDX 1 -#define MMU_KNOSMAP_IDX 2 -#define MMU_NESTED_IDX 3 -#define MMU_PHYS_IDX 4 +#define MMU_KSMAP64_IDX 0 +#define MMU_KSMAP32_IDX 1 +#define MMU_USER64_IDX 2 +#define MMU_USER32_IDX 3 +#define MMU_KNOSMAP64_IDX 4 +#define MMU_KNOSMAP32_IDX 5 +#define MMU_PHYS_IDX 6 +#define MMU_NESTED_IDX 7 + +#ifdef CONFIG_USER_ONLY +#ifdef TARGET_X86_64 +#define MMU_USER_IDX MMU_USER64_IDX +#else +#define MMU_USER_IDX MMU_USER32_IDX +#endif +#endif =20 static inline bool is_mmu_index_smap(int mmu_index) { - return mmu_index =3D=3D MMU_KSMAP_IDX; + return (mmu_index & ~1) =3D=3D MMU_KSMAP64_IDX; } =20 static inline bool is_mmu_index_user(int mmu_index) { - return mmu_index =3D=3D MMU_USER_IDX; + return (mmu_index & ~1) =3D=3D MMU_USER64_IDX; } =20 static inline int cpu_mmu_index_kernel(CPUX86State *env) { - return !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP_IDX : - ((env->hflags & HF_CPL_MASK) < 3 && (env->eflags & AC_MASK)) - ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX; + int mmu_index_32 =3D (env->hflags & HF_LMA_MASK) ? 1 : 0; + int mmu_index_base =3D + !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP64_IDX : + ((env->hflags & HF_CPL_MASK) < 3 && (env->eflags & AC_MASK)) ? MMU= _KNOSMAP64_IDX : MMU_KSMAP64_IDX; + + return mmu_index_base + mmu_index_32; } =20 #define CC_DST (env->cc_dst) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 7f908236767..647371198c7 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7732,13 +7732,16 @@ static bool x86_cpu_has_work(CPUState *cs) return x86_cpu_pending_interrupt(cs, cs->interrupt_request) !=3D 0; } =20 -static int x86_cpu_mmu_index(CPUState *cs, bool ifetch) +static int x86_cpu_mmu_index(CPUState *env, bool ifetch) { CPUX86State *env =3D cpu_env(cs); + int mmu_index_32 =3D (env->hflags & HF_CS64_MASK) ? 1 : 0; + int mmu_index_base =3D + (env->hflags & HF_CPL_MASK) =3D=3D 3 ? MMU_USER64_IDX : + !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP64_IDX : + (env->eflags & AC_MASK) ? MMU_KNOSMAP64_IDX : MMU_KSMAP64_IDX; =20 - return (env->hflags & HF_CPL_MASK) =3D=3D 3 ? MMU_USER_IDX : - (!(env->hflags & HF_SMAP_MASK) || (env->eflags & AC_MASK)) - ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX; + return mmu_index_base + mmu_index_32; } =20 static void x86_disas_set_info(CPUState *cs, disassemble_info *info) diff --git a/target/i386/tcg/sysemu/excp_helper.c b/target/i386/tcg/sysemu/= excp_helper.c index a0d5ce39300..b2c525e1a92 100644 --- a/target/i386/tcg/sysemu/excp_helper.c +++ b/target/i386/tcg/sysemu/excp_helper.c @@ -545,7 +545,8 @@ static bool get_physical_address(CPUX86State *env, vadd= r addr, if (likely(use_stage2)) { in.cr3 =3D env->nested_cr3; in.pg_mode =3D env->nested_pg_mode; - in.mmu_idx =3D MMU_USER_IDX; + in.mmu_idx =3D + env->nested_pg_mode & PG_MODE_LMA ? MMU_USER64_IDX : MMU_U= SER32_IDX; in.ptw_idx =3D MMU_PHYS_IDX; =20 if (!mmu_translate(env, &in, out, err)) { --=20 2.43.2