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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::54a; envelope-from=3FGHeZQcKCoUtxvuxmrpxxpun.lxvznv3-mn4nuwxwpw3.x0p@flex--komlodi.bounces.google.com; helo=mail-pg1-x54a.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01, USER_IN_DEF_DKIM_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @google.com) X-ZM-MESSAGEID: 1709072755719100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" I've seen a few different instances where a CPU or a memory region is behind some sort of IOMMU, and the IOMMU translates (or denies) accesses based on the requester ID of the CPU. This patch only does it on ARM CPUs, because I did not see CPU-agnostic code that added CPU attributes when creating TLBs. Similarly, we add the requester ID during PTW, while populating the rest of the memory attributes. We add the requester ID during GPC and descriptor grabbing as well as PTWs. Signed-off-by: Joe Komlodi --- target/arm/cpu.c | 4 ++++ target/arm/cpu.h | 6 ++++++ target/arm/ptw.c | 5 +++++ 3 files changed, 15 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 5fa86bc8d5..9cfbba10c2 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2402,6 +2402,9 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) } } =20 + /* For MemTxAttrs. */ + env->requester_id =3D cpu->requester_id; + qemu_init_vcpu(cs); cpu_reset(cs); =20 @@ -2439,6 +2442,7 @@ static Property arm_cpu_properties[] =3D { mp_affinity, ARM64_AFFINITY_INVALID), DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID), DEFINE_PROP_INT32("core-count", ARMCPU, core_count, -1), + DEFINE_PROP_UINT16("requester-id", ARMCPU, requester_id, 0), DEFINE_PROP_END_OF_LIST() }; =20 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 63f31e0d98..5fc572e077 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -774,6 +774,9 @@ typedef struct CPUArchState { /* Linux syscall tagged address support */ bool tagged_addr_enable; #endif + + /* For MemTxAttrs. */ + uint16_t requester_id; } CPUARMState; =20 static inline void set_feature(CPUARMState *env, int feature) @@ -1091,6 +1094,9 @@ struct ArchCPU { =20 /* Generic timer counter frequency, in Hz */ uint64_t gt_cntfrq_hz; + + /* Requester ID, used in MemTxAttrs. */ + uint16_t requester_id; }; =20 typedef struct ARMCPUInfo { diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 5eb3577bcd..148af3a000 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -287,6 +287,7 @@ static bool granule_protection_check(CPUARMState *env, = uint64_t paddress, MemTxAttrs attrs =3D { .secure =3D true, .space =3D ARMSS_Root, + .requester_id =3D env->requester_id, }; ARMCPU *cpu =3D env_archcpu(env); uint64_t gpccr =3D env->cp15.gpccr_el3; @@ -638,6 +639,7 @@ static uint32_t arm_ldl_ptw(CPUARMState *env, S1Transla= te *ptw, MemTxAttrs attrs =3D { .space =3D ptw->out_space, .secure =3D arm_space_is_secure(ptw->out_space), + .requester_id =3D env->requester_id, }; AddressSpace *as =3D arm_addressspace(cs, attrs); MemTxResult result =3D MEMTX_OK; @@ -684,6 +686,7 @@ static uint64_t arm_ldq_ptw(CPUARMState *env, S1Transla= te *ptw, MemTxAttrs attrs =3D { .space =3D ptw->out_space, .secure =3D arm_space_is_secure(ptw->out_space), + .requester_id =3D env->requester_id, }; AddressSpace *as =3D arm_addressspace(cs, attrs); MemTxResult result =3D MEMTX_OK; @@ -3306,6 +3309,8 @@ static bool get_phys_addr_nogpc(CPUARMState *env, S1T= ranslate *ptw, result->f.attrs.space =3D ptw->in_space; result->f.attrs.secure =3D arm_space_is_secure(ptw->in_space); =20 + result->f.attrs.requester_id =3D env->requester_id; + switch (mmu_idx) { case ARMMMUIdx_Phys_S: case ARMMMUIdx_Phys_NS: --=20 2.44.0.rc0.258.g7320e95886-goog From nobody Tue Nov 26 06:34:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=google.com ARC-Seal: i=1; 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Tue, 27 Feb 2024 14:24:22 -0800 (PST) Date: Tue, 27 Feb 2024 22:24:14 +0000 In-Reply-To: <20240227222417.929367-1-komlodi@google.com> Mime-Version: 1.0 References: <20240227222417.929367-1-komlodi@google.com> X-Mailer: git-send-email 2.44.0.rc1.240.g4c46232300-goog Message-ID: <20240227222417.929367-3-komlodi@google.com> Subject: [RFC PATCH 2/5] memattrs: Fix target_tlb_bit whitespace From: Joe Komlodi To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com, peterx@redhat.com, david@redhat.com, peter.maydell@linaro.org, marcel.apfelbaum@gmail.com, mst@redhat.com, philmd@linaro.org, roqueh@google.com, slongfield@google.com, komlodi@google.com Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::54a; envelope-from=3FmHeZQcKCocvzxwzotrzzrwp.nzx1px5-op6pwyzyry5.z2r@flex--komlodi.bounces.google.com; helo=mail-pg1-x54a.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01, USER_IN_DEF_DKIM_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @google.com) X-ZM-MESSAGEID: 1709072733734100003 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" checkpatch.pl doesn't like these spaces around the colon, so we may as well fix it up. No functional change. Signed-off-by: Joe Komlodi --- include/exec/memattrs.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h index d04170aa27..942b721be8 100644 --- a/include/exec/memattrs.h +++ b/include/exec/memattrs.h @@ -61,9 +61,9 @@ typedef struct MemTxAttrs { * and has unused bits. These fields will be read by target-specific * helpers using env->iotlb[mmu_idx][tlb_index()].attrs.target_tlb_bit= N. */ - unsigned int target_tlb_bit0 : 1; - unsigned int target_tlb_bit1 : 1; - unsigned int target_tlb_bit2 : 1; + unsigned int target_tlb_bit0:1; + unsigned int target_tlb_bit1:1; + unsigned int target_tlb_bit2:1; } MemTxAttrs; =20 /* Bus masters which don't specify any attributes will get this, --=20 2.44.0.rc0.258.g7320e95886-goog From nobody Tue Nov 26 06:34:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=google.com ARC-Seal: i=1; a=rsa-sha256; t=1709072758; cv=none; d=zohomail.com; s=zohoarc; b=VoZlE0BG6J+1rY5DPvZTUUI7f9xRJ2CpvF1gtbOl2Kb48fQwEY9I2H9gWudGiALSmiRSQeXl9DopEv0CHEX/RyuqfpUVXEOfh7Y9bib7mOQbOG0axFjjEJRlHVHmw59T8yWWns1m4/W4ePuTJ7MjnSvVHMU7POab7qn0GVlUCnY= ARC-Message-Signature: i=1; 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Tue, 27 Feb 2024 14:24:24 -0800 (PST) Date: Tue, 27 Feb 2024 22:24:15 +0000 In-Reply-To: <20240227222417.929367-1-komlodi@google.com> Mime-Version: 1.0 References: <20240227222417.929367-1-komlodi@google.com> X-Mailer: git-send-email 2.44.0.rc1.240.g4c46232300-goog Message-ID: <20240227222417.929367-4-komlodi@google.com> Subject: [RFC PATCH 3/5] memattrs: Add user-defined attribute From: Joe Komlodi To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com, peterx@redhat.com, david@redhat.com, peter.maydell@linaro.org, marcel.apfelbaum@gmail.com, mst@redhat.com, philmd@linaro.org, roqueh@google.com, slongfield@google.com, komlodi@google.com Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::b49; envelope-from=3GGHeZQcKCokx1zy1qvt11tyr.p1z3rz7-qr8ry010t07.14t@flex--komlodi.bounces.google.com; helo=mail-yb1-xb49.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01, USER_IN_DEF_DKIM_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @google.com) X-ZM-MESSAGEID: 1709072759714100009 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" These are used to represent implementation-specific data. These are based off of AMBA-AXI user signals, but can be used in any implementation. The length of 4-bits is arbitrary. Signed-off-by: Joe Komlodi --- include/exec/memattrs.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h index 942b721be8..a38645f881 100644 --- a/include/exec/memattrs.h +++ b/include/exec/memattrs.h @@ -64,6 +64,8 @@ typedef struct MemTxAttrs { unsigned int target_tlb_bit0:1; unsigned int target_tlb_bit1:1; unsigned int target_tlb_bit2:1; + /* User-defined bits represent data that is implementation defined. */ + unsigned int user_defined:4; } MemTxAttrs; =20 /* Bus masters which don't specify any attributes will get this, --=20 2.44.0.rc0.258.g7320e95886-goog From nobody Tue Nov 26 06:34:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=google.com ARC-Seal: i=1; a=rsa-sha256; t=1709072733; cv=none; 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Tue, 27 Feb 2024 14:24:26 -0800 (PST) Date: Tue, 27 Feb 2024 22:24:16 +0000 In-Reply-To: <20240227222417.929367-1-komlodi@google.com> Mime-Version: 1.0 References: <20240227222417.929367-1-komlodi@google.com> X-Mailer: git-send-email 2.44.0.rc1.240.g4c46232300-goog Message-ID: <20240227222417.929367-5-komlodi@google.com> Subject: [RFC PATCH 4/5] target/arm: Add user-defined memattrs From: Joe Komlodi To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com, peterx@redhat.com, david@redhat.com, peter.maydell@linaro.org, marcel.apfelbaum@gmail.com, mst@redhat.com, philmd@linaro.org, roqueh@google.com, slongfield@google.com, komlodi@google.com Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::114a; envelope-from=3GmHeZQcKCosz3103sxv33v0t.r315t19-stAt0232v29.36v@flex--komlodi.bounces.google.com; helo=mail-yw1-x114a.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01, USER_IN_DEF_DKIM_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @google.com) X-ZM-MESSAGEID: 1709072733790100007 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" During transactions, these get added to memory attributes at the same time other attributes are added. Similar to the requester ID, these are added on PTWs, GPCs, and descriptor grabbing as well. Signed-off-by: Joe Komlodi --- target/arm/cpu.c | 2 ++ target/arm/cpu.h | 2 ++ target/arm/ptw.c | 4 ++++ 3 files changed, 8 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 9cfbba10c2..dcd2c16c2e 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2404,6 +2404,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) =20 /* For MemTxAttrs. */ env->requester_id =3D cpu->requester_id; + env->memattr_user_defined =3D cpu->memattr_user_defined; =20 qemu_init_vcpu(cs); cpu_reset(cs); @@ -2443,6 +2444,7 @@ static Property arm_cpu_properties[] =3D { DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID), DEFINE_PROP_INT32("core-count", ARMCPU, core_count, -1), DEFINE_PROP_UINT16("requester-id", ARMCPU, requester_id, 0), + DEFINE_PROP_UINT8("memattr-user-defined", ARMCPU, memattr_user_defined= , 0), DEFINE_PROP_END_OF_LIST() }; =20 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 5fc572e077..499a5b25c7 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -777,6 +777,7 @@ typedef struct CPUArchState { =20 /* For MemTxAttrs. */ uint16_t requester_id; + uint8_t memattr_user_defined; } CPUARMState; =20 static inline void set_feature(CPUARMState *env, int feature) @@ -1097,6 +1098,7 @@ struct ArchCPU { =20 /* Requester ID, used in MemTxAttrs. */ uint16_t requester_id; + uint8_t memattr_user_defined; }; =20 typedef struct ARMCPUInfo { diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 148af3a000..b2af3d9052 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -288,6 +288,7 @@ static bool granule_protection_check(CPUARMState *env, = uint64_t paddress, .secure =3D true, .space =3D ARMSS_Root, .requester_id =3D env->requester_id, + .user_defined =3D env->memattr_user_defined, }; ARMCPU *cpu =3D env_archcpu(env); uint64_t gpccr =3D env->cp15.gpccr_el3; @@ -640,6 +641,7 @@ static uint32_t arm_ldl_ptw(CPUARMState *env, S1Transla= te *ptw, .space =3D ptw->out_space, .secure =3D arm_space_is_secure(ptw->out_space), .requester_id =3D env->requester_id, + .user_defined =3D env->memattr_user_defined, }; AddressSpace *as =3D arm_addressspace(cs, attrs); MemTxResult result =3D MEMTX_OK; @@ -687,6 +689,7 @@ static uint64_t arm_ldq_ptw(CPUARMState *env, S1Transla= te *ptw, .space =3D ptw->out_space, .secure =3D arm_space_is_secure(ptw->out_space), .requester_id =3D env->requester_id, + .user_defined =3D env->memattr_user_defined, }; AddressSpace *as =3D arm_addressspace(cs, attrs); MemTxResult result =3D MEMTX_OK; @@ -3310,6 +3313,7 @@ static bool get_phys_addr_nogpc(CPUARMState *env, S1T= ranslate *ptw, result->f.attrs.secure =3D arm_space_is_secure(ptw->in_space); =20 result->f.attrs.requester_id =3D env->requester_id; + result->f.attrs.user_defined =3D env->memattr_user_defined; =20 switch (mmu_idx) { case ARMMMUIdx_Phys_S: --=20 2.44.0.rc0.258.g7320e95886-goog From nobody Tue Nov 26 06:34:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Tue, 27 Feb 2024 14:24:27 -0800 (PST) Date: Tue, 27 Feb 2024 22:24:17 +0000 In-Reply-To: <20240227222417.929367-1-komlodi@google.com> Mime-Version: 1.0 References: <20240227222417.929367-1-komlodi@google.com> X-Mailer: git-send-email 2.44.0.rc1.240.g4c46232300-goog Message-ID: <20240227222417.929367-6-komlodi@google.com> Subject: [RFC PATCH 5/5] hw/pci: Add user-defined memattrs From: Joe Komlodi To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com, peterx@redhat.com, david@redhat.com, peter.maydell@linaro.org, marcel.apfelbaum@gmail.com, mst@redhat.com, philmd@linaro.org, roqueh@google.com, slongfield@google.com, komlodi@google.com Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::b49; envelope-from=3G2HeZQcKCow04214tyw44w1u.s426u2A-tuBu1343w3A.47w@flex--komlodi.bounces.google.com; helo=mail-yb1-xb49.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01, USER_IN_DEF_DKIM_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @google.com) X-ZM-MESSAGEID: 1709072733738100004 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds user-defined bits, which users can set and use on transactions that involve memory attributes. We add it in the MSI function, since the attributes are initialized in that function. We do not add it in pci_dma_rw because the attributes are passed in. Some users might pass in MEMTXATTRS_UNSPECIFIED, and we should respect that instead of injecting user-defined attributes in the function. Signed-off-by: Joe Komlodi --- hw/pci/pci.c | 3 +++ include/hw/pci/pci_device.h | 1 + 2 files changed, 4 insertions(+) diff --git a/hw/pci/pci.c b/hw/pci/pci.c index 6496d027ca..b0bb682f15 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -85,6 +85,8 @@ static Property pci_props[] =3D { QEMU_PCIE_ERR_UNC_MASK_BITNR, true), DEFINE_PROP_BIT("x-pcie-ari-nextfn-1", PCIDevice, cap_present, QEMU_PCIE_ARI_NEXTFN_1_BITNR, false), + DEFINE_PROP_UINT8("memattr-user-defined", PCIDevice, memattr_user_defi= ned, + 0), DEFINE_PROP_END_OF_LIST() }; =20 @@ -361,6 +363,7 @@ static void pci_msi_trigger(PCIDevice *dev, MSIMessage = msg) return; } attrs.requester_id =3D pci_requester_id(dev); + attrs.user_defined =3D dev->memattr_user_defined; address_space_stl_le(&dev->bus_master_as, msg.address, msg.data, attrs, NULL); } diff --git a/include/hw/pci/pci_device.h b/include/hw/pci/pci_device.h index d3dd0f64b2..99be6d72b1 100644 --- a/include/hw/pci/pci_device.h +++ b/include/hw/pci/pci_device.h @@ -84,6 +84,7 @@ struct PCIDevice { * conventional PCI root complex, this field is meaningless. */ PCIReqIDCache requester_id_cache; + uint8_t memattr_user_defined; char name[64]; PCIIORegion io_regions[PCI_NUM_REGIONS]; AddressSpace bus_master_as; --=20 2.44.0.rc0.258.g7320e95886-goog