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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id i13-20020adfe48d000000b0033ae7d768b2sm11319552wrm.117.2024.02.27.05.33.19 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 Feb 2024 05:33:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1709040800; x=1709645600; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=oFeKXeW31Su0U94AYEZ3ImMqkHFM46i1mg2K/MGn0p4=; b=IKo9Xfbqd6xBBFW2ES10/te3r9MPNLAbDh64E/nD/EynTB9XPfFf4ot4hIFV9AQ7Pi z44GH8oIF5A2/A0Thjl2Zh+eULztx5uSocmwO2UqQ/nfw7X9w2RwzuYuLWm0EcjksCf6 lGxxGf2Raz3EjE4QIkeaOS1x488N8A/zCKRQCQcImnOizMhnhCAI3zHU4jQDN7yYx95u W7Fl922jPHtH4nkmsWoOYqkkeWwJUz4aNZ9LRCYb5jV03FwDr2YrEpMmtl4mb65qlKIv ota1QrDVzf1brLxDO4hyhNb/3LHAvBqp+1i/y/mzdsEyhmRKKO9cPgGKYFunMWEvt9ZB /c8A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1709040800; x=1709645600; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=oFeKXeW31Su0U94AYEZ3ImMqkHFM46i1mg2K/MGn0p4=; b=jAHOJQU/qy0bUAS0g9LFTn8Ac4UrBUCnFF873GLtw7IA6iLwL9lKUrDnoGgKh4TjeA 9DLUWjhDszca0Bdh7vgA61Iojq7re+AuRfSM8Da+/X97pfzB3ns4DAZ1YPgWVo9rMfYB ukup7RPnD9YzVebOWcX6PH4oOC28F6BcErLijikpFr9IpALxHMPtALN9QAKHyPB8EZlM CyJ+FMiIkU9v4n72JUtrn3YFPOlKK6jf0SViSSRv9CuYj4HZCzrFZcLon/9LBOSJx2al AIx5D7c6pY5y8igE5vTB105/m50cAcQtLSJZKCogZ7ALDXLDXKkJl7EV+LoNzAnT9x4M Es1g== X-Gm-Message-State: AOJu0YxvSr7N93i9ldw3Wvy4x4L5XWc/ALbdoTk/3XFEXI8Q0N/efy6z 5QwJUkBJrVSk3XzfrdoAHjx3tSZ0otJc82LhJ5PttLVglLbxbIcCjAqGp+Ducd3sCePt9mouPOv 6 X-Google-Smtp-Source: AGHT+IHwp1FYswkHO/xPjoKizp+HsZ74Qic/xrfzWIcUhovQsO2riALGCDiVZ4AYdnfP8ZR5kjEXOg== X-Received: by 2002:adf:f3c4:0:b0:33d:5a6f:a856 with SMTP id g4-20020adff3c4000000b0033d5a6fa856mr7517558wrp.30.1709040799974; Tue, 27 Feb 2024 05:33:19 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 08/45] tests/qtest: Check that EXTI fan-in irqs are correctly connected Date: Tue, 27 Feb 2024 13:32:37 +0000 Message-Id: <20240227133314.1721857-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240227133314.1721857-1-peter.maydell@linaro.org> References: <20240227133314.1721857-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1709040842616100002 From: In=C3=A8s Varhol This commit adds a QTest that verifies each input line of a specific EXTI OR gate can influence the output line. Signed-off-by: In=C3=A8s Varhol Reviewed-by: Peter Maydell Message-id: 20240220184145.106107-3-ines.varhol@telecom-paris.fr Signed-off-by: Peter Maydell --- tests/qtest/stm32l4x5_exti-test.c | 37 +++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/tests/qtest/stm32l4x5_exti-test.c b/tests/qtest/stm32l4x5_exti= -test.c index c3900777139..81830be8aea 100644 --- a/tests/qtest/stm32l4x5_exti-test.c +++ b/tests/qtest/stm32l4x5_exti-test.c @@ -31,6 +31,7 @@ =20 #define EXTI0_IRQ 6 #define EXTI1_IRQ 7 +#define EXTI5_9_IRQ 23 #define EXTI35_IRQ 1 =20 static void enable_nvic_irq(unsigned int n) @@ -499,6 +500,40 @@ static void test_interrupt(void) g_assert_false(check_nvic_pending(EXTI1_IRQ)); } =20 +static void test_orred_interrupts(void) +{ + /* + * For lines EXTI5..9 (fanned-in to NVIC irq 23), + * test that raising the line pends interrupt + * 23 in NVIC. + */ + enable_nvic_irq(EXTI5_9_IRQ); + /* Check that there are no interrupts already pending in PR */ + g_assert_cmpuint(exti_readl(EXTI_PR1), =3D=3D, 0x00000000); + /* Check that this specific interrupt isn't pending in NVIC */ + g_assert_false(check_nvic_pending(EXTI5_9_IRQ)); + + /* Enable interrupt lines EXTI[5..9] */ + exti_writel(EXTI_IMR1, (0x1F << 5)); + + /* Configure interrupt on rising edge */ + exti_writel(EXTI_RTSR1, (0x1F << 5)); + + /* Raise GPIO line i, check that the interrupt is pending */ + for (unsigned i =3D 5; i < 10; i++) { + exti_set_irq(i, 1); + g_assert_cmpuint(exti_readl(EXTI_PR1), =3D=3D, 1 << i); + g_assert_true(check_nvic_pending(EXTI5_9_IRQ)); + + exti_writel(EXTI_PR1, 1 << i); + g_assert_cmpuint(exti_readl(EXTI_PR1), =3D=3D, 0x00000000); + g_assert_true(check_nvic_pending(EXTI5_9_IRQ)); + + unpend_nvic_irq(EXTI5_9_IRQ); + g_assert_false(check_nvic_pending(EXTI5_9_IRQ)); + } +} + int main(int argc, char **argv) { int ret; @@ -515,6 +550,8 @@ int main(int argc, char **argv) qtest_add_func("stm32l4x5/exti/masked_interrupt", test_masked_interrup= t); qtest_add_func("stm32l4x5/exti/interrupt", test_interrupt); qtest_add_func("stm32l4x5/exti/test_edge_selector", test_edge_selector= ); + qtest_add_func("stm32l4x5/exti/test_orred_interrupts", + test_orred_interrupts); =20 qtest_start("-machine b-l475e-iot01a"); ret =3D g_test_run(); --=20 2.34.1