From nobody Tue Nov 26 08:27:21 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.intel.com ARC-Seal: i=1; a=rsa-sha256; t=1709029229; cv=none; d=zohomail.com; s=zohoarc; b=NzY3ViYQwgAnJJk8pq5vRp+18ZtvTW/z4UxlB7Xbplb0KVCJZSDjqlwV9NRMwRmB2/I85dTGoj4Jr4Aiq/gBoCocdbd2rBF+z+3E/HbxDEc5dqiV9yLTvUYJF/0Ybg8LuEAFwLotKQLfC9X/hqGmKac8amAqplLIgNxBWVVt0xM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1709029229; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=ypXDwenEjr6qEaOmpPoUPWVLeo4aDd9JeNRH0HznkVY=; b=lPH2XGW3Oa8j0ySn/0hJy0Wdwr421Wn33OsmEO7G+GItsRZMgTC1NS4hg6P2iXZ3Q+8+l/YuB6hX2QTIS51hmEkkVnFYwyQpvS0Wg4I/6OCIwIxD9tVYatOeqBCaw8SiP2LPC5DjG6VvozPgwhLVrbxUr5ehuVBzvLAO8311AYA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1709029229706227.0282360853539; Tue, 27 Feb 2024 02:20:29 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1reuZ1-00056I-RJ; Tue, 27 Feb 2024 05:19:55 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1reuYn-0004OS-PX for qemu-devel@nongnu.org; Tue, 27 Feb 2024 05:19:44 -0500 Received: from mgamail.intel.com ([192.198.163.13]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1reuYl-00036Z-2q for qemu-devel@nongnu.org; Tue, 27 Feb 2024 05:19:41 -0500 Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by fmvoesa107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Feb 2024 02:19:28 -0800 Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.36]) by fmviesa010.fm.intel.com with ESMTP; 27 Feb 2024 02:19:24 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1709029179; x=1740565179; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=wiBtvC9npNwOGQwvG+wKYWaGKFwDNnpYwHcx9hX6vcs=; b=jisRbi5qjyu4aaF2EocWn5yhRAZ6mjbWDHbnxKCoil5POetTzm1szOdl 5Fwny6Evn4gr9ekQsPChMpHxtiiFgVCM1rBlz2t5eACYn81Z8VdhMireq rkofiefsk6EDwu2wC57JgyaekN38Vaf+ahaR0GPs7p3gBb06qwesgKCh2 u6Iwe/F/miC5LzG7oKaNCJQCVgVMdCuOxFqzfe0bFA3Qy/qjbtmLYxszj 214p5yPl3vHEfO1RTKd5RNXxkFd82zDHBZ0sTsEojII4dsAeC2UoOu4Uu ZKV49KkfB4YrvNDSPkiJYqXx5WyAdZP1a6f5ka2MvLyp46ehZbOEDpROV g==; X-IronPort-AV: E=McAfee;i="6600,9927,10996"; a="6310282" X-IronPort-AV: E=Sophos;i="6.06,187,1705392000"; d="scan'208";a="6310282" X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.06,187,1705392000"; d="scan'208";a="6954788" From: Zhao Liu To: Eduardo Habkost , Marcel Apfelbaum , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , "Michael S . Tsirkin" , Richard Henderson , Paolo Bonzini , Eric Blake , Markus Armbruster , Marcelo Tosatti , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Xiaoyao Li Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, Zhenyu Wang , Zhuocheng Ding , Babu Moger , Yongwei Ma , Zhao Liu Subject: [PATCH v9 07/21] i386/cpu: Use APIC ID info get NumSharingCache for CPUID[0x8000001D].EAX[bits 25:14] Date: Tue, 27 Feb 2024 18:32:17 +0800 Message-Id: <20240227103231.1556302-8-zhao1.liu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240227103231.1556302-1-zhao1.liu@linux.intel.com> References: <20240227103231.1556302-1-zhao1.liu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=192.198.163.13; envelope-from=zhao1.liu@linux.intel.com; helo=mgamail.intel.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.014, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1709029230708100001 Content-Type: text/plain; charset="utf-8" From: Zhao Liu The commit 8f4202fb1080 ("i386: Populate AMD Processor Cache Information for cpuid 0x8000001D") adds the cache topology for AMD CPU by encoding the number of sharing threads directly. From AMD's APM, NumSharingCache (CPUID[0x8000001D].EAX[bits 25:14]) means [1]: The number of logical processors sharing this cache is the value of this field incremented by 1. To determine which logical processors are sharing a cache, determine a Share Id for each processor as follows: ShareId =3D LocalApicId >> log2(NumSharingCache+1) Logical processors with the same ShareId then share a cache. If NumSharingCache+1 is not a power of two, round it up to the next power of two. From the description above, the calculation of this field should be same as CPUID[4].EAX[bits 25:14] for Intel CPUs. So also use the offsets of APIC ID to calculate this field. [1]: APM, vol.3, appendix.E.4.15 Function 8000_001Dh--Cache Topology Information Cc: Babu Moger Tested-by: Yongwei Ma Signed-off-by: Zhao Liu Reviewed-by: Babu Moger Reviewed-by: Xiaoyao Li --- Changes since v7: * Moved this patch after CPUID[4]'s similar change ("i386/cpu: Use APIC ID offset to encode cache topo in CPUID[4]"). (Xiaoyao) * Dropped Michael/Babu's Acked/Reviewed/Tested tags since the code change due to the rebase. * Re-added Yongwei's Tested tag For his re-testing (compilation on Intel platforms). Changes since v3: * Rewrote the subject. (Babu) * Deleted the original "comment/help" expression, as this behavior is confirmed for AMD CPUs. (Babu) * Renamed "num_apic_ids" (v3) to "num_sharing_cache" to match spec definition. (Babu) Changes since v1: * Renamed "l3_threads" to "num_apic_ids" in encode_cache_cpuid8000001d(). (Yanan) * Added the description of the original commit and add Cc. --- target/i386/cpu.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index c77bcbc44d59..df56c7a449c8 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -331,7 +331,7 @@ static void encode_cache_cpuid8000001d(CPUCacheInfo *ca= che, uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx) { - uint32_t l3_threads; + uint32_t num_sharing_cache; assert(cache->size =3D=3D cache->line_size * cache->associativity * cache->partitions * cache->sets); =20 @@ -340,11 +340,11 @@ static void encode_cache_cpuid8000001d(CPUCacheInfo *= cache, =20 /* L3 is shared among multiple cores */ if (cache->level =3D=3D 3) { - l3_threads =3D topo_info->cores_per_die * topo_info->threads_per_c= ore; - *eax |=3D (l3_threads - 1) << 14; + num_sharing_cache =3D 1 << apicid_die_offset(topo_info); } else { - *eax |=3D ((topo_info->threads_per_core - 1) << 14); + num_sharing_cache =3D 1 << apicid_core_offset(topo_info); } + *eax |=3D (num_sharing_cache - 1) << 14; =20 assert(cache->line_size > 0); assert(cache->partitions > 0); --=20 2.34.1