From nobody Tue Nov 26 08:23:43 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.intel.com ARC-Seal: i=1; a=rsa-sha256; t=1709029222; cv=none; d=zohomail.com; s=zohoarc; b=YytO1hsxP6TJnRG4e6LEAz7HsPnUoQS3NZgMknT7ZrLzO6O2qppYPmuqFp1cV6K2Ius+n3OfIL1AKwRwG9zWyx4PNrvLSre8A+xmPdJj1dcREykM3IleB0dQxii6nSXr3Et1UhgZiB9i8eh6PiV4KZr0ZtlFW4wsoYC5MfnaUMs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1709029222; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=dCpqgkjs15noFgou/8Au+vLpCWvn1RkC4IK2uSbHKSY=; b=Yjvwi5AY53wQrhi45UFcBnuw6FkLFxON5x3VPwdJ6bDBtAkSwDrW/uYicO70zl2exuy2xZA4jbEdmwNCzEjaNa5Ied0hlXRFyCpUgYn+AentLTABXkT1o7j8jgFC6nkNB1w9W5pT7wbuhqOZF+rhczaiHCQP5h8/WZOeXUqc7F4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 170902922256361.31643051406445; Tue, 27 Feb 2024 02:20:22 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1reuYh-0004Ds-6U; Tue, 27 Feb 2024 05:19:41 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1reuYU-0004Cj-Ms for qemu-devel@nongnu.org; Tue, 27 Feb 2024 05:19:22 -0500 Received: from mgamail.intel.com ([192.198.163.13]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1reuYT-00036Z-0v for qemu-devel@nongnu.org; Tue, 27 Feb 2024 05:19:22 -0500 Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by fmvoesa107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Feb 2024 02:19:19 -0800 Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.36]) by fmviesa010.fm.intel.com with ESMTP; 27 Feb 2024 02:19:14 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1709029161; x=1740565161; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=+D0kFbwk/6uu2utuPjUeCfJFwddDsRc/EgoeBeVWwmA=; b=NO3YUO9IG3fs61vhK28TXEfUmGIJzu5i76B2Plw3hOeMjRDvSopBYgH7 +tbGK02DRaCGVZqMU7mDXkXBTNfRU+LhbRi47gyy1vtL5SScyUmIQJugE zQLiBFLBNBk1D3Jd5jDnXhxF+rqLwbyAH449ftIL3nC60HYp8RJUso7+1 OJX1UpA71GQI/B7zcQZ6so7kV2UqLC/eTlHzxzqDgzmvT4ZMfeoXM562v UyP59ZHox2OVVZ/9w9j7E/LDbMLSB3JiVQYcNAnLSY16KbthLUUyAzZJ4 kFFAvGsTHjWIWyFQBsWIkNMgR3ecUCfSwFNDgDsCQJWaPI9FdnUsTZY6q w==; X-IronPort-AV: E=McAfee;i="6600,9927,10996"; a="6310248" X-IronPort-AV: E=Sophos;i="6.06,187,1705392000"; d="scan'208";a="6310248" X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.06,187,1705392000"; d="scan'208";a="6954774" From: Zhao Liu To: Eduardo Habkost , Marcel Apfelbaum , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , "Michael S . Tsirkin" , Richard Henderson , Paolo Bonzini , Eric Blake , Markus Armbruster , Marcelo Tosatti , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Xiaoyao Li Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, Zhenyu Wang , Zhuocheng Ding , Babu Moger , Yongwei Ma , Zhao Liu , Robert Hoo Subject: [PATCH v9 05/21] i386/cpu: Fix i/d-cache topology to core level for Intel CPU Date: Tue, 27 Feb 2024 18:32:15 +0800 Message-Id: <20240227103231.1556302-6-zhao1.liu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240227103231.1556302-1-zhao1.liu@linux.intel.com> References: <20240227103231.1556302-1-zhao1.liu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=192.198.163.13; envelope-from=zhao1.liu@linux.intel.com; helo=mgamail.intel.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.014, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1709029224658100005 Content-Type: text/plain; charset="utf-8" From: Zhao Liu For i-cache and d-cache, current QEMU hardcodes the maximum IDs for CPUs sharing cache (CPUID.04H.00H:EAX[bits 25:14] and CPUID.04H.01H:EAX[bits 25:14]) to 0, and this means i-cache and d-cache are shared in the SMT level. This is correct if there's single thread per core, but is wrong for the hyper threading case (one core contains multiple threads) since the i-cache and d-cache are shared in the core level other than SMT level. For AMD CPU, commit 8f4202fb1080 ("i386: Populate AMD Processor Cache Information for cpuid 0x8000001D") has already introduced i/d cache topology as core level by default. Therefore, in order to be compatible with both multi-threaded and single-threaded situations, we should set i-cache and d-cache be shared at the core level by default. This fix changes the default i/d cache topology from per-thread to per-core. Potentially, this change in L1 cache topology may affect the performance of the VM if the user does not specifically specify the topology or bind the vCPU. However, the way to achieve optimal performance should be to create a reasonable topology and set the appropriate vCPU affinity without relying on QEMU's default topology structure. Fixes: 7e3482f82480 ("i386: Helpers to encode cache information consistentl= y") Suggested-by: Robert Hoo Signed-off-by: Zhao Liu Reviewed-by: Xiaoyao Li Tested-by: Babu Moger Tested-by: Yongwei Ma Acked-by: Michael S. Tsirkin --- Changes since v3: * Changed the description of current i/d cache encoding status to avoid misleading to "architectural rules". (Xiaoyao) Changes since v1: * Split this fix from the patch named "i386/cpu: Fix number of addressable IDs in CPUID.04H". * Added the explanation of the impact on performance. (Xiaoyao) --- target/i386/cpu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 7f9082367672..81d9046167e8 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -6113,12 +6113,12 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index= , uint32_t count, switch (count) { case 0: /* L1 dcache info */ encode_cache_cpuid4(env->cache_info_cpuid4.l1d_cache, - 1, cs->nr_cores, + cs->nr_threads, cs->nr_cores, eax, ebx, ecx, edx); break; case 1: /* L1 icache info */ encode_cache_cpuid4(env->cache_info_cpuid4.l1i_cache, - 1, cs->nr_cores, + cs->nr_threads, cs->nr_cores, eax, ebx, ecx, edx); break; case 2: /* L2 cache info */ --=20 2.34.1