From nobody Tue Nov 26 09:37:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.intel.com ARC-Seal: i=1; a=rsa-sha256; t=1709029251; cv=none; d=zohomail.com; s=zohoarc; b=Er/p7yx5VPxaM2RTE02P3czHHFKieOAnzpSEAq6MD5NUrpT7SLf5FBJFWKZHCXbBh+R1bYeXy1UQy5CYT2Wy19StVUckvd5xdKxW5dq2v0S6C0QiXSl5+AW1DjuBVAFYxlQ6h6IUiJYY8nK9t1eAdMEZQ9rpOSOhNJHcQaiWsGM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1709029251; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=aF+qdbIe/xegWbSLUoZj8XcUnnCLGZWeUBd/2eaxkko=; b=laXVtbecekKX9SOUmTuv9SIdPasoeNjjHGTeLuZFNOXB1QnCRgWH5le4BumlVq/J/iKIxjtiJcIQLB7VASIEiDad7r9JmuFhZw8fXo9FQVFE4SrDuqHzTjuDMRz5tbwawKaQnrslGXeF74/Ddq4hiUYUr7Lvpi550fes4N8fAWg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1709029251684473.51987662307135; Tue, 27 Feb 2024 02:20:51 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1reuZa-0007iP-OL; Tue, 27 Feb 2024 05:20:30 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1reuZY-0007UZ-Ql for qemu-devel@nongnu.org; Tue, 27 Feb 2024 05:20:28 -0500 Received: from mgamail.intel.com ([192.198.163.13]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1reuZW-0003gS-Rt for qemu-devel@nongnu.org; Tue, 27 Feb 2024 05:20:28 -0500 Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by fmvoesa107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Feb 2024 02:20:07 -0800 Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.36]) by fmviesa010.fm.intel.com with ESMTP; 27 Feb 2024 02:20:02 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1709029226; x=1740565226; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=WE+yg3E+gmPd/IZEoC7RQitGeBNtyR3NYawZF3AIMbc=; b=cd3N8jxPQtz2dC0kTNAJAIevGs04nOrS50/02LX3qISTxNY6oT184dVY J2tlvh2X74Dq1S/yPocC7Ccmg8PLUrSAK1+QEUyfL1djB2TO7waYs4buV LIbn83pq2kj+G96fn5m5sO1jjvSdWchnM/b+Yf5qjIB0mAR2LQQ4wIe5U KTfoI8jQzqN/EAVrMC2zfIl4OVx4EbYG1LM+Fmbs+zD515iV+mxuXAICX rWKr1sgglJDFh3reSiI+W5XdwQc3TymetS+f1XwqJlSptjGDEii2KxJl5 B+ib2VAX7RpPIJKNcF0YwAyuUOzht92vkJCQWLjqmroN62gZ+Id62SqJj g==; X-IronPort-AV: E=McAfee;i="6600,9927,10996"; a="6310415" X-IronPort-AV: E=Sophos;i="6.06,187,1705392000"; d="scan'208";a="6310415" X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.06,187,1705392000"; d="scan'208";a="6955024" From: Zhao Liu To: Eduardo Habkost , Marcel Apfelbaum , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , "Michael S . Tsirkin" , Richard Henderson , Paolo Bonzini , Eric Blake , Markus Armbruster , Marcelo Tosatti , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Xiaoyao Li Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, Zhenyu Wang , Zhuocheng Ding , Babu Moger , Yongwei Ma , Zhao Liu Subject: [PATCH v9 15/21] i386: Support module_id in X86CPUTopoIDs Date: Tue, 27 Feb 2024 18:32:25 +0800 Message-Id: <20240227103231.1556302-16-zhao1.liu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240227103231.1556302-1-zhao1.liu@linux.intel.com> References: <20240227103231.1556302-1-zhao1.liu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=192.198.163.13; envelope-from=zhao1.liu@linux.intel.com; helo=mgamail.intel.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.014, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1709029252786100007 Content-Type: text/plain; charset="utf-8" From: Zhao Liu Add module_id member in X86CPUTopoIDs. module_id can be parsed from APIC ID, so also update APIC ID parsing rule to support module level. With this support, the conversions with module level between X86CPUTopoIDs, X86CPUTopoInfo and APIC ID are completed. module_id can be also generated from cpu topology, and before i386 supports "modules" in smp, the default "modules per die" (modules * clusters) is only 1, thus the module_id generated in this way is 0, so that it will not conflict with the module_id generated by APIC ID. Tested-by: Yongwei Ma Signed-off-by: Zhuocheng Ding Co-developed-by: Zhuocheng Ding Signed-off-by: Zhao Liu --- Changes since v7: * Mapped x86 module to the smp module instead of cluster. * Dropped Michael/Babu's ACKed/Tested tags since the code change. * Re-added Yongwei's Tested tag For his re-testing. Changes since v1: * Merged the patch "i386: Update APIC ID parsing rule to support module level" into this one. (Yanan) * Moved the apicid_module_width() and apicid_module_offset() support into the previous modules_per_die related patch. (Yanan) --- hw/i386/x86.c | 31 +++++++++++++++++++++---------- include/hw/i386/topology.h | 17 +++++++++++++---- 2 files changed, 34 insertions(+), 14 deletions(-) diff --git a/hw/i386/x86.c b/hw/i386/x86.c index b668cd537cec..33063ce3888b 100644 --- a/hw/i386/x86.c +++ b/hw/i386/x86.c @@ -332,12 +332,9 @@ void x86_cpu_pre_plug(HotplugHandler *hotplug_dev, =20 /* * If APIC ID is not set, - * set it based on socket/die/core/thread properties. + * set it based on socket/die/module/core/thread properties. */ if (cpu->apic_id =3D=3D UNASSIGNED_APIC_ID) { - int max_socket =3D (ms->smp.max_cpus - 1) / - smp_threads / smp_cores / ms->smp.dies; - /* * die-id was optional in QEMU 4.0 and older, so keep it optional * if there's only one die per socket. @@ -349,9 +346,9 @@ void x86_cpu_pre_plug(HotplugHandler *hotplug_dev, if (cpu->socket_id < 0) { error_setg(errp, "CPU socket-id is not set"); return; - } else if (cpu->socket_id > max_socket) { + } else if (cpu->socket_id > ms->smp.sockets - 1) { error_setg(errp, "Invalid CPU socket-id: %u must be in range 0= :%u", - cpu->socket_id, max_socket); + cpu->socket_id, ms->smp.sockets - 1); return; } if (cpu->die_id < 0) { @@ -383,17 +380,27 @@ void x86_cpu_pre_plug(HotplugHandler *hotplug_dev, topo_ids.die_id =3D cpu->die_id; topo_ids.core_id =3D cpu->core_id; topo_ids.smt_id =3D cpu->thread_id; + + /* + * TODO: This is the temporary initialization for topo_ids.module_= id to + * avoid "maybe-uninitialized" compilation errors. Will remove when + * X86CPU supports module_id. + */ + topo_ids.module_id =3D 0; + cpu->apic_id =3D x86_apicid_from_topo_ids(&topo_info, &topo_ids); } =20 cpu_slot =3D x86_find_cpu_slot(MACHINE(x86ms), cpu->apic_id, &idx); if (!cpu_slot) { x86_topo_ids_from_apicid(cpu->apic_id, &topo_info, &topo_ids); + error_setg(errp, - "Invalid CPU [socket: %u, die: %u, core: %u, thread: %u] with" - " APIC ID %" PRIu32 ", valid index range 0:%d", - topo_ids.pkg_id, topo_ids.die_id, topo_ids.core_id, topo_ids.s= mt_id, - cpu->apic_id, ms->possible_cpus->len - 1); + "Invalid CPU [socket: %u, die: %u, module: %u, core: %u, threa= d: %u]" + " with APIC ID %" PRIu32 ", valid index range 0:%d", + topo_ids.pkg_id, topo_ids.die_id, topo_ids.module_id, + topo_ids.core_id, topo_ids.smt_id, cpu->apic_id, + ms->possible_cpus->len - 1); return; } =20 @@ -519,6 +526,10 @@ const CPUArchIdList *x86_possible_cpu_arch_ids(Machine= State *ms) ms->possible_cpus->cpus[i].props.has_die_id =3D true; ms->possible_cpus->cpus[i].props.die_id =3D topo_ids.die_id; } + if (ms->smp.modules > 1) { + ms->possible_cpus->cpus[i].props.has_module_id =3D true; + ms->possible_cpus->cpus[i].props.module_id =3D topo_ids.module= _id; + } ms->possible_cpus->cpus[i].props.has_core_id =3D true; ms->possible_cpus->cpus[i].props.core_id =3D topo_ids.core_id; ms->possible_cpus->cpus[i].props.has_thread_id =3D true; diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h index ea871045779d..dff49fce1154 100644 --- a/include/hw/i386/topology.h +++ b/include/hw/i386/topology.h @@ -50,6 +50,7 @@ typedef uint32_t apic_id_t; typedef struct X86CPUTopoIDs { unsigned pkg_id; unsigned die_id; + unsigned module_id; unsigned core_id; unsigned smt_id; } X86CPUTopoIDs; @@ -143,6 +144,7 @@ static inline apic_id_t x86_apicid_from_topo_ids(X86CPU= TopoInfo *topo_info, { return (topo_ids->pkg_id << apicid_pkg_offset(topo_info)) | (topo_ids->die_id << apicid_die_offset(topo_info)) | + (topo_ids->module_id << apicid_module_offset(topo_info)) | (topo_ids->core_id << apicid_core_offset(topo_info)) | topo_ids->smt_id; } @@ -156,12 +158,16 @@ static inline void x86_topo_ids_from_idx(X86CPUTopoIn= fo *topo_info, X86CPUTopoIDs *topo_ids) { unsigned nr_dies =3D topo_info->dies_per_pkg; - unsigned nr_cores =3D topo_info->cores_per_module * - topo_info->modules_per_die; + unsigned nr_modules =3D topo_info->modules_per_die; + unsigned nr_cores =3D topo_info->cores_per_module; unsigned nr_threads =3D topo_info->threads_per_core; =20 - topo_ids->pkg_id =3D cpu_index / (nr_dies * nr_cores * nr_threads); - topo_ids->die_id =3D cpu_index / (nr_cores * nr_threads) % nr_dies; + topo_ids->pkg_id =3D cpu_index / (nr_dies * nr_modules * + nr_cores * nr_threads); + topo_ids->die_id =3D cpu_index / (nr_modules * nr_cores * + nr_threads) % nr_dies; + topo_ids->module_id =3D cpu_index / (nr_cores * nr_threads) % + nr_modules; topo_ids->core_id =3D cpu_index / nr_threads % nr_cores; topo_ids->smt_id =3D cpu_index % nr_threads; } @@ -179,6 +185,9 @@ static inline void x86_topo_ids_from_apicid(apic_id_t a= picid, topo_ids->core_id =3D (apicid >> apicid_core_offset(topo_info)) & ~(0xFFFFFFFFUL << apicid_core_width(topo_info)); + topo_ids->module_id =3D + (apicid >> apicid_module_offset(topo_info)) & + ~(0xFFFFFFFFUL << apicid_module_width(topo_info)); topo_ids->die_id =3D (apicid >> apicid_die_offset(topo_info)) & ~(0xFFFFFFFFUL << apicid_die_width(topo_info)); --=20 2.34.1