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[176.184.33.214]) by smtp.gmail.com with ESMTPSA id m22-20020a056000175600b0033d1b653e4csm10609691wrf.54.2024.02.27.00.39.55 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 27 Feb 2024 00:39:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1709023197; x=1709627997; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=F4m0v/in85DGPLUDveir9W6g6TNXCVbXdqiQPBjdgEs=; b=DBJSLat2yaKXo9mPcMH5NLel2QodCcVSKNyi4J950M+fe3Da8JWf2nWEwo1DbFse20 QVV+WLHyGGI7Ip2LL3W4YgWZEx2UbjSIyLwYq66Zm7YJ5atWmebVZpDrh7hbSpdPVeyB UsuWAdn4U7vsB4m0ELV/IhlJoUG0eUeA3Tdm183sl7NgdRsdx87CXAJWw/ntzC2udYm5 879UEOQUltR6j6pwKKgChN2XMKlgcsUbrB8N+xFewmPm9jLn6iTGMBs+qxQmaGonFWHh fT/iBV7S7tRqXACMUg4cGobRYpcLktKWerTTQ5wYvhNFOrvyf+GOn6FgPVi2feA+oedG co5Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1709023197; x=1709627997; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=F4m0v/in85DGPLUDveir9W6g6TNXCVbXdqiQPBjdgEs=; b=gSRFPlvLQWIVD+F2V4E42hWV+C3kudy8Nfk/Og/Qj85N/NLhdPr3kRP8IB3ywnGRBh Uj1ge9+qC9V/d8GYFTZYPynSq/61Y8WKpECQ1DDGXYcxbkJvvtqRTpbZJmgi3qXr/aZp wrJIDFW8zyqsObeWRcNQdxcOduSKVOx6lpnRi8hsXAG5IZKBOl7hfkLOXAcHuqwBRJLi zX1AtFvY6IwngcBIYvoc8E32w+vlqC55E4j/C4cSnetX7D+IK3PbHjkArG8u76J7YVGJ XkZgagCnkKDX7UqtA4iuj7dYDo11OK2KGK4g/j6mhshg0yGKeUxZwkh0CPyF/LwlF51e zIBQ== X-Gm-Message-State: AOJu0YwiuuCkGnIwRp5KtQOYdbl0WWpCvAxuPLIqxFylwYzD25eE4JAO OkIaeMAyS2Zeu0sqPyuPZKORSCgiAX1Jpe/z7IBeJaeK5GsQf0T/pkLV+FpOrzR4E629pKszPVS L X-Google-Smtp-Source: AGHT+IEEnJlLvJWBb1m5MP2/aP43IqfvjxmdwHQUEHjmUidYllIDHumkJYi0anWv+qlbvnykKw5irg== X-Received: by 2002:a05:6000:71b:b0:33d:c652:7c41 with SMTP id bs27-20020a056000071b00b0033dc6527c41mr6627002wrb.71.1709023196656; Tue, 27 Feb 2024 00:39:56 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, qemu-block@nongnu.org, qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Peter Maydell Subject: [PULL 01/30] hw/arm: Inline sysbus_create_simple(PL110 / PL111) Date: Tue, 27 Feb 2024 09:39:17 +0100 Message-ID: <20240227083948.5427-2-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240227083948.5427-1-philmd@linaro.org> References: <20240227083948.5427-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=philmd@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1709023597883100017 We want to set another qdev property (a link) for the pl110 and pl111 devices, we can not use sysbus_create_simple() which only passes sysbus base address and IRQs as arguments. Inline it so we can set the link property in the next commit. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20240226173805.289-2-philmd@linaro.org> --- hw/arm/integratorcp.c | 5 ++++- hw/arm/realview.c | 5 ++++- hw/arm/versatilepb.c | 6 +++++- hw/arm/vexpress.c | 10 ++++++++-- 4 files changed, 21 insertions(+), 5 deletions(-) diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c index f016d20485..5b002da350 100644 --- a/hw/arm/integratorcp.c +++ b/hw/arm/integratorcp.c @@ -670,7 +670,10 @@ static void integratorcp_init(MachineState *machine) smc91c111_init(0xc8000000, pic[27]); } =20 - sysbus_create_simple("pl110", 0xc0000000, pic[22]); + dev =3D qdev_new("pl110"); + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xc0000000); + sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[22]); =20 integrator_binfo.ram_size =3D ram_size; arm_load_kernel(cpu, machine, &integrator_binfo); diff --git a/hw/arm/realview.c b/hw/arm/realview.c index 9058f5b414..77300e92e5 100644 --- a/hw/arm/realview.c +++ b/hw/arm/realview.c @@ -238,7 +238,10 @@ static void realview_init(MachineState *machine, sysbus_create_simple("pl061", 0x10014000, pic[7]); gpio2 =3D sysbus_create_simple("pl061", 0x10015000, pic[8]); =20 - sysbus_create_simple("pl111", 0x10020000, pic[23]); + dev =3D qdev_new("pl111"); + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0x10020000); + sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[23]); =20 dev =3D sysbus_create_varargs("pl181", 0x10005000, pic[17], pic[18], N= ULL); /* Wire up MMC card detect and read-only signals. These have diff --git a/hw/arm/versatilepb.c b/hw/arm/versatilepb.c index d10b75dfdb..7e04b23af8 100644 --- a/hw/arm/versatilepb.c +++ b/hw/arm/versatilepb.c @@ -299,7 +299,11 @@ static void versatile_init(MachineState *machine, int = board_id) =20 /* The versatile/PB actually has a modified Color LCD controller that includes hardware cursor support from the PL111. */ - dev =3D sysbus_create_simple("pl110_versatile", 0x10120000, pic[16]); + dev =3D qdev_new("pl110_versatile"); + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0x10120000); + sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[16]); + /* Wire up the mux control signals from the SYS_CLCD register */ qdev_connect_gpio_out(sysctl, 0, qdev_get_gpio_in(dev, 0)); =20 diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c index aa5f3ca0d4..671986c21e 100644 --- a/hw/arm/vexpress.c +++ b/hw/arm/vexpress.c @@ -276,6 +276,7 @@ static void a9_daughterboard_init(VexpressMachineState = *vms, { MachineState *machine =3D MACHINE(vms); MemoryRegion *sysmem =3D get_system_memory(); + DeviceState *dev; =20 if (ram_size > 0x40000000) { /* 1GB is the maximum the address space permits */ @@ -297,7 +298,9 @@ static void a9_daughterboard_init(VexpressMachineState = *vms, /* Daughterboard peripherals : 0x10020000 .. 0x20000000 */ =20 /* 0x10020000 PL111 CLCD (daughterboard) */ - sysbus_create_simple("pl111", 0x10020000, pic[44]); + dev =3D qdev_new("pl111"); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0x10020000); + sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[44]); =20 /* 0x10060000 AXI RAM */ /* 0x100e0000 PL341 Dynamic Memory Controller */ @@ -650,7 +653,10 @@ static void vexpress_common_init(MachineState *machine) =20 /* VE_COMPACTFLASH: not modelled */ =20 - sysbus_create_simple("pl111", map[VE_CLCD], pic[14]); + dev =3D qdev_new("pl111"); + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, map[VE_CLCD]); + sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[14]); =20 dinfo =3D drive_get(IF_PFLASH, 0, 0); pflash0 =3D ve_pflash_cfi01_register(map[VE_NORFLASH0], "vexpress.flas= h0", --=20 2.41.0