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Iglesias" , Anton Johansson , Mark Cave-Ayland , Peter Maydell , Zhao Liu , Eduardo Habkost , Marcel Apfelbaum , Igor Mammedov , Richard Henderson , Ani Sinha , Bernhard Beschow , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Paolo Bonzini , "Michael S. Tsirkin" , Laszlo Ersek , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [RFC PATCH 4/5] hw/i386/q35: Wire virtual SMI# lines to ICH9 chipset Date: Mon, 26 Feb 2024 17:49:11 +0100 Message-ID: <20240226164913.94077-5-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240226164913.94077-1-philmd@linaro.org> References: <20240226164913.94077-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::22e; envelope-from=philmd@linaro.org; helo=mail-lj1-x22e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1708966243580100003 We use virtual SMI lines for the virtualized q35 machine (see commit 5ce45c7a2b "hw/isa/lpc_ich9: add broadcast SMI feature"). Expose them as QDev GPIO at the machine level. Wire them to the ICH9 chipset. This allows removing a pair of calls to cpu_interrupt() from the ICH9 model and make it target agnostic. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/isa/ich9_lpc.h | 12 ++++++++++++ include/hw/southbridge/ich9.h | 1 + hw/i386/pc_q35.c | 26 ++++++++++++++++++++++++++ hw/isa/ich9_lpc.c | 10 ++++------ hw/southbridge/ich9.c | 1 + 5 files changed, 44 insertions(+), 6 deletions(-) diff --git a/include/hw/isa/ich9_lpc.h b/include/hw/isa/ich9_lpc.h index b64d88b395..f11ae7e762 100644 --- a/include/hw/isa/ich9_lpc.h +++ b/include/hw/isa/ich9_lpc.h @@ -21,6 +21,17 @@ OBJECT_DECLARE_SIMPLE_TYPE(ICH9LPCState, ICH9_LPC_DEVICE) =20 #define ICH9_CC_SIZE (16 * 1024) /* 16KB. Chipset configuration registers = */ =20 +/* + * Real ICH9 contains a single SMI output line and doesn't broadcast CPUs. + * Virtualized ICH9 allows broadcasting upon negatiation with guest, see + * commit 5ce45c7a2b. + */ +enum { + ICH9_VIRT_SMI_BROADCAST, + ICH9_VIRT_SMI_CURRENT, +#define ICH9_VIRT_SMI_COUNT 2 +}; + struct ICH9LPCState { /* ICH9 LPC PCI to ISA bridge */ PCIDevice d; @@ -71,6 +82,7 @@ struct ICH9LPCState { Notifier machine_ready; =20 qemu_irq gsi[IOAPIC_NUM_PINS]; + qemu_irq virt_smi[ICH9_VIRT_SMI_COUNT]; }; =20 #define ICH9_MASK(bit, ms_bit, ls_bit) \ diff --git a/include/hw/southbridge/ich9.h b/include/hw/southbridge/ich9.h index a8da4a8665..48a4212ed8 100644 --- a/include/hw/southbridge/ich9.h +++ b/include/hw/southbridge/ich9.h @@ -17,6 +17,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(ICH9State, ICH9_SOUTHBRIDGE) #define ICH9_PCIE_FUNC_MAX 6 =20 #define ICH9_GPIO_GSI "gsi" +#define ICH9_VIRT_SMI "x-virt-smi" =20 #define ICH9_LPC_SMI_NEGOTIATED_FEAT_PROP "x-smi-negotiated-features" =20 diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index 31ab0ae77b..77fe8932e8 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -50,6 +50,7 @@ #include "hw/ide/ahci-pci.h" #include "hw/intc/ioapic.h" #include "hw/southbridge/ich9.h" +#include "hw/isa/ich9_lpc.h" #include "qapi/error.h" #include "qemu/error-report.h" #include "sysemu/numa.h" @@ -58,6 +59,25 @@ #include "hw/i386/acpi-build.h" #include "target/i386/cpu.h" =20 +/* + * Kludge IRQ handler for ICH9 virtual SMI delivery. + * IRQ#0: broadcast + * IRQ#1: deliver to current CPU + */ +static void pc_q35_ich9_virt_smi(void *opaque, int irq, int level) +{ + assert(level); + if (irq) { + cpu_interrupt(current_cpu, CPU_INTERRUPT_SMI); + } else { + CPUState *cs; + + CPU_FOREACH(cs) { + cpu_interrupt(cs, CPU_INTERRUPT_SMI); + } + } +} + /* PC hardware initialisation */ static void pc_q35_init(MachineState *machine) { @@ -65,6 +85,7 @@ static void pc_q35_init(MachineState *machine) PCMachineClass *pcmc =3D PC_MACHINE_GET_CLASS(pcms); X86MachineState *x86ms =3D X86_MACHINE(machine); Object *phb; + qemu_irq *smi_irq; DeviceState *ich9; Object *lpc_obj; MemoryRegion *system_memory =3D get_system_memory(); @@ -160,6 +181,8 @@ static void pc_q35_init(MachineState *machine) =20 /* irq lines */ gsi_state =3D pc_gsi_create(&x86ms->gsi, true); + smi_irq =3D qemu_allocate_irqs(pc_q35_ich9_virt_smi, NULL, + ICH9_VIRT_SMI_COUNT); =20 ich9 =3D qdev_new(TYPE_ICH9_SOUTHBRIDGE); object_property_add_child(OBJECT(machine), "ich9", OBJECT(ich9)); @@ -168,6 +191,9 @@ static void pc_q35_init(MachineState *machine) for (i =3D 0; i < IOAPIC_NUM_PINS; i++) { qdev_connect_gpio_out_named(ich9, ICH9_GPIO_GSI, i, x86ms->gsi[i]); } + for (i =3D 0; i < ICH9_VIRT_SMI_COUNT; i++) { + qdev_connect_gpio_out_named(ich9, ICH9_VIRT_SMI, i, smi_irq[i]); + } qdev_prop_set_bit(ich9, "d2p-enabled", false); qdev_prop_set_bit(ich9, "smm-enabled", x86_machine_is_smm_enabled(x86m= s)); qdev_prop_set_bit(ich9, "sata-enabled", pcms->sata_enabled); diff --git a/hw/isa/ich9_lpc.c b/hw/isa/ich9_lpc.c index b1f41158c5..599cb0ee86 100644 --- a/hw/isa/ich9_lpc.c +++ b/hw/isa/ich9_lpc.c @@ -30,7 +30,6 @@ =20 #include "qemu/osdep.h" #include "qemu/log.h" -#include "cpu.h" #include "qapi/error.h" #include "qapi/visitor.h" #include "qemu/range.h" @@ -495,12 +494,9 @@ static void ich9_apm_ctrl_changed(uint32_t val, void *= arg) if (lpc->pm.smi_en & ICH9_PMIO_SMI_EN_APMC_EN) { if (lpc->smi_negotiated_features & (UINT64_C(1) << ICH9_LPC_SMI_F_BROADCAST_BIT)) { - CPUState *cs; - CPU_FOREACH(cs) { - cpu_interrupt(cs, CPU_INTERRUPT_SMI); - } + qemu_irq_raise(lpc->virt_smi[ICH9_VIRT_SMI_BROADCAST]); } else { - cpu_interrupt(current_cpu, CPU_INTERRUPT_SMI); + qemu_irq_raise(lpc->virt_smi[ICH9_VIRT_SMI_CURRENT]); } } } @@ -700,6 +696,8 @@ static void ich9_lpc_initfn(Object *obj) =20 qdev_init_gpio_out_named(DEVICE(lpc), lpc->gsi, ICH9_GPIO_GSI, IOAPIC_NUM_PINS); + qdev_init_gpio_out_named(DEVICE(lpc), lpc->virt_smi, + ICH9_VIRT_SMI, ARRAY_SIZE(lpc->virt_smi)); =20 object_property_add_uint8_ptr(obj, ACPI_PM_PROP_SCI_INT, &lpc->sci_gsi, OBJ_PROP_FLAG_READ); diff --git a/hw/southbridge/ich9.c b/hw/southbridge/ich9.c index 521925b462..d5e131cff3 100644 --- a/hw/southbridge/ich9.c +++ b/hw/southbridge/ich9.c @@ -64,6 +64,7 @@ static void ich9_init(Object *obj) =20 object_initialize_child(obj, "lpc", &s->lpc, TYPE_ICH9_LPC_DEVICE); qdev_pass_gpios(DEVICE(&s->lpc), DEVICE(s), ICH9_GPIO_GSI); + qdev_pass_gpios(DEVICE(&s->lpc), DEVICE(s), ICH9_VIRT_SMI); qdev_prop_set_int32(DEVICE(&s->lpc), "addr", ICH9_LPC_DEVFN); qdev_prop_set_bit(DEVICE(&s->lpc), "multifunction", true); object_property_add_alias(obj, "smm-enabled", --=20 2.41.0