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Iglesias" , Anton Johansson , Mark Cave-Ayland , Peter Maydell , Zhao Liu , Eduardo Habkost , Marcel Apfelbaum , Igor Mammedov , Richard Henderson , Ani Sinha , Bernhard Beschow , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Paolo Bonzini , "Michael S. Tsirkin" , Laszlo Ersek , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 1/5] target/i386/cpu: Expose SMI# IRQ line via QDev Date: Mon, 26 Feb 2024 17:49:08 +0100 Message-ID: <20240226164913.94077-2-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240226164913.94077-1-philmd@linaro.org> References: <20240226164913.94077-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=philmd@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1708966263555100003 In order to remove calls to cpu_interrupt() from hw/ code, expose the SMI# interrupt via QDev as named GPIO. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/i386/cpu-internal.h | 1 + target/i386/cpu-sysemu.c | 11 +++++++++++ target/i386/cpu.c | 2 ++ 3 files changed, 14 insertions(+) diff --git a/target/i386/cpu-internal.h b/target/i386/cpu-internal.h index 9baac5c0b4..9d76bb77cf 100644 --- a/target/i386/cpu-internal.h +++ b/target/i386/cpu-internal.h @@ -62,6 +62,7 @@ GuestPanicInformation *x86_cpu_get_crash_info(CPUState *c= s); void x86_cpu_get_crash_info_qom(Object *obj, Visitor *v, const char *name, void *opaque, Error **er= rp); =20 +void x86_cpu_smi_irq(void *opaque, int irq, int level); void x86_cpu_apic_create(X86CPU *cpu, Error **errp); void x86_cpu_apic_realize(X86CPU *cpu, Error **errp); void x86_cpu_machine_reset_cb(void *opaque); diff --git a/target/i386/cpu-sysemu.c b/target/i386/cpu-sysemu.c index 7422096737..7684a7f01e 100644 --- a/target/i386/cpu-sysemu.c +++ b/target/i386/cpu-sysemu.c @@ -370,3 +370,14 @@ void x86_cpu_get_crash_info_qom(Object *obj, Visitor *= v, qapi_free_GuestPanicInformation(panic_info); } =20 +void x86_cpu_smi_irq(void *opaque, int irq, int level) +{ + DeviceState *dev =3D opaque; + CPUState *cs =3D CPU(dev); + + if (level) { + cpu_interrupt(cs, CPU_INTERRUPT_SMI); + } else { + cpu_reset_interrupt(cs, CPU_INTERRUPT_SMI); + } +} diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 7f90823676..6b4462d533 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7463,6 +7463,8 @@ static void x86_cpu_realizefn(DeviceState *dev, Error= **errp) } =20 #ifndef CONFIG_USER_ONLY + qdev_init_gpio_in_named(dev, x86_cpu_smi_irq, "SMI", 1); + x86_cpu_apic_realize(cpu, &local_err); if (local_err !=3D NULL) { goto out; --=20 2.41.0 From nobody Tue Nov 26 08:55:12 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; 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Iglesias" , Anton Johansson , Mark Cave-Ayland , Peter Maydell , Zhao Liu , Eduardo Habkost , Marcel Apfelbaum , Igor Mammedov , Richard Henderson , Ani Sinha , Bernhard Beschow , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Paolo Bonzini , "Michael S. Tsirkin" , Laszlo Ersek , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 2/5] hw/i386/piix: Set CPU SMI# interrupt using QDev GPIO API Date: Mon, 26 Feb 2024 17:49:09 +0100 Message-ID: <20240226164913.94077-3-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240226164913.94077-1-philmd@linaro.org> References: <20240226164913.94077-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::231; envelope-from=philmd@linaro.org; helo=mail-lj1-x231.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1708966208227100004 Use the CPU "SMI" IRQ, removing a call to cpu_interrupt() from hw/. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/i386/pc.h | 2 -- hw/i386/pc.c | 9 --------- hw/i386/pc_piix.c | 4 ++-- 3 files changed, 2 insertions(+), 13 deletions(-) diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index 4bb1899602..c8227e18c3 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -148,8 +148,6 @@ GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabl= ed); /* pc.c */ extern int fd_bootchk; =20 -void pc_acpi_smi_interrupt(void *opaque, int irq, int level); - #define PCI_HOST_PROP_RAM_MEM "ram-mem" #define PCI_HOST_PROP_PCI_MEM "pci-mem" #define PCI_HOST_PROP_SYSTEM_MEM "system-mem" diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 880e95de26..1df9f5ba90 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -651,15 +651,6 @@ static gboolean pc_init_ne2k_isa(ISABus *bus, NICInfo = *nd, Error **errp) return true; } =20 -void pc_acpi_smi_interrupt(void *opaque, int irq, int level) -{ - X86CPU *cpu =3D opaque; - - if (level) { - cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); - } -} - static void pc_machine_done(Notifier *notifier, void *data) { diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index ce6aad758d..447130ade1 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -345,9 +345,9 @@ static void pc_init1(MachineState *machine, pc_cmos_init(pcms, x86ms->rtc); =20 if (piix4_pm) { - smi_irq =3D qemu_allocate_irq(pc_acpi_smi_interrupt, first_cpu, 0); - + smi_irq =3D qdev_get_gpio_in_named(DEVICE(first_cpu), "SMI", 0); qdev_connect_gpio_out_named(DEVICE(piix4_pm), "smi-irq", 0, smi_ir= q); + pcms->smbus =3D I2C_BUS(qdev_get_child_bus(DEVICE(piix4_pm), "i2c"= )); /* TODO: Populate SPD eeprom data. */ smbus_eeprom_init(pcms->smbus, 8, NULL, 0); --=20 2.41.0 From nobody Tue Nov 26 08:55:12 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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Iglesias" , Anton Johansson , Mark Cave-Ayland , Peter Maydell , Zhao Liu , Eduardo Habkost , Marcel Apfelbaum , Igor Mammedov , Richard Henderson , Ani Sinha , Bernhard Beschow , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Paolo Bonzini , "Michael S. Tsirkin" , Laszlo Ersek , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [RFC PATCH 3/5] hw/ahci/ich9_tco: Set CPU SMI# interrupt using QDev GPIO API Date: Mon, 26 Feb 2024 17:49:10 +0100 Message-ID: <20240226164913.94077-4-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240226164913.94077-1-philmd@linaro.org> References: <20240226164913.94077-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=philmd@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1708966237622100003 Use the CPU "SMI" IRQ, removing a call to cpu_interrupt() from hw/. Keep a reference to the IRQ in the TCOIORegs structure, which while being names with the Regs suffix doesn't contain only registers. Remove ich9_generate_smi(). Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- I suppose ideally ICH9 TCO would be a QOM object... --- include/hw/acpi/ich9.h | 1 + include/hw/acpi/ich9_tco.h | 4 ++-- hw/acpi/ich9.c | 3 ++- hw/acpi/ich9_tco.c | 13 ++++++++++--- hw/isa/ich9_lpc.c | 5 ----- 5 files changed, 15 insertions(+), 11 deletions(-) diff --git a/include/hw/acpi/ich9.h b/include/hw/acpi/ich9.h index 3587a35c9f..84e1557257 100644 --- a/include/hw/acpi/ich9.h +++ b/include/hw/acpi/ich9.h @@ -49,6 +49,7 @@ typedef struct ICH9LPCPMRegs { uint32_t smi_sts; =20 qemu_irq irq; /* SCI */ + qemu_irq smi; /* SMI */ =20 uint32_t pm_io_base; Notifier powerdown_notifier; diff --git a/include/hw/acpi/ich9_tco.h b/include/hw/acpi/ich9_tco.h index 68ee64942f..31730b8e14 100644 --- a/include/hw/acpi/ich9_tco.h +++ b/include/hw/acpi/ich9_tco.h @@ -73,10 +73,10 @@ typedef struct TCOIORegs { uint8_t timeouts_no; =20 MemoryRegion io; + qemu_irq smi; } TCOIORegs; =20 -void ich9_acpi_pm_tco_init(TCOIORegs *tr, MemoryRegion *parent); -void ich9_generate_smi(void); +void ich9_acpi_pm_tco_init(TCOIORegs *tr, MemoryRegion *parent, qemu_irq s= mi); =20 extern const VMStateDescription vmstate_ich9_sm_tco; =20 diff --git a/hw/acpi/ich9.c b/hw/acpi/ich9.c index 1f41ab49c4..e0b3838365 100644 --- a/hw/acpi/ich9.c +++ b/hw/acpi/ich9.c @@ -318,7 +318,8 @@ void ich9_pm_init(PCIDevice *lpc_pci, ICH9LPCPMRegs *pm= , qemu_irq sci_irq) memory_region_add_subregion(&pm->io, ICH9_PMIO_SMI_EN, &pm->io_smi); =20 if (pm->enable_tco) { - ich9_acpi_pm_tco_init(&pm->tco_regs, &pm->io); + pm->smi =3D qdev_get_gpio_in_named(DEVICE(first_cpu), "SMI", 0); + ich9_acpi_pm_tco_init(&pm->tco_regs, &pm->io, pm->smi); } =20 if (pm->acpi_pci_hotplug.use_acpi_hotplug_bridge) { diff --git a/hw/acpi/ich9_tco.c b/hw/acpi/ich9_tco.c index 7499ec17db..1061b18b7e 100644 --- a/hw/acpi/ich9_tco.c +++ b/hw/acpi/ich9_tco.c @@ -14,6 +14,7 @@ =20 #include "hw/acpi/ich9_tco.h" #include "hw/isa/ich9_lpc.h" +#include "hw/irq.h" #include "trace.h" =20 enum { @@ -31,6 +32,11 @@ enum { SW_IRQ_GEN_DEFAULT =3D 0x03, }; =20 +static void ich9_generate_smi(TCOIORegs *tr) +{ + qemu_irq_raise(tr->smi); +} + static inline void tco_timer_reload(TCOIORegs *tr) { int ticks =3D tr->tco.tmr & TCO_TMR_MASK; @@ -72,7 +78,7 @@ static void tco_timer_expired(void *opaque) } =20 if (pm->smi_en & ICH9_PMIO_SMI_EN_TCO_EN) { - ich9_generate_smi(); + ich9_generate_smi(tr); } tr->tco.rld =3D tr->tco.tmr; tco_timer_reload(tr); @@ -154,7 +160,7 @@ static void tco_ioport_writew(TCOIORegs *tr, uint32_t a= ddr, uint32_t val) case TCO_DAT_IN: tr->tco.din =3D val; tr->tco.sts1 |=3D SW_TCO_SMI; - ich9_generate_smi(); + ich9_generate_smi(tr); break; case TCO_DAT_OUT: tr->tco.dout =3D val; @@ -225,7 +231,7 @@ static const MemoryRegionOps tco_io_ops =3D { .endianness =3D DEVICE_LITTLE_ENDIAN, }; =20 -void ich9_acpi_pm_tco_init(TCOIORegs *tr, MemoryRegion *parent) +void ich9_acpi_pm_tco_init(TCOIORegs *tr, MemoryRegion *parent, qemu_irq s= mi) { *tr =3D (TCOIORegs) { .tco =3D { @@ -245,6 +251,7 @@ void ich9_acpi_pm_tco_init(TCOIORegs *tr, MemoryRegion = *parent) .tco_timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, tco_timer_expi= red, tr), .expire_time =3D -1, .timeouts_no =3D 0, + .smi =3D smi, }; memory_region_init_io(&tr->io, memory_region_owner(parent), &tco_io_ops, tr, "sm-tco", ICH9_PMIO_TCO_LEN); diff --git a/hw/isa/ich9_lpc.c b/hw/isa/ich9_lpc.c index 2339f66e0f..b1f41158c5 100644 --- a/hw/isa/ich9_lpc.c +++ b/hw/isa/ich9_lpc.c @@ -353,11 +353,6 @@ static PCIINTxRoute ich9_route_intx_pin_to_irq(void *o= paque, int pirq_pin) return route; } =20 -void ich9_generate_smi(void) -{ - cpu_interrupt(first_cpu, CPU_INTERRUPT_SMI); -} - /* Returns -1 on error, IRQ number on success */ static int ich9_lpc_sci_irq(ICH9LPCState *lpc) { --=20 2.41.0 From nobody Tue Nov 26 08:55:12 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1708966241; cv=none; d=zohomail.com; s=zohoarc; b=JgVnjuFdJdb0WSjo4V7wVp+nfSZ8Jvw1cDauV+KZJXxGfA9esGYb/WFvHwh6TSrSjyyg3pQB8DpCjKXmamRZw4H36jsXXGld+iXgct0/bIvkLvBPbPZ6qY0nWo63RtvuRNpsMYYB0wZnJrK8X4BASvt4CLYcfslNrIhYY9wgooM= ARC-Message-Signature: i=1; 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Mon, 26 Feb 2024 08:49:42 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Thomas Huth , "Edgar E . Iglesias" , Anton Johansson , Mark Cave-Ayland , Peter Maydell , Zhao Liu , Eduardo Habkost , Marcel Apfelbaum , Igor Mammedov , Richard Henderson , Ani Sinha , Bernhard Beschow , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Paolo Bonzini , "Michael S. Tsirkin" , Laszlo Ersek , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [RFC PATCH 4/5] hw/i386/q35: Wire virtual SMI# lines to ICH9 chipset Date: Mon, 26 Feb 2024 17:49:11 +0100 Message-ID: <20240226164913.94077-5-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240226164913.94077-1-philmd@linaro.org> References: <20240226164913.94077-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::22e; envelope-from=philmd@linaro.org; helo=mail-lj1-x22e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1708966243580100003 We use virtual SMI lines for the virtualized q35 machine (see commit 5ce45c7a2b "hw/isa/lpc_ich9: add broadcast SMI feature"). Expose them as QDev GPIO at the machine level. Wire them to the ICH9 chipset. This allows removing a pair of calls to cpu_interrupt() from the ICH9 model and make it target agnostic. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/isa/ich9_lpc.h | 12 ++++++++++++ include/hw/southbridge/ich9.h | 1 + hw/i386/pc_q35.c | 26 ++++++++++++++++++++++++++ hw/isa/ich9_lpc.c | 10 ++++------ hw/southbridge/ich9.c | 1 + 5 files changed, 44 insertions(+), 6 deletions(-) diff --git a/include/hw/isa/ich9_lpc.h b/include/hw/isa/ich9_lpc.h index b64d88b395..f11ae7e762 100644 --- a/include/hw/isa/ich9_lpc.h +++ b/include/hw/isa/ich9_lpc.h @@ -21,6 +21,17 @@ OBJECT_DECLARE_SIMPLE_TYPE(ICH9LPCState, ICH9_LPC_DEVICE) =20 #define ICH9_CC_SIZE (16 * 1024) /* 16KB. Chipset configuration registers = */ =20 +/* + * Real ICH9 contains a single SMI output line and doesn't broadcast CPUs. + * Virtualized ICH9 allows broadcasting upon negatiation with guest, see + * commit 5ce45c7a2b. + */ +enum { + ICH9_VIRT_SMI_BROADCAST, + ICH9_VIRT_SMI_CURRENT, +#define ICH9_VIRT_SMI_COUNT 2 +}; + struct ICH9LPCState { /* ICH9 LPC PCI to ISA bridge */ PCIDevice d; @@ -71,6 +82,7 @@ struct ICH9LPCState { Notifier machine_ready; =20 qemu_irq gsi[IOAPIC_NUM_PINS]; + qemu_irq virt_smi[ICH9_VIRT_SMI_COUNT]; }; =20 #define ICH9_MASK(bit, ms_bit, ls_bit) \ diff --git a/include/hw/southbridge/ich9.h b/include/hw/southbridge/ich9.h index a8da4a8665..48a4212ed8 100644 --- a/include/hw/southbridge/ich9.h +++ b/include/hw/southbridge/ich9.h @@ -17,6 +17,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(ICH9State, ICH9_SOUTHBRIDGE) #define ICH9_PCIE_FUNC_MAX 6 =20 #define ICH9_GPIO_GSI "gsi" +#define ICH9_VIRT_SMI "x-virt-smi" =20 #define ICH9_LPC_SMI_NEGOTIATED_FEAT_PROP "x-smi-negotiated-features" =20 diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index 31ab0ae77b..77fe8932e8 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -50,6 +50,7 @@ #include "hw/ide/ahci-pci.h" #include "hw/intc/ioapic.h" #include "hw/southbridge/ich9.h" +#include "hw/isa/ich9_lpc.h" #include "qapi/error.h" #include "qemu/error-report.h" #include "sysemu/numa.h" @@ -58,6 +59,25 @@ #include "hw/i386/acpi-build.h" #include "target/i386/cpu.h" =20 +/* + * Kludge IRQ handler for ICH9 virtual SMI delivery. + * IRQ#0: broadcast + * IRQ#1: deliver to current CPU + */ +static void pc_q35_ich9_virt_smi(void *opaque, int irq, int level) +{ + assert(level); + if (irq) { + cpu_interrupt(current_cpu, CPU_INTERRUPT_SMI); + } else { + CPUState *cs; + + CPU_FOREACH(cs) { + cpu_interrupt(cs, CPU_INTERRUPT_SMI); + } + } +} + /* PC hardware initialisation */ static void pc_q35_init(MachineState *machine) { @@ -65,6 +85,7 @@ static void pc_q35_init(MachineState *machine) PCMachineClass *pcmc =3D PC_MACHINE_GET_CLASS(pcms); X86MachineState *x86ms =3D X86_MACHINE(machine); Object *phb; + qemu_irq *smi_irq; DeviceState *ich9; Object *lpc_obj; MemoryRegion *system_memory =3D get_system_memory(); @@ -160,6 +181,8 @@ static void pc_q35_init(MachineState *machine) =20 /* irq lines */ gsi_state =3D pc_gsi_create(&x86ms->gsi, true); + smi_irq =3D qemu_allocate_irqs(pc_q35_ich9_virt_smi, NULL, + ICH9_VIRT_SMI_COUNT); =20 ich9 =3D qdev_new(TYPE_ICH9_SOUTHBRIDGE); object_property_add_child(OBJECT(machine), "ich9", OBJECT(ich9)); @@ -168,6 +191,9 @@ static void pc_q35_init(MachineState *machine) for (i =3D 0; i < IOAPIC_NUM_PINS; i++) { qdev_connect_gpio_out_named(ich9, ICH9_GPIO_GSI, i, x86ms->gsi[i]); } + for (i =3D 0; i < ICH9_VIRT_SMI_COUNT; i++) { + qdev_connect_gpio_out_named(ich9, ICH9_VIRT_SMI, i, smi_irq[i]); + } qdev_prop_set_bit(ich9, "d2p-enabled", false); qdev_prop_set_bit(ich9, "smm-enabled", x86_machine_is_smm_enabled(x86m= s)); qdev_prop_set_bit(ich9, "sata-enabled", pcms->sata_enabled); diff --git a/hw/isa/ich9_lpc.c b/hw/isa/ich9_lpc.c index b1f41158c5..599cb0ee86 100644 --- a/hw/isa/ich9_lpc.c +++ b/hw/isa/ich9_lpc.c @@ -30,7 +30,6 @@ =20 #include "qemu/osdep.h" #include "qemu/log.h" -#include "cpu.h" #include "qapi/error.h" #include "qapi/visitor.h" #include "qemu/range.h" @@ -495,12 +494,9 @@ static void ich9_apm_ctrl_changed(uint32_t val, void *= arg) if (lpc->pm.smi_en & ICH9_PMIO_SMI_EN_APMC_EN) { if (lpc->smi_negotiated_features & (UINT64_C(1) << ICH9_LPC_SMI_F_BROADCAST_BIT)) { - CPUState *cs; - CPU_FOREACH(cs) { - cpu_interrupt(cs, CPU_INTERRUPT_SMI); - } + qemu_irq_raise(lpc->virt_smi[ICH9_VIRT_SMI_BROADCAST]); } else { - cpu_interrupt(current_cpu, CPU_INTERRUPT_SMI); + qemu_irq_raise(lpc->virt_smi[ICH9_VIRT_SMI_CURRENT]); } } } @@ -700,6 +696,8 @@ static void ich9_lpc_initfn(Object *obj) =20 qdev_init_gpio_out_named(DEVICE(lpc), lpc->gsi, ICH9_GPIO_GSI, IOAPIC_NUM_PINS); + qdev_init_gpio_out_named(DEVICE(lpc), lpc->virt_smi, + ICH9_VIRT_SMI, ARRAY_SIZE(lpc->virt_smi)); =20 object_property_add_uint8_ptr(obj, ACPI_PM_PROP_SCI_INT, &lpc->sci_gsi, OBJ_PROP_FLAG_READ); diff --git a/hw/southbridge/ich9.c b/hw/southbridge/ich9.c index 521925b462..d5e131cff3 100644 --- a/hw/southbridge/ich9.c +++ b/hw/southbridge/ich9.c @@ -64,6 +64,7 @@ static void ich9_init(Object *obj) =20 object_initialize_child(obj, "lpc", &s->lpc, TYPE_ICH9_LPC_DEVICE); qdev_pass_gpios(DEVICE(&s->lpc), DEVICE(s), ICH9_GPIO_GSI); + qdev_pass_gpios(DEVICE(&s->lpc), DEVICE(s), ICH9_VIRT_SMI); qdev_prop_set_int32(DEVICE(&s->lpc), "addr", ICH9_LPC_DEVFN); qdev_prop_set_bit(DEVICE(&s->lpc), "multifunction", true); object_property_add_alias(obj, "smm-enabled", --=20 2.41.0 From nobody Tue Nov 26 08:55:12 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 26 Feb 2024 08:49:48 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Thomas Huth , "Edgar E . Iglesias" , Anton Johansson , Mark Cave-Ayland , Peter Maydell , Zhao Liu , Eduardo Habkost , Marcel Apfelbaum , Igor Mammedov , Richard Henderson , Ani Sinha , Bernhard Beschow , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Paolo Bonzini , "Michael S. Tsirkin" , Laszlo Ersek , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [RFC PATCH 5/5] hw/isa: Build ich9_lpc.c once Date: Mon, 26 Feb 2024 17:49:12 +0100 Message-ID: <20240226164913.94077-6-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240226164913.94077-1-philmd@linaro.org> References: <20240226164913.94077-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=philmd@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1708966279635100001 ich9_lpc.c doesn't contain any target-specific calls, lets build it once. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/isa/meson.build | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/hw/isa/meson.build b/hw/isa/meson.build index 3b5504f78d..df58287d62 100644 --- a/hw/isa/meson.build +++ b/hw/isa/meson.build @@ -3,9 +3,8 @@ system_ss.add(when: 'CONFIG_FDC37M81X', if_true: files('fdc= 37m81x-superio.c')) system_ss.add(when: 'CONFIG_I82378', if_true: files('i82378.c')) system_ss.add(when: 'CONFIG_ISA_BUS', if_true: files('isa-bus.c')) system_ss.add(when: 'CONFIG_ISA_SUPERIO', if_true: files('isa-superio.c')) +system_ss.add(when: 'CONFIG_LPC_ICH9', if_true: files('ich9_lpc.c')) system_ss.add(when: 'CONFIG_PC87312', if_true: files('pc87312.c')) system_ss.add(when: 'CONFIG_PIIX', if_true: files('piix.c')) system_ss.add(when: 'CONFIG_SMC37C669', if_true: files('smc37c669-superio.= c')) system_ss.add(when: 'CONFIG_VT82C686', if_true: files('vt82c686.c')) - -specific_ss.add(when: 'CONFIG_LPC_ICH9', if_true: files('ich9_lpc.c')) --=20 2.41.0