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Tsirkin" , Igor Mammedov , Richard Henderson , Mark Cave-Ayland , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 12/15] hw/southbridge/ich9: Add the SMBus function Date: Mon, 26 Feb 2024 12:14:11 +0100 Message-ID: <20240226111416.39217-13-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240226111416.39217-1-philmd@linaro.org> References: <20240226111416.39217-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=philmd@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1708946175804100007 Instantiate TYPE_ICH9_SMB_DEVICE in TYPE_ICH9_SOUTHBRIDGE. Since the PC machines can disable SMBus (see the PC_MACHINE_SMBUS dynamic property), add the 'smbus-enabled' property to disable it. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/southbridge/ich9.h | 32 -------------------------------- hw/i2c/ich9_smbus.c | 29 ++++++++++++++++++++++++++++- hw/i386/pc_q35.c | 10 ++-------- hw/southbridge/ich9.c | 21 +++++++++++++++++++++ hw/southbridge/Kconfig | 1 + 5 files changed, 52 insertions(+), 41 deletions(-) diff --git a/include/hw/southbridge/ich9.h b/include/hw/southbridge/ich9.h index ac7f9f4ff5..d4b299bf3c 100644 --- a/include/hw/southbridge/ich9.h +++ b/include/hw/southbridge/ich9.h @@ -173,38 +173,6 @@ struct ICH9LPCState { #define ICH9_APM_ACPI_ENABLE 0x2 #define ICH9_APM_ACPI_DISABLE 0x3 =20 - -/* D31:F3 SMBus controller */ -#define TYPE_ICH9_SMB_DEVICE "ICH9-SMB" - -#define ICH9_A2_SMB_REVISION 0x02 -#define ICH9_SMB_PI 0x00 - -#define ICH9_SMB_SMBMBAR0 0x10 -#define ICH9_SMB_SMBMBAR1 0x14 -#define ICH9_SMB_SMBM_BAR 0 -#define ICH9_SMB_SMBM_SIZE (1 << 8) -#define ICH9_SMB_SMB_BASE 0x20 -#define ICH9_SMB_SMB_BASE_BAR 4 -#define ICH9_SMB_SMB_BASE_SIZE (1 << 5) -#define ICH9_SMB_HOSTC 0x40 -#define ICH9_SMB_HOSTC_SSRESET ((uint8_t)(1 << 3)) -#define ICH9_SMB_HOSTC_I2C_EN ((uint8_t)(1 << 2)) -#define ICH9_SMB_HOSTC_SMB_SMI_EN ((uint8_t)(1 << 1)) -#define ICH9_SMB_HOSTC_HST_EN ((uint8_t)(1 << 0)) - -/* D31:F3 SMBus I/O and memory mapped I/O registers */ -#define ICH9_SMB_DEV 31 -#define ICH9_SMB_FUNC 3 - -#define ICH9_SMB_HST_STS 0x00 -#define ICH9_SMB_HST_CNT 0x02 -#define ICH9_SMB_HST_CMD 0x03 -#define ICH9_SMB_XMIT_SLVA 0x04 -#define ICH9_SMB_HST_D0 0x05 -#define ICH9_SMB_HST_D1 0x06 -#define ICH9_SMB_HOST_BLOCK_DB 0x07 - #define ICH9_LPC_SMI_NEGOTIATED_FEAT_PROP "x-smi-negotiated-features" =20 /* bit positions used in fw_cfg SMI feature negotiation */ diff --git a/hw/i2c/ich9_smbus.c b/hw/i2c/ich9_smbus.c index 35f526d71c..1c3b9964de 100644 --- a/hw/i2c/ich9_smbus.c +++ b/hw/i2c/ich9_smbus.c @@ -26,10 +26,37 @@ #include "migration/vmstate.h" #include "qemu/module.h" =20 -#include "hw/southbridge/ich9.h" #include "qom/object.h" #include "hw/acpi/acpi_aml_interface.h" =20 +/* D31:F3 SMBus controller */ + +#define ICH9_A2_SMB_REVISION 0x02 +#define ICH9_SMB_PI 0x00 + +#define ICH9_SMB_SMBMBAR0 0x10 +#define ICH9_SMB_SMBMBAR1 0x14 +#define ICH9_SMB_SMBM_BAR 0 +#define ICH9_SMB_SMBM_SIZE (1 << 8) +#define ICH9_SMB_SMB_BASE 0x20 +#define ICH9_SMB_SMB_BASE_BAR 4 +#define ICH9_SMB_SMB_BASE_SIZE (1 << 5) +#define ICH9_SMB_HOSTC 0x40 +#define ICH9_SMB_HOSTC_SSRESET ((uint8_t)(1 << 3)) +#define ICH9_SMB_HOSTC_I2C_EN ((uint8_t)(1 << 2)) +#define ICH9_SMB_HOSTC_SMB_SMI_EN ((uint8_t)(1 << 1)) +#define ICH9_SMB_HOSTC_HST_EN ((uint8_t)(1 << 0)) + +/* D31:F3 SMBus I/O and memory mapped I/O registers */ + +#define ICH9_SMB_HST_STS 0x00 +#define ICH9_SMB_HST_CNT 0x02 +#define ICH9_SMB_HST_CMD 0x03 +#define ICH9_SMB_XMIT_SLVA 0x04 +#define ICH9_SMB_HST_D0 0x05 +#define ICH9_SMB_HST_D1 0x06 +#define ICH9_SMB_HOST_BLOCK_DB 0x07 + static bool ich9_vmstate_need_smbus(void *opaque, int version_id) { return pm_smbus_vmstate_needed(); diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index 6903719b97..0ff94b7afd 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -224,6 +224,7 @@ static void pc_q35_init(MachineState *machine) OBJECT(pcms->pcibus), &error_abort); qdev_prop_set_bit(ich9, "d2p-enabled", false); qdev_prop_set_bit(ich9, "sata-enabled", pcms->sata_enabled); + qdev_prop_set_bit(ich9, "smbus-enabled", pcms->smbus_enabled); qdev_realize_and_unref(ich9, NULL, &error_fatal); =20 /* create ISA bus */ @@ -294,15 +295,8 @@ static void pc_q35_init(MachineState *machine) } =20 if (pcms->smbus_enabled) { - PCIDevice *smb; - + pcms->smbus =3D I2C_BUS(qdev_get_child_bus(ich9, "i2c")); /* TODO: Populate SPD eeprom data. */ - smb =3D pci_create_simple_multifunction(pcms->pcibus, - PCI_DEVFN(ICH9_SMB_DEV, - ICH9_SMB_FUNC), - TYPE_ICH9_SMB_DEVICE); - pcms->smbus =3D I2C_BUS(qdev_get_child_bus(DEVICE(smb), "i2c")); - smbus_eeprom_init(pcms->smbus, 8, NULL, 0); } =20 diff --git a/hw/southbridge/ich9.c b/hw/southbridge/ich9.c index 37255bb941..413e9187e4 100644 --- a/hw/southbridge/ich9.c +++ b/hw/southbridge/ich9.c @@ -15,9 +15,11 @@ #include "hw/pci-bridge/ich9_dmi.h" #include "hw/ide/ahci-pci.h" #include "hw/ide/ide-dev.h" +#include "hw/i2c/ich9_smbus.h" =20 #define ICH9_D2P_DEVFN PCI_DEVFN(30, 0) #define ICH9_SATA1_DEVFN PCI_DEVFN(31, 2) +#define ICH9_SMB_DEVFN PCI_DEVFN(31, 3) =20 #define SATA_PORTS 6 =20 @@ -26,10 +28,12 @@ struct ICH9State { =20 I82801b11Bridge d2p; AHCIPCIState sata0; + ICH9SMBState smb; =20 PCIBus *pci_bus; bool d2p_enabled; bool sata_enabled; + bool smbus_enabled; }; =20 static Property ich9_props[] =3D { @@ -37,6 +41,7 @@ static Property ich9_props[] =3D { TYPE_PCIE_BUS, PCIBus *), DEFINE_PROP_BOOL("d2p-enabled", ICH9State, d2p_enabled, true), DEFINE_PROP_BOOL("sata-enabled", ICH9State, sata_enabled, true), + DEFINE_PROP_BOOL("smbus-enabled", ICH9State, smbus_enabled, true), DEFINE_PROP_END_OF_LIST(), }; =20 @@ -83,6 +88,18 @@ static bool ich9_realize_sata(ICH9State *s, Error **errp) return true; } =20 +static bool ich9_realize_smbus(ICH9State *s, Error **errp) +{ + object_initialize_child(OBJECT(s), "smb", &s->smb, TYPE_ICH9_SMB_DEVIC= E); + qdev_prop_set_int32(DEVICE(&s->smb), "addr", ICH9_SMB_DEVFN); + if (!qdev_realize(DEVICE(&s->smb), BUS(s->pci_bus), errp)) { + return false; + } + object_property_add_alias(OBJECT(s), "i2c", OBJECT(&s->smb), "i2c"); + + return true; +} + static void ich9_realize(DeviceState *dev, Error **errp) { ICH9State *s =3D ICH9_SOUTHBRIDGE(dev); @@ -99,6 +116,10 @@ static void ich9_realize(DeviceState *dev, Error **errp) if (s->sata_enabled && !ich9_realize_sata(s, errp)) { return; } + + if (s->smbus_enabled && !ich9_realize_smbus(s, errp)) { + return; + } } =20 static void ich9_class_init(ObjectClass *klass, void *data) diff --git a/hw/southbridge/Kconfig b/hw/southbridge/Kconfig index f806033d48..03e89a55d1 100644 --- a/hw/southbridge/Kconfig +++ b/hw/southbridge/Kconfig @@ -5,3 +5,4 @@ config ICH9 depends on PCI_EXPRESS imply I82801B11 select AHCI_ICH9 + select ACPI_ICH9 --=20 2.41.0