From nobody Thu Nov 14 17:55:32 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1708946277; cv=none; d=zohomail.com; s=zohoarc; b=fQuhCAoLq0kY95Q/T9C8ACKG/gzyuILmjHXExgP+4XZGNatcicYXJqL6NBuNadRDTUPQzNR5JstXBfZbrInFXHVb92NjpRGvzAAz9tyZrULr+ww2B5DRMnuQ6hKhNa2RrNUwQGdD8yPt1oUCmdzJXL9W6vyz/CsCzbsfqxJkCh8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1708946277; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=AOAgdiTLrHitfNCm+AG8p3RfvQWogq//ul3+PzccJzg=; b=bod4D8jyiplGNrTPoMpt7hKURW00TNfhWsNJH4Pi/PGCYW3F3G2AFq8gohAoQb5fe+77lwgubZ3AukWkH6iIa/kW/8XsqNLsNzHQJibl9QOQ3VTuTmLM1LkR3WAA4W2AfQ3qRyz8h34F/yGAdLw2tmdl6OlalVlOUlSP7o/tPB4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1708946277231530.5238214575153; Mon, 26 Feb 2024 03:17:57 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1reYxN-00023j-1e; Mon, 26 Feb 2024 06:15:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1reYx5-0001Ov-7F for qemu-devel@nongnu.org; Mon, 26 Feb 2024 06:15:25 -0500 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1reYx3-0000IK-CG for qemu-devel@nongnu.org; Mon, 26 Feb 2024 06:15:18 -0500 Received: by mail-wm1-x32b.google.com with SMTP id 5b1f17b1804b1-412a5ed5a25so3216165e9.0 for ; Mon, 26 Feb 2024 03:15:16 -0800 (PST) Received: from m1x-phil.lan ([176.176.164.69]) by smtp.gmail.com with ESMTPSA id u16-20020a5d6ad0000000b0033b6e26f0f9sm7928127wrw.42.2024.02.26.03.15.13 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 26 Feb 2024 03:15:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1708946115; x=1709550915; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=AOAgdiTLrHitfNCm+AG8p3RfvQWogq//ul3+PzccJzg=; b=k3p17Dp6Tno6Y5i0U18wc8IZMuflH6pF7JZ185xbiAjvHmGmCGtK2Qjnsxghe4Kt3m BJ5m6+o9xfvEewYLoRSTPBPrHObAnMra/gOnZEt7ThU5bYAyw/w7CR+zrWtIQVQVhoP6 i0YNlXxb3XVcc79zc2LC7EhURXbsTpGINLjRIeVVitPbBH18IyJwD+vlRqes/TvH8TPT BJWly7aZw94frmhj9sgib8hQYE9dXypW3jYe0U2IL1JE2Nf4QCpWOanrKPAPC3QHZE+T Q42gR9D3gzsYRYVVVo41V8nNh3GewRO90/VVwp4UuofGVzjMwEJK7HHZFk6DKP2e0bfC f0mQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1708946115; x=1709550915; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=AOAgdiTLrHitfNCm+AG8p3RfvQWogq//ul3+PzccJzg=; b=w/UGqiqa9iJDD7UfuJ++NEoz5FLTpQVDNjFb4yLE+UbV5y83FujPkOZ+hB3vdMJAZp k/Mr524b8L3Dc7vLnVSVB/urTXeFrwTue1fE6kxD7i3Bt0dlIZe5UA0v0B5kgaGaX9YK ZH/me1ZSI7mzfGAf/MbOd0JVNMhBKsbEEjcdrInLRHnDjNwQWXPFe/rAlihfBjKVpqas LHEwPdnsy9CRRC07aedq9/6jb29Fmn3cZGRj3jCSCgsRP/zPPtlWBrn7dM34rTMozgdL 1kpleemFnq1Ys0ILoj5TCbYpHTpCUChy+HQSzuGcA9oQ96qZYJTA3EKlkRYylaQ8S81s p3Xg== X-Gm-Message-State: AOJu0YzsWDUw1hSIo82WGiG1JJKoWb9U8iv+JIEJ8jLCa3LZVh/gf5EL VV9xlDz2W5mtZBQzoD35HlLZhjwn5MQSadWFHJZmtv7vwDRJZmPQO4x10xrNyXRracr0NJczpbE C X-Google-Smtp-Source: AGHT+IFGGyZ8M0LB5lryrip/wWQ/od4AVBvJPxOp2mEf4kZe+Kqq0idqMI32gDGdRm7DU0zoR7m6tA== X-Received: by 2002:a05:600c:190c:b0:412:a215:e635 with SMTP id j12-20020a05600c190c00b00412a215e635mr2246078wmq.3.1708946115099; Mon, 26 Feb 2024 03:15:15 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Bernhard Beschow Cc: Laurent Vivier , Thomas Huth , BALATON Zoltan , Ani Sinha , qemu-block@nongnu.org, Marcel Apfelbaum , Eduardo Habkost , John Snow , Paolo Bonzini , "Michael S. Tsirkin" , Igor Mammedov , Richard Henderson , Mark Cave-Ayland , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 09/15] hw/southbridge/ich9: Introduce TYPE_ICH9_SOUTHBRIDGE stub Date: Mon, 26 Feb 2024 12:14:08 +0100 Message-ID: <20240226111416.39217-10-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240226111416.39217-1-philmd@linaro.org> References: <20240226111416.39217-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=philmd@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1708946278091100001 Start the TYPE_ICH9_SOUTHBRIDGE stub, a kind of QOM container which will contain all the ICH9 parts. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- MAINTAINERS | 1 + include/hw/southbridge/ich9.h | 3 ++ hw/i386/pc_q35.c | 7 ++++ hw/southbridge/ich9.c | 61 +++++++++++++++++++++++++++++++++++ hw/Kconfig | 1 + hw/i386/Kconfig | 1 + hw/meson.build | 1 + hw/southbridge/Kconfig | 5 +++ hw/southbridge/meson.build | 3 ++ 9 files changed, 83 insertions(+) create mode 100644 hw/southbridge/ich9.c create mode 100644 hw/southbridge/Kconfig create mode 100644 hw/southbridge/meson.build diff --git a/MAINTAINERS b/MAINTAINERS index 52282c680e..4576339053 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2616,6 +2616,7 @@ S: Supported F: hw/acpi/ich9*.c F: hw/i2c/smbus_ich9.c F: hw/isa/lpc_ich9.c +F: hw/southbridge/ich9.c F: include/hw/acpi/ich9*.h F: include/hw/i2c/ich9_smbus.h F: include/hw/pci-bridge/ich9_dmi.h diff --git a/include/hw/southbridge/ich9.h b/include/hw/southbridge/ich9.h index b2abf483e0..162ae3baa1 100644 --- a/include/hw/southbridge/ich9.h +++ b/include/hw/southbridge/ich9.h @@ -11,6 +11,9 @@ #include "qemu/notify.h" #include "qom/object.h" =20 +#define TYPE_ICH9_SOUTHBRIDGE "ICH9-southbridge" +OBJECT_DECLARE_SIMPLE_TYPE(ICH9State, ICH9_SOUTHBRIDGE) + #define ICH9_CC_SIZE (16 * 1024) /* 16KB. Chipset configuration registers = */ =20 #define TYPE_ICH9_LPC_DEVICE "ICH9-LPC" diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index dcad6000d9..8c8a2f65b8 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -123,6 +123,7 @@ static void pc_q35_init(MachineState *machine) PCMachineClass *pcmc =3D PC_MACHINE_GET_CLASS(pcms); X86MachineState *x86ms =3D X86_MACHINE(machine); Object *phb; + DeviceState *ich9; PCIDevice *lpc; Object *lpc_obj; DeviceState *lpc_dev; @@ -221,6 +222,12 @@ static void pc_q35_init(MachineState *machine) /* irq lines */ gsi_state =3D pc_gsi_create(&x86ms->gsi, true); =20 + ich9 =3D qdev_new(TYPE_ICH9_SOUTHBRIDGE); + object_property_add_child(OBJECT(machine), "ich9", OBJECT(ich9)); + object_property_set_link(OBJECT(ich9), "mch-pcie-bus", + OBJECT(pcms->pcibus), &error_abort); + qdev_realize_and_unref(ich9, NULL, &error_fatal); + /* create ISA bus */ lpc =3D pci_new_multifunction(PCI_DEVFN(ICH9_LPC_DEV, ICH9_LPC_FUNC), TYPE_ICH9_LPC_DEVICE); diff --git a/hw/southbridge/ich9.c b/hw/southbridge/ich9.c new file mode 100644 index 0000000000..f3a9b932ab --- /dev/null +++ b/hw/southbridge/ich9.c @@ -0,0 +1,61 @@ +/* + * QEMU Intel ICH9 south bridge emulation + * + * SPDX-FileCopyrightText: 2024 Linaro Ltd + * SPDX-FileContributor: Philippe Mathieu-Daud=C3=A9 + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "hw/qdev-properties.h" +#include "hw/southbridge/ich9.h" +#include "hw/pci/pci.h" + +struct ICH9State { + DeviceState parent_obj; + + PCIBus *pci_bus; +}; + +static Property ich9_props[] =3D { + DEFINE_PROP_LINK("mch-pcie-bus", ICH9State, pci_bus, + TYPE_PCIE_BUS, PCIBus *), + DEFINE_PROP_END_OF_LIST(), +}; + +static void ich9_init(Object *obj) +{ +} + +static void ich9_realize(DeviceState *dev, Error **errp) +{ + ICH9State *s =3D ICH9_SOUTHBRIDGE(dev); + + if (!s->pci_bus) { + error_setg(errp, "'pcie-bus' property must be set"); + return; + } +} + +static void ich9_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->realize =3D ich9_realize; + device_class_set_props(dc, ich9_props); + set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); +} + +static const TypeInfo ich9_types[] =3D { + { + .name =3D TYPE_ICH9_SOUTHBRIDGE, + .parent =3D TYPE_DEVICE, + .instance_size =3D sizeof(ICH9State), + .instance_init =3D ich9_init, + .class_init =3D ich9_class_init, + } +}; + +DEFINE_TYPES(ich9_types) diff --git a/hw/Kconfig b/hw/Kconfig index 2c00936c28..6584f2f72a 100644 --- a/hw/Kconfig +++ b/hw/Kconfig @@ -36,6 +36,7 @@ source scsi/Kconfig source sd/Kconfig source sensor/Kconfig source smbios/Kconfig +source southbridge/Kconfig source ssi/Kconfig source timer/Kconfig source tpm/Kconfig diff --git a/hw/i386/Kconfig b/hw/i386/Kconfig index a1846be6f7..d21638f4f9 100644 --- a/hw/i386/Kconfig +++ b/hw/i386/Kconfig @@ -99,6 +99,7 @@ config Q35 select PC_PCI select PC_ACPI select PCI_EXPRESS_Q35 + select ICH9 select LPC_ICH9 select AHCI_ICH9 select DIMM diff --git a/hw/meson.build b/hw/meson.build index 463d702683..7f9ae8659a 100644 --- a/hw/meson.build +++ b/hw/meson.build @@ -33,6 +33,7 @@ subdir('rtc') subdir('scsi') subdir('sd') subdir('sensor') +subdir('southbridge') subdir('smbios') subdir('ssi') subdir('timer') diff --git a/hw/southbridge/Kconfig b/hw/southbridge/Kconfig new file mode 100644 index 0000000000..852b7f346f --- /dev/null +++ b/hw/southbridge/Kconfig @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +config ICH9 + bool + depends on PCI_EXPRESS diff --git a/hw/southbridge/meson.build b/hw/southbridge/meson.build new file mode 100644 index 0000000000..70c1fa3cb2 --- /dev/null +++ b/hw/southbridge/meson.build @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +system_ss.add(when: 'CONFIG_ICH9', if_true: files('ich9.c')) --=20 2.41.0