From nobody Tue Nov 26 09:27:14 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1708766774; cv=none; d=zohomail.com; s=zohoarc; b=ioGN8niQN+MnoIZN4QRC4GvvRBPyP8pUc100NNFJ/tVAbsH6aT1YFsOv092jn2M8+xp4+FicSS75zTIetvY2H1oPSb1hx/DAFhH65/viZe/aL29QSeL1a+yR+kaPTSDVE/ap0Rt9GNe8YyDuFefNymNmDt10GG8yptHs1gJD/rM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1708766774; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=WM47wdy4Cb/mp1eobpOxgb3rFoDQbhprTWLPDZcJhAo=; b=a20cHU3RUmdL87BYV2c+lxjDBIlo4VIC/N/FRWxyGrvOXlqcPiWlcFraNwLghLqg08w/ppilhTaRhenmRJhFuWZIHCHI3tb8+wEgdujYAM5XXK50ALUTdFOKuEDDMgFttK/wQy4ximGaN3LJ56eGeKmV3q+qMz7Gk5Sbcd5z6qg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1708766774967232.66666249928085; Sat, 24 Feb 2024 01:26:14 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rdoH7-0006NN-Iq; Sat, 24 Feb 2024 04:24:55 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rdoH6-0006Mx-Ob for qemu-devel@nongnu.org; Sat, 24 Feb 2024 04:24:52 -0500 Received: from mail-pg1-x52e.google.com ([2607:f8b0:4864:20::52e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rdoH4-0002OO-4A for qemu-devel@nongnu.org; Sat, 24 Feb 2024 04:24:52 -0500 Received: by mail-pg1-x52e.google.com with SMTP id 41be03b00d2f7-5d8b887bb0cso994374a12.2 for ; Sat, 24 Feb 2024 01:24:49 -0800 (PST) Received: from localhost ([157.82.203.206]) by smtp.gmail.com with UTF8SMTPSA id fx3-20020a056a00820300b006e47e57d976sm745892pfb.166.2024.02.24.01.24.45 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 24 Feb 2024 01:24:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=daynix-com.20230601.gappssmtp.com; s=20230601; t=1708766689; x=1709371489; darn=nongnu.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=WM47wdy4Cb/mp1eobpOxgb3rFoDQbhprTWLPDZcJhAo=; b=Jw5VziREcZXm+KaeC7Nz/u4JKI8auv6uWSEVcFwK4zFd7Mm1K5/WRPBLx5Pcs7KACJ tOu8sGkBZuZmvgZ4wl4Iy7xrhQGymoYLpdTlLqr+yyxj6UR8hLbbund0sdac7oIjAuOH 2lkmE7veBV5kR8pbfiJdygDO5y4azYzmpmZfLRAhn6OS1CjYdtH1NLqaWHLUdLmTXjWw t2DhWSf3NT4EJJfjVb+iWUIAFIV275h31y5yHiWXhzTgYSTBqj0LIFucLkyD3QRlw05O A7cDBpheOCVu3IzRBawf5ZSisaSVxKLjqVJRpl8mWufUK6XLfmUmz/uAbTNTDF3kfE1M 6OUw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1708766689; x=1709371489; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WM47wdy4Cb/mp1eobpOxgb3rFoDQbhprTWLPDZcJhAo=; b=wmrsQScFZO+TCGtKD/itlvHuEyVn+LNbSJ7SV729WzHg5viUWe9RZUBzNaEUBisVeC h6+U/3dHOpJlnzrU+/mMi6mQcvj0kIjGroiLVgn7KuukYG4CVy/sKL5XnBeBIkIosy1c MUYF4laEovCsvYLDQaVO3PeS9HfNfMFq1zSWiuPcd1fFS5DxQU78hM34mtf7sNxzP5jG UGC6o6Z0KglSieZnoRz0sg59ghh/bxaZDRzLtG8+Cd9DjyvmHEc6t3Cfw8BKEy/cyOXA mfrGbDrLdZMaNG7v8URfhIzsj0t8UdsbV7WUnmKIDBuGU/mbSCGtAcYHzYTtDIj6RL0J GbOg== X-Gm-Message-State: AOJu0YzYPYAIuegVBLMw/bikxuQ4h/D9pySJmpXIoVxKXbMwdXTQN/Ig /tnpQ4I7qMNXgsZpwFyjwdm8dgzY3csmfUp9BqGUpor9oEY75OMLfxdwlrbkUjo= X-Google-Smtp-Source: AGHT+IE0yG8WWCvGvj47WhDiA+0B4UNhyixLdJAXLuDFT+Ng66ZIyT7oP0LQaIceIuM1RtGwsf3BfQ== X-Received: by 2002:a05:6a20:e507:b0:1a0:cce6:d526 with SMTP id ne7-20020a056a20e50700b001a0cce6d526mr1998665pzb.41.1708766688891; Sat, 24 Feb 2024 01:24:48 -0800 (PST) From: Akihiko Odaki Date: Sat, 24 Feb 2024 18:24:33 +0900 Subject: [PATCH v7 01/16] hw/nvme: Use pcie_sriov_num_vfs() MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240224-reuse-v7-1-29c14bcb952e@daynix.com> References: <20240224-reuse-v7-0-29c14bcb952e@daynix.com> In-Reply-To: <20240224-reuse-v7-0-29c14bcb952e@daynix.com> To: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" , Marcel Apfelbaum , Alex Williamson , =?utf-8?q?C=C3=A9dric_Le_Goater?= , Paolo Bonzini , =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , Eduardo Habkost , Sriram Yagnaraman , Jason Wang , Keith Busch , Klaus Jensen Cc: qemu-devel@nongnu.org, qemu-block@nongnu.org, Akihiko Odaki , qemu-stable@nongnu.org X-Mailer: b4 0.12.3 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=2607:f8b0:4864:20::52e; envelope-from=akihiko.odaki@daynix.com; helo=mail-pg1-x52e.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @daynix-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1708766775478100003 nvme_sriov_pre_write_ctrl() used to directly inspect SR-IOV configurations to know the number of VFs being disabled due to SR-IOV configuration writes, but the logic was flawed and resulted in out-of-bound memory access. It assumed PCI_SRIOV_NUM_VF always has the number of currently enabled VFs, but it actually doesn't in the following cases: - PCI_SRIOV_NUM_VF has been set but PCI_SRIOV_CTRL_VFE has never been. - PCI_SRIOV_NUM_VF was written after PCI_SRIOV_CTRL_VFE was set. - VFs were only partially enabled because of realization failure. It is a responsibility of pcie_sriov to interpret SR-IOV configurations and pcie_sriov does it correctly, so use pcie_sriov_num_vfs(), which it provides, to get the number of enabled VFs before and after SR-IOV configuration writes. Cc: qemu-stable@nongnu.org Fixes: CVE-2024-26328 Fixes: 11871f53ef8e ("hw/nvme: Add support for the Virtualization Managemen= t command") Suggested-by: Michael S. Tsirkin Signed-off-by: Akihiko Odaki --- hw/nvme/ctrl.c | 26 ++++++++------------------ 1 file changed, 8 insertions(+), 18 deletions(-) diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c index f026245d1e9e..7a56e7b79b4d 100644 --- a/hw/nvme/ctrl.c +++ b/hw/nvme/ctrl.c @@ -8466,36 +8466,26 @@ static void nvme_pci_reset(DeviceState *qdev) nvme_ctrl_reset(n, NVME_RESET_FUNCTION); } =20 -static void nvme_sriov_pre_write_ctrl(PCIDevice *dev, uint32_t address, - uint32_t val, int len) +static void nvme_sriov_post_write_config(PCIDevice *dev, uint16_t old_num_= vfs) { NvmeCtrl *n =3D NVME(dev); NvmeSecCtrlEntry *sctrl; - uint16_t sriov_cap =3D dev->exp.sriov_cap; - uint32_t off =3D address - sriov_cap; - int i, num_vfs; + int i; =20 - if (!sriov_cap) { - return; - } - - if (range_covers_byte(off, len, PCI_SRIOV_CTRL)) { - if (!(val & PCI_SRIOV_CTRL_VFE)) { - num_vfs =3D pci_get_word(dev->config + sriov_cap + PCI_SRIOV_N= UM_VF); - for (i =3D 0; i < num_vfs; i++) { - sctrl =3D &n->sec_ctrl_list.sec[i]; - nvme_virt_set_state(n, le16_to_cpu(sctrl->scid), false); - } - } + for (i =3D pcie_sriov_num_vfs(dev); i < old_num_vfs; i++) { + sctrl =3D &n->sec_ctrl_list.sec[i]; + nvme_virt_set_state(n, le16_to_cpu(sctrl->scid), false); } } =20 static void nvme_pci_write_config(PCIDevice *dev, uint32_t address, uint32_t val, int len) { - nvme_sriov_pre_write_ctrl(dev, address, val, len); + uint16_t old_num_vfs =3D pcie_sriov_num_vfs(dev); + pci_default_write_config(dev, address, val, len); pcie_cap_flr_write_config(dev, address, val, len); + nvme_sriov_post_write_config(dev, old_num_vfs); } =20 static const VMStateDescription nvme_vmstate =3D { --=20 2.43.2 From nobody Tue Nov 26 09:27:14 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1708766788; cv=none; d=zohomail.com; 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bh=XAlWXKGj/Qs8kksBVXE9dWWgaRg5MiFxbRpTNiPgudE=; b=nNgYY/vuek4+L1pk6BHWG4jMLGZ3RmvPuQotDQPEmNoZLFtRavSJw32cfINKEmKT0L 5pO4T5NL0+8I2q4FZ296BQgy7iXtF1NqkIwgLIUPqya3peEDYZ5hnpKfpFbVEt9eGb7S mH3PnA0pjUCFIrFkqP8dFd1fVdvS5P2ttAODJZMq2glPfPKQIpSYCkSAGZx7DhstsL+C AZxflTbcYZ1V6GApg4MAwdtExYMFtNaeF3Nj21lG5rLFUw/83aTcGT39dLnOh0jtp9G7 k3xAJ+hLdPdEnMeomNqstVyzU4WrNr/ZMwPfGNnHziNrOIMezO/Abdg+waU7eNc/H2N6 IGQw== X-Gm-Message-State: AOJu0YwadBSrLF5TmIGjpqwf4gDTNL2CxV+nHdYceQYSflTELcegdNKy NFdEOjem/qv3zyHIuJkLGUqdtf6UpbE6B4s2mb1L1vU5iCFWGraqKxsIf/rcDtc= X-Google-Smtp-Source: AGHT+IGbRtdYYQG2GEF/VDgDfeiO1qHT4p/K4DIg34O/4elLXo34dw2jYOWxcaNRTfgMOOuDSgtBMg== X-Received: by 2002:a17:902:bb16:b0:1dc:688e:188a with SMTP id im22-20020a170902bb1600b001dc688e188amr1926990plb.21.1708766693653; Sat, 24 Feb 2024 01:24:53 -0800 (PST) From: Akihiko Odaki Date: Sat, 24 Feb 2024 18:24:34 +0900 Subject: [PATCH v7 02/16] pcie_sriov: Validate NumVFs MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240224-reuse-v7-2-29c14bcb952e@daynix.com> References: <20240224-reuse-v7-0-29c14bcb952e@daynix.com> In-Reply-To: <20240224-reuse-v7-0-29c14bcb952e@daynix.com> To: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" , Marcel Apfelbaum , Alex Williamson , =?utf-8?q?C=C3=A9dric_Le_Goater?= , Paolo Bonzini , =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , Eduardo Habkost , Sriram Yagnaraman , Jason Wang , Keith Busch , Klaus Jensen Cc: qemu-devel@nongnu.org, qemu-block@nongnu.org, Akihiko Odaki , qemu-stable@nongnu.org X-Mailer: b4 0.12.3 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=2607:f8b0:4864:20::62c; envelope-from=akihiko.odaki@daynix.com; helo=mail-pl1-x62c.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @daynix-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1708766789272100015 The guest may write NumVFs greater than TotalVFs and that can lead to buffer overflow in VF implementations. Cc: qemu-stable@nongnu.org Fixes: CVE-2024-26327 Fixes: 7c0fa8dff811 ("pcie: Add support for Single Root I/O Virtualization = (SR/IOV)") Signed-off-by: Akihiko Odaki --- hw/pci/pcie_sriov.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/hw/pci/pcie_sriov.c b/hw/pci/pcie_sriov.c index a1fe65f5d801..da209b7f47fd 100644 --- a/hw/pci/pcie_sriov.c +++ b/hw/pci/pcie_sriov.c @@ -176,6 +176,9 @@ static void register_vfs(PCIDevice *dev) =20 assert(sriov_cap > 0); num_vfs =3D pci_get_word(dev->config + sriov_cap + PCI_SRIOV_NUM_VF); + if (num_vfs > pci_get_word(dev->config + sriov_cap + PCI_SRIOV_TOTAL_V= F)) { + return; + } =20 dev->exp.sriov_pf.vf =3D g_new(PCIDevice *, num_vfs); =20 --=20 2.43.2 From nobody Tue Nov 26 09:27:14 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; 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Tsirkin" , Marcel Apfelbaum , Alex Williamson , =?utf-8?q?C=C3=A9dric_Le_Goater?= , Paolo Bonzini , =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , Eduardo Habkost , Sriram Yagnaraman , Jason Wang , Keith Busch , Klaus Jensen Cc: qemu-devel@nongnu.org, qemu-block@nongnu.org, Akihiko Odaki X-Mailer: b4 0.12.3 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=2607:f8b0:4864:20::c2d; envelope-from=akihiko.odaki@daynix.com; helo=mail-oo1-xc2d.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @daynix-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1708766787384100008 pcie_sriov_pf_disable_vfs() is called when resetting the PF, but it only disables VFs and does not reset SR-IOV extended capability, leaking the state and making the VF Enable register inconsistent with the actual state. Replace pcie_sriov_pf_disable_vfs() with pcie_sriov_pf_reset(), which does not only disable VFs but also resets the capability. Signed-off-by: Akihiko Odaki --- include/hw/pci/pcie_sriov.h | 4 ++-- hw/net/igb.c | 2 +- hw/nvme/ctrl.c | 2 +- hw/pci/pcie_sriov.c | 26 ++++++++++++++++++-------- 4 files changed, 22 insertions(+), 12 deletions(-) diff --git a/include/hw/pci/pcie_sriov.h b/include/hw/pci/pcie_sriov.h index 095fb0c9edf9..b77eb7bf58ac 100644 --- a/include/hw/pci/pcie_sriov.h +++ b/include/hw/pci/pcie_sriov.h @@ -58,8 +58,8 @@ void pcie_sriov_pf_add_sup_pgsize(PCIDevice *dev, uint16_= t opt_sup_pgsize); void pcie_sriov_config_write(PCIDevice *dev, uint32_t address, uint32_t val, int len); =20 -/* Reset SR/IOV VF Enable bit to unregister all VFs */ -void pcie_sriov_pf_disable_vfs(PCIDevice *dev); +/* Reset SR/IOV */ +void pcie_sriov_pf_reset(PCIDevice *dev); =20 /* Get logical VF number of a VF - only valid for VFs */ uint16_t pcie_sriov_vf_number(PCIDevice *dev); diff --git a/hw/net/igb.c b/hw/net/igb.c index 0b5c31a58bba..9345506f81ec 100644 --- a/hw/net/igb.c +++ b/hw/net/igb.c @@ -493,7 +493,7 @@ static void igb_qdev_reset_hold(Object *obj) =20 trace_e1000e_cb_qdev_reset_hold(); =20 - pcie_sriov_pf_disable_vfs(d); + pcie_sriov_pf_reset(d); igb_core_reset(&s->core); } =20 diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c index 7a56e7b79b4d..7c0d3f108724 100644 --- a/hw/nvme/ctrl.c +++ b/hw/nvme/ctrl.c @@ -7116,7 +7116,7 @@ static void nvme_ctrl_reset(NvmeCtrl *n, NvmeResetTyp= e rst) } =20 if (rst !=3D NVME_RESET_CONTROLLER) { - pcie_sriov_pf_disable_vfs(pci_dev); + pcie_sriov_pf_reset(pci_dev); } } =20 diff --git a/hw/pci/pcie_sriov.c b/hw/pci/pcie_sriov.c index da209b7f47fd..51b66d1bb342 100644 --- a/hw/pci/pcie_sriov.c +++ b/hw/pci/pcie_sriov.c @@ -249,16 +249,26 @@ void pcie_sriov_config_write(PCIDevice *dev, uint32_t= address, } =20 =20 -/* Reset SR/IOV VF Enable bit to trigger an unregister of all VFs */ -void pcie_sriov_pf_disable_vfs(PCIDevice *dev) +/* Reset SR/IOV */ +void pcie_sriov_pf_reset(PCIDevice *dev) { uint16_t sriov_cap =3D dev->exp.sriov_cap; - if (sriov_cap) { - uint32_t val =3D pci_get_byte(dev->config + sriov_cap + PCI_SRIOV_= CTRL); - if (val & PCI_SRIOV_CTRL_VFE) { - val &=3D ~PCI_SRIOV_CTRL_VFE; - pcie_sriov_config_write(dev, sriov_cap + PCI_SRIOV_CTRL, val, = 1); - } + if (!sriov_cap) { + return; + } + + pci_set_word(dev->config + sriov_cap + PCI_SRIOV_CTRL, 0); + unregister_vfs(dev); + + /* + * Default is to use 4K pages, software can modify it + * to any of the supported bits + */ + pci_set_word(dev->config + sriov_cap + PCI_SRIOV_SYS_PGSIZE, 0x1); + + for (uint16_t i =3D 0; i < PCI_NUM_REGIONS; i++) { + pci_set_quad(dev->config + sriov_cap + PCI_SRIOV_BAR + i * 4, + dev->exp.sriov_pf.vf_bar_type[i]); } } =20 --=20 2.43.2 From nobody Tue Nov 26 09:27:14 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1708766794; cv=none; d=zohomail.com; s=zohoarc; b=H6n7HTwZNuvjw8Cm6pCNX/vDDwaNQjTdg7zorZlfKFjWPiGtkbvfosXo252wl/XGgCRZF++4KF+jY36Y3eOHBkqY5zDl3v2D1qM5QwdALHy3Bp02zk7EnyrKV7DAoss1YrtS0vBkOWl9XiPopCDN2kuyLVCLTduCkLEa7hVLPQU= ARC-Message-Signature: i=1; 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Sat, 24 Feb 2024 01:25:03 -0800 (PST) From: Akihiko Odaki Date: Sat, 24 Feb 2024 18:24:36 +0900 Subject: [PATCH v7 04/16] pcie_sriov: Do not reset NumVFs after disabling VFs MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240224-reuse-v7-4-29c14bcb952e@daynix.com> References: <20240224-reuse-v7-0-29c14bcb952e@daynix.com> In-Reply-To: <20240224-reuse-v7-0-29c14bcb952e@daynix.com> To: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" , Marcel Apfelbaum , Alex Williamson , =?utf-8?q?C=C3=A9dric_Le_Goater?= , Paolo Bonzini , =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , Eduardo Habkost , Sriram Yagnaraman , Jason Wang , Keith Busch , Klaus Jensen Cc: qemu-devel@nongnu.org, qemu-block@nongnu.org, Akihiko Odaki X-Mailer: b4 0.12.3 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=2607:f8b0:4864:20::42f; envelope-from=akihiko.odaki@daynix.com; helo=mail-pf1-x42f.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @daynix-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1708766795313100029 The spec does not NumVFs is reset after disabling VFs except when resetting the PF. Clearing it is guest visible and out of spec, even though Linux doesn't rely on this value being preserved, so we never noticed. Fixes: 7c0fa8dff811 ("pcie: Add support for Single Root I/O Virtualization = (SR/IOV)") Signed-off-by: Akihiko Odaki --- hw/pci/pcie_sriov.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/pci/pcie_sriov.c b/hw/pci/pcie_sriov.c index 51b66d1bb342..e9b23221d713 100644 --- a/hw/pci/pcie_sriov.c +++ b/hw/pci/pcie_sriov.c @@ -215,7 +215,6 @@ static void unregister_vfs(PCIDevice *dev) g_free(dev->exp.sriov_pf.vf); dev->exp.sriov_pf.vf =3D NULL; dev->exp.sriov_pf.num_vfs =3D 0; - pci_set_word(dev->config + dev->exp.sriov_cap + PCI_SRIOV_NUM_VF, 0); } =20 void pcie_sriov_config_write(PCIDevice *dev, uint32_t address, @@ -260,6 +259,8 @@ void pcie_sriov_pf_reset(PCIDevice *dev) pci_set_word(dev->config + sriov_cap + PCI_SRIOV_CTRL, 0); unregister_vfs(dev); =20 + pci_set_word(dev->config + sriov_cap + PCI_SRIOV_NUM_VF, 0); + /* * Default is to use 4K pages, software can modify it * to any of the supported bits --=20 2.43.2 From nobody Tue Nov 26 09:27:14 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Sat, 24 Feb 2024 01:25:07 -0800 (PST) From: Akihiko Odaki Date: Sat, 24 Feb 2024 18:24:37 +0900 Subject: [PATCH v7 05/16] hw/pci: Always call pcie_sriov_pf_reset() MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240224-reuse-v7-5-29c14bcb952e@daynix.com> References: <20240224-reuse-v7-0-29c14bcb952e@daynix.com> In-Reply-To: <20240224-reuse-v7-0-29c14bcb952e@daynix.com> To: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" , Marcel Apfelbaum , Alex Williamson , =?utf-8?q?C=C3=A9dric_Le_Goater?= , Paolo Bonzini , =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , Eduardo Habkost , Sriram Yagnaraman , Jason Wang , Keith Busch , Klaus Jensen Cc: qemu-devel@nongnu.org, qemu-block@nongnu.org, Akihiko Odaki X-Mailer: b4 0.12.3 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=2607:f8b0:4864:20::632; envelope-from=akihiko.odaki@daynix.com; helo=mail-pl1-x632.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @daynix-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1708766813323100003 Call pcie_sriov_pf_reset() from pci_do_device_reset() just as we do for msi_reset() and msix_reset() to prevent duplicating code for each SR-IOV PF. Signed-off-by: Akihiko Odaki --- hw/net/igb.c | 2 -- hw/nvme/ctrl.c | 4 ---- hw/pci/pci.c | 1 + 3 files changed, 1 insertion(+), 6 deletions(-) diff --git a/hw/net/igb.c b/hw/net/igb.c index 9345506f81ec..9b37523d6df8 100644 --- a/hw/net/igb.c +++ b/hw/net/igb.c @@ -488,12 +488,10 @@ static void igb_pci_uninit(PCIDevice *pci_dev) =20 static void igb_qdev_reset_hold(Object *obj) { - PCIDevice *d =3D PCI_DEVICE(obj); IGBState *s =3D IGB(obj); =20 trace_e1000e_cb_qdev_reset_hold(); =20 - pcie_sriov_pf_reset(d); igb_core_reset(&s->core); } =20 diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c index 7c0d3f108724..c1af4b87b34a 100644 --- a/hw/nvme/ctrl.c +++ b/hw/nvme/ctrl.c @@ -7114,10 +7114,6 @@ static void nvme_ctrl_reset(NvmeCtrl *n, NvmeResetTy= pe rst) sctrl =3D &n->sec_ctrl_list.sec[i]; nvme_virt_set_state(n, le16_to_cpu(sctrl->scid), false); } - - if (rst !=3D NVME_RESET_CONTROLLER) { - pcie_sriov_pf_reset(pci_dev); - } } =20 if (rst !=3D NVME_RESET_CONTROLLER) { diff --git a/hw/pci/pci.c b/hw/pci/pci.c index 6496d027ca61..e7a39cb203ae 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -409,6 +409,7 @@ static void pci_do_device_reset(PCIDevice *dev) =20 msi_reset(dev); msix_reset(dev); + pcie_sriov_pf_reset(dev); } =20 /* --=20 2.43.2 From nobody Tue Nov 26 09:27:14 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1708766789; cv=none; d=zohomail.com; s=zohoarc; b=hAsdCjvAVarrTpI5lSN6tWI8lH8jixpjyz1WmY0nMI9ju2oV5dMIF3ETzKWJVXuajsEG8oNVB8ieR3/8ujXpxWZrmSuX08VQR9zXIxFY7FakFRGVqkcSqbiF9KlnmiiJ56DTDLjqC2BDdByu3J8v0Y69yquwt+ef92OwRTC2ncw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1708766789; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=lyOTxnkcJD9Fch8p801dtN80LFjIP1Z0j9VlXnqzBNg=; b=Qt1JsJLPtn1/c1JwQwl9QkyG2PSxqJortY5DCpMcdwFOjWLkcGONs0JtWcsQEaMNPeZRUM2AJGL+aoL6iFdb913WB0oiJMsydbcAP+0ixQ95Qgr1OGMp27+RInqvM0N+WiuovGq1JKkoCv+syMnCF9CAvH4Enjn4VNhJQe570GU= ARC-Authentication-Results: i=1; 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Sat, 24 Feb 2024 01:25:13 -0800 (PST) From: Akihiko Odaki Date: Sat, 24 Feb 2024 18:24:38 +0900 Subject: [PATCH v7 06/16] hw/pci: Rename has_power to enabled MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240224-reuse-v7-6-29c14bcb952e@daynix.com> References: <20240224-reuse-v7-0-29c14bcb952e@daynix.com> In-Reply-To: <20240224-reuse-v7-0-29c14bcb952e@daynix.com> To: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" , Marcel Apfelbaum , Alex Williamson , =?utf-8?q?C=C3=A9dric_Le_Goater?= , Paolo Bonzini , =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , Eduardo Habkost , Sriram Yagnaraman , Jason Wang , Keith Busch , Klaus Jensen Cc: qemu-devel@nongnu.org, qemu-block@nongnu.org, Akihiko Odaki X-Mailer: b4 0.12.3 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=2607:f8b0:4864:20::436; envelope-from=akihiko.odaki@daynix.com; helo=mail-pf1-x436.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @daynix-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1708766791303100019 The renamed state will not only represent powering state of PFs, but also represent SR-IOV VF enablement in the future. Signed-off-by: Akihiko Odaki --- include/hw/pci/pci.h | 7 ++++++- include/hw/pci/pci_device.h | 2 +- hw/pci/pci.c | 14 +++++++------- hw/pci/pci_host.c | 4 ++-- 4 files changed, 16 insertions(+), 11 deletions(-) diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h index eaa3fc99d884..6c92b2f70008 100644 --- a/include/hw/pci/pci.h +++ b/include/hw/pci/pci.h @@ -642,6 +642,11 @@ static inline void pci_irq_pulse(PCIDevice *pci_dev) } =20 MSIMessage pci_get_msi_message(PCIDevice *dev, int vector); -void pci_set_power(PCIDevice *pci_dev, bool state); +void pci_set_enabled(PCIDevice *pci_dev, bool state); + +static inline void pci_set_power(PCIDevice *pci_dev, bool state) +{ + pci_set_enabled(pci_dev, state); +} =20 #endif diff --git a/include/hw/pci/pci_device.h b/include/hw/pci/pci_device.h index d3dd0f64b273..d57f9ce83884 100644 --- a/include/hw/pci/pci_device.h +++ b/include/hw/pci/pci_device.h @@ -56,7 +56,7 @@ typedef struct PCIReqIDCache PCIReqIDCache; struct PCIDevice { DeviceState qdev; bool partially_hotplugged; - bool has_power; + bool enabled; =20 /* PCI config space */ uint8_t *config; diff --git a/hw/pci/pci.c b/hw/pci/pci.c index e7a39cb203ae..8bde13f7cd1e 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -1525,7 +1525,7 @@ static void pci_update_mappings(PCIDevice *d) continue; =20 new_addr =3D pci_bar_address(d, i, r->type, r->size); - if (!d->has_power) { + if (!d->enabled) { new_addr =3D PCI_BAR_UNMAPPED; } =20 @@ -1613,7 +1613,7 @@ void pci_default_write_config(PCIDevice *d, uint32_t = addr, uint32_t val_in, int pci_update_irq_disabled(d, was_irq_disabled); memory_region_set_enabled(&d->bus_master_enable_region, (pci_get_word(d->config + PCI_COMMAND) - & PCI_COMMAND_MASTER) && d->has_power); + & PCI_COMMAND_MASTER) && d->enabled); } =20 msi_write_config(d, addr, val_in, l); @@ -2811,18 +2811,18 @@ MSIMessage pci_get_msi_message(PCIDevice *dev, int = vector) return msg; } =20 -void pci_set_power(PCIDevice *d, bool state) +void pci_set_enabled(PCIDevice *d, bool state) { - if (d->has_power =3D=3D state) { + if (d->enabled =3D=3D state) { return; } =20 - d->has_power =3D state; + d->enabled =3D state; pci_update_mappings(d); memory_region_set_enabled(&d->bus_master_enable_region, (pci_get_word(d->config + PCI_COMMAND) - & PCI_COMMAND_MASTER) && d->has_power); - if (!d->has_power) { + & PCI_COMMAND_MASTER) && d->enabled); + if (!d->enabled) { pci_device_reset(d); } } diff --git a/hw/pci/pci_host.c b/hw/pci/pci_host.c index dfe6fe618401..0d82727cc9dd 100644 --- a/hw/pci/pci_host.c +++ b/hw/pci/pci_host.c @@ -86,7 +86,7 @@ void pci_host_config_write_common(PCIDevice *pci_dev, uin= t32_t addr, * allowing direct removal of unexposed functions. */ if ((pci_dev->qdev.hotplugged && !pci_get_function_0(pci_dev)) || - !pci_dev->has_power || is_pci_dev_ejected(pci_dev)) { + !pci_dev->enabled || is_pci_dev_ejected(pci_dev)) { return; } =20 @@ -111,7 +111,7 @@ uint32_t pci_host_config_read_common(PCIDevice *pci_dev= , uint32_t addr, * allowing direct removal of unexposed functions. */ if ((pci_dev->qdev.hotplugged && !pci_get_function_0(pci_dev)) || - !pci_dev->has_power || is_pci_dev_ejected(pci_dev)) { + !pci_dev->enabled || is_pci_dev_ejected(pci_dev)) { return ~0x0; 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Sat, 24 Feb 2024 01:25:17 -0800 (PST) From: Akihiko Odaki Date: Sat, 24 Feb 2024 18:24:39 +0900 Subject: [PATCH v7 07/16] pcie_sriov: Do not manually unrealize MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240224-reuse-v7-7-29c14bcb952e@daynix.com> References: <20240224-reuse-v7-0-29c14bcb952e@daynix.com> In-Reply-To: <20240224-reuse-v7-0-29c14bcb952e@daynix.com> To: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" , Marcel Apfelbaum , Alex Williamson , =?utf-8?q?C=C3=A9dric_Le_Goater?= , Paolo Bonzini , =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , Eduardo Habkost , Sriram Yagnaraman , Jason Wang , Keith Busch , Klaus Jensen Cc: qemu-devel@nongnu.org, qemu-block@nongnu.org, Akihiko Odaki X-Mailer: b4 0.12.3 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=2607:f8b0:4864:20::430; envelope-from=akihiko.odaki@daynix.com; helo=mail-pf1-x430.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @daynix-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1708766775466100001 A device gets automatically unrealized when being unparented. Signed-off-by: Akihiko Odaki --- hw/pci/pcie_sriov.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/hw/pci/pcie_sriov.c b/hw/pci/pcie_sriov.c index e9b23221d713..8b1fd2a89ad7 100644 --- a/hw/pci/pcie_sriov.c +++ b/hw/pci/pcie_sriov.c @@ -17,7 +17,6 @@ #include "hw/qdev-properties.h" #include "qemu/error-report.h" #include "qemu/range.h" -#include "qapi/error.h" #include "trace.h" =20 static PCIDevice *register_vf(PCIDevice *pf, int devfn, @@ -204,11 +203,7 @@ static void unregister_vfs(PCIDevice *dev) trace_sriov_unregister_vfs(dev->name, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), num_vfs); for (i =3D 0; i < num_vfs; i++) { - Error *err =3D NULL; PCIDevice *vf =3D dev->exp.sriov_pf.vf[i]; - if (!object_property_set_bool(OBJECT(vf), "realized", false, &err)= ) { - error_reportf_err(err, "Failed to unplug: "); - } object_unparent(OBJECT(vf)); object_unref(OBJECT(vf)); } --=20 2.43.2 From nobody Tue Nov 26 09:27:14 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Sat, 24 Feb 2024 01:25:22 -0800 (PST) From: Akihiko Odaki Date: Sat, 24 Feb 2024 18:24:40 +0900 Subject: [PATCH v7 08/16] pcie_sriov: Reuse SR-IOV VF device instances MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240224-reuse-v7-8-29c14bcb952e@daynix.com> References: <20240224-reuse-v7-0-29c14bcb952e@daynix.com> In-Reply-To: <20240224-reuse-v7-0-29c14bcb952e@daynix.com> To: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" , Marcel Apfelbaum , Alex Williamson , =?utf-8?q?C=C3=A9dric_Le_Goater?= , Paolo Bonzini , =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , Eduardo Habkost , Sriram Yagnaraman , Jason Wang , Keith Busch , Klaus Jensen Cc: qemu-devel@nongnu.org, qemu-block@nongnu.org, Akihiko Odaki X-Mailer: b4 0.12.3 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=2607:f8b0:4864:20::635; envelope-from=akihiko.odaki@daynix.com; helo=mail-pl1-x635.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @daynix-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1708766813348100004 Disable SR-IOV VF devices by reusing code to power down PCI devices instead of removing them when the guest requests to disable VFs. This allows to realize devices and report VF realization errors at PF realization time. Signed-off-by: Akihiko Odaki --- docs/pcie_sriov.txt | 8 ++-- include/hw/pci/pci.h | 5 --- include/hw/pci/pci_device.h | 15 +++++++ include/hw/pci/pcie_sriov.h | 6 +-- hw/net/igb.c | 13 ++++-- hw/nvme/ctrl.c | 24 +++++++---- hw/pci/pci.c | 2 +- hw/pci/pcie_sriov.c | 102 +++++++++++++++++++---------------------= ---- 8 files changed, 95 insertions(+), 80 deletions(-) diff --git a/docs/pcie_sriov.txt b/docs/pcie_sriov.txt index a47aad0bfab0..ab2142807f79 100644 --- a/docs/pcie_sriov.txt +++ b/docs/pcie_sriov.txt @@ -52,9 +52,11 @@ setting up a BAR for a VF. ... =20 /* Add and initialize the SR/IOV capability */ - pcie_sriov_pf_init(d, 0x200, "your_virtual_dev", - vf_devid, initial_vfs, total_vfs, - fun_offset, stride); + if (!pcie_sriov_pf_init(d, 0x200, "your_virtual_dev", + vf_devid, initial_vfs, total_vfs, + fun_offset, stride, errp)) { + return; + } =20 /* Set up individual VF BARs (parameters as for normal BARs) */ pcie_sriov_pf_init_vf_bar( ... ) diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h index 6c92b2f70008..442017b4865d 100644 --- a/include/hw/pci/pci.h +++ b/include/hw/pci/pci.h @@ -644,9 +644,4 @@ static inline void pci_irq_pulse(PCIDevice *pci_dev) MSIMessage pci_get_msi_message(PCIDevice *dev, int vector); void pci_set_enabled(PCIDevice *pci_dev, bool state); =20 -static inline void pci_set_power(PCIDevice *pci_dev, bool state) -{ - pci_set_enabled(pci_dev, state); -} - #endif diff --git a/include/hw/pci/pci_device.h b/include/hw/pci/pci_device.h index d57f9ce83884..ca151325085d 100644 --- a/include/hw/pci/pci_device.h +++ b/include/hw/pci/pci_device.h @@ -205,6 +205,21 @@ static inline uint16_t pci_get_bdf(PCIDevice *dev) return PCI_BUILD_BDF(pci_bus_num(pci_get_bus(dev)), dev->devfn); } =20 +static inline void pci_set_power(PCIDevice *pci_dev, bool state) +{ + /* + * Don't change the enabled state of VFs when powering on/off the devi= ce. + * + * When powering on, VFs must not be enabled immediately but they must + * wait until the guest configures SR-IOV. + * When powering off, their corresponding PFs will be reset and disable + * VFs. + */ + if (!pci_is_vf(pci_dev)) { + pci_set_enabled(pci_dev, state); + } +} + uint16_t pci_requester_id(PCIDevice *dev); =20 /* DMA access functions */ diff --git a/include/hw/pci/pcie_sriov.h b/include/hw/pci/pcie_sriov.h index b77eb7bf58ac..4b1133f79e15 100644 --- a/include/hw/pci/pcie_sriov.h +++ b/include/hw/pci/pcie_sriov.h @@ -18,7 +18,6 @@ struct PCIESriovPF { uint16_t num_vfs; /* Number of virtual functions created */ uint8_t vf_bar_type[PCI_NUM_REGIONS]; /* Store type for each VF bar = */ - const char *vfname; /* Reference to the device type used for the VFs */ PCIDevice **vf; /* Pointer to an array of num_vfs VF devices */ }; =20 @@ -27,10 +26,11 @@ struct PCIESriovVF { uint16_t vf_number; /* Logical VF number of this function */ }; =20 -void pcie_sriov_pf_init(PCIDevice *dev, uint16_t offset, +bool pcie_sriov_pf_init(PCIDevice *dev, uint16_t offset, const char *vfname, uint16_t vf_dev_id, uint16_t init_vfs, uint16_t total_vfs, - uint16_t vf_offset, uint16_t vf_stride); + uint16_t vf_offset, uint16_t vf_stride, + Error **errp); void pcie_sriov_pf_exit(PCIDevice *dev); =20 /* Set up a VF bar in the SR/IOV bar area */ diff --git a/hw/net/igb.c b/hw/net/igb.c index 9b37523d6df8..907259fd8b3b 100644 --- a/hw/net/igb.c +++ b/hw/net/igb.c @@ -447,9 +447,16 @@ static void igb_pci_realize(PCIDevice *pci_dev, Error = **errp) =20 pcie_ari_init(pci_dev, 0x150); =20 - pcie_sriov_pf_init(pci_dev, IGB_CAP_SRIOV_OFFSET, TYPE_IGBVF, - IGB_82576_VF_DEV_ID, IGB_MAX_VF_FUNCTIONS, IGB_MAX_VF_FUNCTIONS, - IGB_VF_OFFSET, IGB_VF_STRIDE); + if (!pcie_sriov_pf_init(pci_dev, IGB_CAP_SRIOV_OFFSET, + TYPE_IGBVF, IGB_82576_VF_DEV_ID, + IGB_MAX_VF_FUNCTIONS, IGB_MAX_VF_FUNCTIONS, + IGB_VF_OFFSET, IGB_VF_STRIDE, + errp)) { + pcie_cap_exit(pci_dev); + igb_cleanup_msix(s); + msi_uninit(pci_dev); + return; + } =20 pcie_sriov_pf_init_vf_bar(pci_dev, IGBVF_MMIO_BAR_IDX, PCI_BASE_ADDRESS_MEM_TYPE_64 | PCI_BASE_ADDRESS_MEM_PREFETCH, diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c index c1af4b87b34a..98c3e942077c 100644 --- a/hw/nvme/ctrl.c +++ b/hw/nvme/ctrl.c @@ -8027,7 +8027,8 @@ static uint64_t nvme_bar_size(unsigned total_queues, = unsigned total_irqs, return bar_size; } =20 -static void nvme_init_sriov(NvmeCtrl *n, PCIDevice *pci_dev, uint16_t offs= et) +static bool nvme_init_sriov(NvmeCtrl *n, PCIDevice *pci_dev, uint16_t offs= et, + Error **errp) { uint16_t vf_dev_id =3D n->params.use_intel_id ? PCI_DEVICE_ID_INTEL_NVME : PCI_DEVICE_ID_REDHAT_N= VME; @@ -8036,12 +8037,17 @@ static void nvme_init_sriov(NvmeCtrl *n, PCIDevice = *pci_dev, uint16_t offset) le16_to_cpu(cap->vifrsm), NULL, NULL); =20 - pcie_sriov_pf_init(pci_dev, offset, "nvme", vf_dev_id, - n->params.sriov_max_vfs, n->params.sriov_max_vfs, - NVME_VF_OFFSET, NVME_VF_STRIDE); + if (!pcie_sriov_pf_init(pci_dev, offset, "nvme", vf_dev_id, + n->params.sriov_max_vfs, n->params.sriov_max_v= fs, + NVME_VF_OFFSET, NVME_VF_STRIDE, + errp)) { + return false; + } =20 pcie_sriov_pf_init_vf_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64, bar_size); + + return true; } =20 static int nvme_add_pm_capability(PCIDevice *pci_dev, uint8_t offset) @@ -8120,6 +8126,12 @@ static bool nvme_init_pci(NvmeCtrl *n, PCIDevice *pc= i_dev, Error **errp) return false; } =20 + if (!pci_is_vf(pci_dev) && n->params.sriov_max_vfs && + !nvme_init_sriov(n, pci_dev, 0x120, errp)) { + msix_uninit(pci_dev, &n->bar0, &n->bar0); + return false; + } + nvme_update_msixcap_ts(pci_dev, n->conf_msix_qsize); =20 if (n->params.cmb_size_mb) { @@ -8130,10 +8142,6 @@ static bool nvme_init_pci(NvmeCtrl *n, PCIDevice *pc= i_dev, Error **errp) nvme_init_pmr(n, pci_dev); } =20 - if (!pci_is_vf(pci_dev) && n->params.sriov_max_vfs) { - nvme_init_sriov(n, pci_dev, 0x120); - } - return true; } =20 diff --git a/hw/pci/pci.c b/hw/pci/pci.c index 8bde13f7cd1e..750c2ba696d1 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -2822,7 +2822,7 @@ void pci_set_enabled(PCIDevice *d, bool state) memory_region_set_enabled(&d->bus_master_enable_region, (pci_get_word(d->config + PCI_COMMAND) & PCI_COMMAND_MASTER) && d->enabled); - if (!d->enabled) { + if (d->qdev.realized) { pci_device_reset(d); } } diff --git a/hw/pci/pcie_sriov.c b/hw/pci/pcie_sriov.c index 8b1fd2a89ad7..d934cd7d0e64 100644 --- a/hw/pci/pcie_sriov.c +++ b/hw/pci/pcie_sriov.c @@ -19,15 +19,25 @@ #include "qemu/range.h" #include "trace.h" =20 -static PCIDevice *register_vf(PCIDevice *pf, int devfn, - const char *name, uint16_t vf_num); -static void unregister_vfs(PCIDevice *dev); +static void unparent_vfs(PCIDevice *dev, uint16_t total_vfs) +{ + for (uint16_t i =3D 0; i < total_vfs; i++) { + PCIDevice *vf =3D dev->exp.sriov_pf.vf[i]; + object_unparent(OBJECT(vf)); + object_unref(OBJECT(vf)); + } + g_free(dev->exp.sriov_pf.vf); + dev->exp.sriov_pf.vf =3D NULL; +} =20 -void pcie_sriov_pf_init(PCIDevice *dev, uint16_t offset, +bool pcie_sriov_pf_init(PCIDevice *dev, uint16_t offset, const char *vfname, uint16_t vf_dev_id, uint16_t init_vfs, uint16_t total_vfs, - uint16_t vf_offset, uint16_t vf_stride) + uint16_t vf_offset, uint16_t vf_stride, + Error **errp) { + BusState *bus =3D qdev_get_parent_bus(&dev->qdev); + int32_t devfn =3D dev->devfn + vf_offset; uint8_t *cfg =3D dev->config + offset; uint8_t *wmask; =20 @@ -35,7 +45,6 @@ void pcie_sriov_pf_init(PCIDevice *dev, uint16_t offset, offset, PCI_EXT_CAP_SRIOV_SIZEOF); dev->exp.sriov_cap =3D offset; dev->exp.sriov_pf.num_vfs =3D 0; - dev->exp.sriov_pf.vfname =3D g_strdup(vfname); dev->exp.sriov_pf.vf =3D NULL; =20 pci_set_word(cfg + PCI_SRIOV_VF_OFFSET, vf_offset); @@ -68,13 +77,35 @@ void pcie_sriov_pf_init(PCIDevice *dev, uint16_t offset, pci_set_word(wmask + PCI_SRIOV_SYS_PGSIZE, 0x553); =20 qdev_prop_set_bit(&dev->qdev, "multifunction", true); + + dev->exp.sriov_pf.vf =3D g_new(PCIDevice *, total_vfs); + + for (uint16_t i =3D 0; i < total_vfs; i++) { + PCIDevice *vf =3D pci_new(devfn, vfname); + vf->exp.sriov_vf.pf =3D dev; + vf->exp.sriov_vf.vf_number =3D i; + + if (!qdev_realize(&vf->qdev, bus, errp)) { + unparent_vfs(dev, i); + return false; + } + + /* set vid/did according to sr/iov spec - they are not used */ + pci_config_set_vendor_id(vf->config, 0xffff); + pci_config_set_device_id(vf->config, 0xffff); + + dev->exp.sriov_pf.vf[i] =3D vf; + devfn +=3D vf_stride; + } + + return true; } =20 void pcie_sriov_pf_exit(PCIDevice *dev) { - unregister_vfs(dev); - g_free((char *)dev->exp.sriov_pf.vfname); - dev->exp.sriov_pf.vfname =3D NULL; + uint8_t *cfg =3D dev->config + dev->exp.sriov_cap; + + unparent_vfs(dev, pci_get_word(cfg + PCI_SRIOV_TOTAL_VF)); } =20 void pcie_sriov_pf_init_vf_bar(PCIDevice *dev, int region_num, @@ -140,38 +171,11 @@ void pcie_sriov_vf_register_bar(PCIDevice *dev, int r= egion_num, } } =20 -static PCIDevice *register_vf(PCIDevice *pf, int devfn, const char *name, - uint16_t vf_num) -{ - PCIDevice *dev =3D pci_new(devfn, name); - dev->exp.sriov_vf.pf =3D pf; - dev->exp.sriov_vf.vf_number =3D vf_num; - PCIBus *bus =3D pci_get_bus(pf); - Error *local_err =3D NULL; - - qdev_realize(&dev->qdev, &bus->qbus, &local_err); - if (local_err) { - error_report_err(local_err); - return NULL; - } - - /* set vid/did according to sr/iov spec - they are not used */ - pci_config_set_vendor_id(dev->config, 0xffff); - pci_config_set_device_id(dev->config, 0xffff); - - return dev; -} - static void register_vfs(PCIDevice *dev) { uint16_t num_vfs; uint16_t i; uint16_t sriov_cap =3D dev->exp.sriov_cap; - uint16_t vf_offset =3D - pci_get_word(dev->config + sriov_cap + PCI_SRIOV_VF_OFFSET); - uint16_t vf_stride =3D - pci_get_word(dev->config + sriov_cap + PCI_SRIOV_VF_STRIDE); - int32_t devfn =3D dev->devfn + vf_offset; =20 assert(sriov_cap > 0); num_vfs =3D pci_get_word(dev->config + sriov_cap + PCI_SRIOV_NUM_VF); @@ -179,18 +183,10 @@ static void register_vfs(PCIDevice *dev) return; } =20 - dev->exp.sriov_pf.vf =3D g_new(PCIDevice *, num_vfs); - trace_sriov_register_vfs(dev->name, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), num_vfs); for (i =3D 0; i < num_vfs; i++) { - dev->exp.sriov_pf.vf[i] =3D register_vf(dev, devfn, - dev->exp.sriov_pf.vfname, i); - if (!dev->exp.sriov_pf.vf[i]) { - num_vfs =3D i; - break; - } - devfn +=3D vf_stride; + pci_set_enabled(dev->exp.sriov_pf.vf[i], true); } dev->exp.sriov_pf.num_vfs =3D num_vfs; } @@ -203,12 +199,8 @@ static void unregister_vfs(PCIDevice *dev) trace_sriov_unregister_vfs(dev->name, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), num_vfs); for (i =3D 0; i < num_vfs; i++) { - PCIDevice *vf =3D dev->exp.sriov_pf.vf[i]; - object_unparent(OBJECT(vf)); - object_unref(OBJECT(vf)); + pci_set_enabled(dev->exp.sriov_pf.vf[i], false); } - g_free(dev->exp.sriov_pf.vf); - dev->exp.sriov_pf.vf =3D NULL; dev->exp.sriov_pf.num_vfs =3D 0; } =20 @@ -230,14 +222,10 @@ void pcie_sriov_config_write(PCIDevice *dev, uint32_t= address, PCI_FUNC(dev->devfn), off, val, len); =20 if (range_covers_byte(off, len, PCI_SRIOV_CTRL)) { - if (dev->exp.sriov_pf.num_vfs) { - if (!(val & PCI_SRIOV_CTRL_VFE)) { - unregister_vfs(dev); - } + if (val & PCI_SRIOV_CTRL_VFE) { + register_vfs(dev); } else { - if (val & PCI_SRIOV_CTRL_VFE) { - register_vfs(dev); - } + unregister_vfs(dev); } } } --=20 2.43.2 From nobody Tue Nov 26 09:27:14 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1708766786; cv=none; d=zohomail.com; s=zohoarc; b=OlcrxH/hu8szrFQmkBRHBdZd/FmUZfgFEy6GiFjoic8WfO6B6itSIqtoGbiEi3ji1nPIqZs8yKCnT7AQgipm1Tea/I3d8C0cEKIbUNwKuvwNLJ9c3jy58ZK99FQYOUl8oJzihY8PX2t4+EEunf6Wd33zsiYLC6jSXXh64m5RNV0= ARC-Message-Signature: i=1; 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Sat, 24 Feb 2024 01:25:27 -0800 (PST) From: Akihiko Odaki Date: Sat, 24 Feb 2024 18:24:41 +0900 Subject: [PATCH v7 09/16] pcie_sriov: Release VFs failed to realize MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240224-reuse-v7-9-29c14bcb952e@daynix.com> References: <20240224-reuse-v7-0-29c14bcb952e@daynix.com> In-Reply-To: <20240224-reuse-v7-0-29c14bcb952e@daynix.com> To: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" , Marcel Apfelbaum , Alex Williamson , =?utf-8?q?C=C3=A9dric_Le_Goater?= , Paolo Bonzini , =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , Eduardo Habkost , Sriram Yagnaraman , Jason Wang , Keith Busch , Klaus Jensen Cc: qemu-devel@nongnu.org, qemu-block@nongnu.org, Akihiko Odaki X-Mailer: b4 0.12.3 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=2607:f8b0:4864:20::633; envelope-from=akihiko.odaki@daynix.com; helo=mail-pl1-x633.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @daynix-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1708766787359100007 Release VFs failed to realize just as we do in unregister_vfs(). Fixes: 7c0fa8dff811 ("pcie: Add support for Single Root I/O Virtualization = (SR/IOV)") Signed-off-by: Akihiko Odaki --- hw/pci/pcie_sriov.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/pci/pcie_sriov.c b/hw/pci/pcie_sriov.c index d934cd7d0e64..8710ee95b26d 100644 --- a/hw/pci/pcie_sriov.c +++ b/hw/pci/pcie_sriov.c @@ -86,6 +86,8 @@ bool pcie_sriov_pf_init(PCIDevice *dev, uint16_t offset, vf->exp.sriov_vf.vf_number =3D i; =20 if (!qdev_realize(&vf->qdev, bus, errp)) { + object_unparent(OBJECT(vf)); + object_unref(vf); unparent_vfs(dev, i); return false; } --=20 2.43.2 From nobody Tue Nov 26 09:27:14 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1708766817; cv=none; d=zohomail.com; s=zohoarc; b=GAa5LYAfp5x/JLxxKiJAUOfWi8YwWRiXhnHZqOCs92ERcpx9EaV05CaSjHi0IrUA6ZNpQa3jC2dHVxO/7mrJa9FGIp4dJsMfDZlH8Bhwj4Q05BVEWQ4b0AWtn9T2+B58TIEFH9jtakyenJr/0PjI8C6KPbK6CtIlES46UXLGAjc= ARC-Message-Signature: i=1; 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Sat, 24 Feb 2024 01:25:31 -0800 (PST) From: Akihiko Odaki Date: Sat, 24 Feb 2024 18:24:42 +0900 Subject: [PATCH v7 10/16] pcie_sriov: Remove num_vfs from PCIESriovPF MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240224-reuse-v7-10-29c14bcb952e@daynix.com> References: <20240224-reuse-v7-0-29c14bcb952e@daynix.com> In-Reply-To: <20240224-reuse-v7-0-29c14bcb952e@daynix.com> To: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" , Marcel Apfelbaum , Alex Williamson , =?utf-8?q?C=C3=A9dric_Le_Goater?= , Paolo Bonzini , =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , Eduardo Habkost , Sriram Yagnaraman , Jason Wang , Keith Busch , Klaus Jensen Cc: qemu-devel@nongnu.org, qemu-block@nongnu.org, Akihiko Odaki X-Mailer: b4 0.12.3 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=2607:f8b0:4864:20::32c; envelope-from=akihiko.odaki@daynix.com; helo=mail-ot1-x32c.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @daynix-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1708766819347100002 num_vfs is not migrated so use PCI_SRIOV_CTRL_VFE and PCI_SRIOV_NUM_VF instead. Signed-off-by: Akihiko Odaki --- include/hw/pci/pcie_sriov.h | 1 - hw/pci/pcie_sriov.c | 28 ++++++++++++++++++++-------- hw/pci/trace-events | 2 +- 3 files changed, 21 insertions(+), 10 deletions(-) diff --git a/include/hw/pci/pcie_sriov.h b/include/hw/pci/pcie_sriov.h index 4b1133f79e15..793d03c5f12e 100644 --- a/include/hw/pci/pcie_sriov.h +++ b/include/hw/pci/pcie_sriov.h @@ -16,7 +16,6 @@ #include "hw/pci/pci.h" =20 struct PCIESriovPF { - uint16_t num_vfs; /* Number of virtual functions created */ uint8_t vf_bar_type[PCI_NUM_REGIONS]; /* Store type for each VF bar = */ PCIDevice **vf; /* Pointer to an array of num_vfs VF devices */ }; diff --git a/hw/pci/pcie_sriov.c b/hw/pci/pcie_sriov.c index 8710ee95b26d..fb48c1a18c9a 100644 --- a/hw/pci/pcie_sriov.c +++ b/hw/pci/pcie_sriov.c @@ -44,7 +44,6 @@ bool pcie_sriov_pf_init(PCIDevice *dev, uint16_t offset, pcie_add_capability(dev, PCI_EXT_CAP_ID_SRIOV, 1, offset, PCI_EXT_CAP_SRIOV_SIZEOF); dev->exp.sriov_cap =3D offset; - dev->exp.sriov_pf.num_vfs =3D 0; dev->exp.sriov_pf.vf =3D NULL; =20 pci_set_word(cfg + PCI_SRIOV_VF_OFFSET, vf_offset); @@ -173,6 +172,12 @@ void pcie_sriov_vf_register_bar(PCIDevice *dev, int re= gion_num, } } =20 +static void clear_ctrl_vfe(PCIDevice *dev) +{ + uint8_t *ctrl =3D dev->config + dev->exp.sriov_cap + PCI_SRIOV_CTRL; + pci_set_word(ctrl, pci_get_word(ctrl) & ~PCI_SRIOV_CTRL_VFE); +} + static void register_vfs(PCIDevice *dev) { uint16_t num_vfs; @@ -182,6 +187,7 @@ static void register_vfs(PCIDevice *dev) assert(sriov_cap > 0); num_vfs =3D pci_get_word(dev->config + sriov_cap + PCI_SRIOV_NUM_VF); if (num_vfs > pci_get_word(dev->config + sriov_cap + PCI_SRIOV_TOTAL_V= F)) { + clear_ctrl_vfe(dev); return; } =20 @@ -190,20 +196,18 @@ static void register_vfs(PCIDevice *dev) for (i =3D 0; i < num_vfs; i++) { pci_set_enabled(dev->exp.sriov_pf.vf[i], true); } - dev->exp.sriov_pf.num_vfs =3D num_vfs; } =20 static void unregister_vfs(PCIDevice *dev) { - uint16_t num_vfs =3D dev->exp.sriov_pf.num_vfs; uint16_t i; + uint8_t *cfg =3D dev->config + dev->exp.sriov_cap; =20 trace_sriov_unregister_vfs(dev->name, PCI_SLOT(dev->devfn), - PCI_FUNC(dev->devfn), num_vfs); - for (i =3D 0; i < num_vfs; i++) { + PCI_FUNC(dev->devfn)); + for (i =3D 0; i < pci_get_word(cfg + PCI_SRIOV_TOTAL_VF); i++) { pci_set_enabled(dev->exp.sriov_pf.vf[i], false); } - dev->exp.sriov_pf.num_vfs =3D 0; } =20 void pcie_sriov_config_write(PCIDevice *dev, uint32_t address, @@ -229,6 +233,9 @@ void pcie_sriov_config_write(PCIDevice *dev, uint32_t a= ddress, } else { unregister_vfs(dev); } + } else if (range_covers_byte(off, len, PCI_SRIOV_NUM_VF)) { + clear_ctrl_vfe(dev); + unregister_vfs(dev); } } =20 @@ -291,7 +298,7 @@ PCIDevice *pcie_sriov_get_pf(PCIDevice *dev) PCIDevice *pcie_sriov_get_vf_at_index(PCIDevice *dev, int n) { assert(!pci_is_vf(dev)); - if (n < dev->exp.sriov_pf.num_vfs) { + if (n < pcie_sriov_num_vfs(dev)) { return dev->exp.sriov_pf.vf[n]; } return NULL; @@ -299,5 +306,10 @@ PCIDevice *pcie_sriov_get_vf_at_index(PCIDevice *dev, = int n) =20 uint16_t pcie_sriov_num_vfs(PCIDevice *dev) { - return dev->exp.sriov_pf.num_vfs; + uint16_t sriov_cap =3D dev->exp.sriov_cap; + uint8_t *cfg =3D dev->config + sriov_cap; + + return sriov_cap && + (pci_get_word(cfg + PCI_SRIOV_CTRL) & PCI_SRIOV_CTRL_VFE) ? + pci_get_word(cfg + PCI_SRIOV_NUM_VF) : 0; } diff --git a/hw/pci/trace-events b/hw/pci/trace-events index 42430869ce05..b30e31619787 100644 --- a/hw/pci/trace-events +++ b/hw/pci/trace-events @@ -14,5 +14,5 @@ msix_write_config(char *name, bool enabled, bool masked) = "dev %s enabled %d mask =20 # hw/pci/pcie_sriov.c sriov_register_vfs(const char *name, int slot, int function, int num_vfs) = "%s %02x:%x: creating %d vf devs" -sriov_unregister_vfs(const char *name, int slot, int function, int num_vfs= ) "%s %02x:%x: Unregistering %d vf devs" +sriov_unregister_vfs(const char *name, int slot, int function) "%s %02x:%x= : Unregistering vf devs" sriov_config_write(const char *name, int slot, int fun, uint32_t offset, u= int32_t val, uint32_t len) "%s %02x:%x: sriov offset 0x%x val 0x%x len %d" --=20 2.43.2 From nobody Tue Nov 26 09:27:14 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Sat, 24 Feb 2024 01:25:36 -0800 (PST) From: Akihiko Odaki Date: Sat, 24 Feb 2024 18:24:43 +0900 Subject: [PATCH v7 11/16] pcie_sriov: Register VFs after migration MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240224-reuse-v7-11-29c14bcb952e@daynix.com> References: <20240224-reuse-v7-0-29c14bcb952e@daynix.com> In-Reply-To: <20240224-reuse-v7-0-29c14bcb952e@daynix.com> To: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" , Marcel Apfelbaum , Alex Williamson , =?utf-8?q?C=C3=A9dric_Le_Goater?= , Paolo Bonzini , =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , Eduardo Habkost , Sriram Yagnaraman , Jason Wang , Keith Busch , Klaus Jensen Cc: qemu-devel@nongnu.org, qemu-block@nongnu.org, Akihiko Odaki X-Mailer: b4 0.12.3 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=2607:f8b0:4864:20::52d; envelope-from=akihiko.odaki@daynix.com; helo=mail-pg1-x52d.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @daynix-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1708766807315100011 pcie_sriov doesn't have code to restore its state after migration, but igb, which uses pcie_sriov, naively claimed its migration capability. Add code to register VFs after migration and fix igb migration. Fixes: 3a977deebe6b ("Intrdocue igb device emulation") Signed-off-by: Akihiko Odaki --- include/hw/pci/pcie_sriov.h | 2 ++ hw/pci/pci.c | 7 +++++++ hw/pci/pcie_sriov.c | 7 +++++++ 3 files changed, 16 insertions(+) diff --git a/include/hw/pci/pcie_sriov.h b/include/hw/pci/pcie_sriov.h index 793d03c5f12e..d576a8c6be19 100644 --- a/include/hw/pci/pcie_sriov.h +++ b/include/hw/pci/pcie_sriov.h @@ -57,6 +57,8 @@ void pcie_sriov_pf_add_sup_pgsize(PCIDevice *dev, uint16_= t opt_sup_pgsize); void pcie_sriov_config_write(PCIDevice *dev, uint32_t address, uint32_t val, int len); =20 +void pcie_sriov_pf_post_load(PCIDevice *dev); + /* Reset SR/IOV */ void pcie_sriov_pf_reset(PCIDevice *dev); =20 diff --git a/hw/pci/pci.c b/hw/pci/pci.c index 750c2ba696d1..54b375da2d26 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -733,10 +733,17 @@ static bool migrate_is_not_pcie(void *opaque, int ver= sion_id) return !pci_is_express((PCIDevice *)opaque); } =20 +static int pci_post_load(void *opaque, int version_id) +{ + pcie_sriov_pf_post_load(opaque); + return 0; +} + const VMStateDescription vmstate_pci_device =3D { .name =3D "PCIDevice", .version_id =3D 2, .minimum_version_id =3D 1, + .post_load =3D pci_post_load, .fields =3D (const VMStateField[]) { VMSTATE_INT32_POSITIVE_LE(version_id, PCIDevice), VMSTATE_BUFFER_UNSAFE_INFO_TEST(config, PCIDevice, diff --git a/hw/pci/pcie_sriov.c b/hw/pci/pcie_sriov.c index fb48c1a18c9a..09a53ed30027 100644 --- a/hw/pci/pcie_sriov.c +++ b/hw/pci/pcie_sriov.c @@ -239,6 +239,13 @@ void pcie_sriov_config_write(PCIDevice *dev, uint32_t = address, } } =20 +void pcie_sriov_pf_post_load(PCIDevice *dev) +{ + if (dev->exp.sriov_cap) { + register_vfs(dev); + } +} + =20 /* Reset SR/IOV */ void pcie_sriov_pf_reset(PCIDevice *dev) --=20 2.43.2 From nobody Tue Nov 26 09:27:14 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; 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bh=to/Jrs3zcoDLKOpkcBrN6NN3gvz3JR19dFR5YKO4O7w=; b=hLJyj+IUiQc6VJK5uVJEusPHW1ajMoUzAvA2eLKA73dPC0g03zcymTxht4Fl93y2pF MghquRWTagelRZ9DuthB5/YIQZJQjnxduIMlFX4HtJrU1U21mA/pApLHs/TSbu3ajLwi o2YULNRQn2Jg+y0K1jtWW6UW34sm0mkcpyNiPXJtTTpIgh8fkcL1LswlHmD2ZHKHTJ52 yF3kXiAAUgoud3GggsQHTzBUDyccTJWaR9I3q44DsHrf3SYa5v3wDOpjfehsKJbYOZMN NhBS5MkU3z7SY5XALRthH3166E7D9m4R7eOiWZjaDIRrTPS28AmKNPXsnDgeXW9eETq3 q+Lw== X-Gm-Message-State: AOJu0YyRWCL4XrxaPhX1z4RCUyG/BfqXad3Gr6lbmKXB5bDa8S8Lbq55 g2b1lpI0z373piZs7S6buKiPc3MfyfczkPLbbnoTKaep4t7OY4Xtyq06yDOsoFMtVWnoEEGGdgW t X-Google-Smtp-Source: AGHT+IEvAKRNsen9U6MFbhEmv8hOFUJXcaxXE5wYROKuyN7F8tT01/aDL/oyCe8q/RUqfeWR7C33Vw== X-Received: by 2002:aa7:8b84:0:b0:6e4:8df7:d52e with SMTP id r4-20020aa78b84000000b006e48df7d52emr2023122pfd.18.1708766742105; Sat, 24 Feb 2024 01:25:42 -0800 (PST) From: Akihiko Odaki Date: Sat, 24 Feb 2024 18:24:44 +0900 Subject: [PATCH v7 12/16] hw/pci: Replace -1 with UINT32_MAX for romsize MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240224-reuse-v7-12-29c14bcb952e@daynix.com> References: <20240224-reuse-v7-0-29c14bcb952e@daynix.com> In-Reply-To: <20240224-reuse-v7-0-29c14bcb952e@daynix.com> To: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" , Marcel Apfelbaum , Alex Williamson , =?utf-8?q?C=C3=A9dric_Le_Goater?= , Paolo Bonzini , =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , Eduardo Habkost , Sriram Yagnaraman , Jason Wang , Keith Busch , Klaus Jensen Cc: qemu-devel@nongnu.org, qemu-block@nongnu.org, Akihiko Odaki X-Mailer: b4 0.12.3 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=2607:f8b0:4864:20::433; envelope-from=akihiko.odaki@daynix.com; helo=mail-pf1-x433.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @daynix-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1708766793305100023 romsize is an uint32_t variable. Specifying -1 as an uint32_t value is obscure way to denote UINT32_MAX. Worse, if int is wider than 32-bit, it will change the behavior of a construct like the following: romsize =3D -1; if (romsize !=3D -1) { ... } When -1 is assigned to romsize, -1 will be implicitly casted into uint32_t, resulting in UINT32_MAX. On contrary, when evaluating romsize !=3D -1, romsize will be casted into int, and it will be a comparison of UINT32_MAX and -1, and result in false. Fix these issues by replacing -1 with UINT32_MAX for statements involving the variable. Signed-off-by: Akihiko Odaki Reviewed-by: Markus Armbruster --- hw/pci/pci.c | 8 ++++---- hw/xen/xen_pt_load_rom.c | 2 +- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/hw/pci/pci.c b/hw/pci/pci.c index 54b375da2d26..84df07a2789b 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -70,7 +70,7 @@ static bool pcie_has_upstream_port(PCIDevice *dev); static Property pci_props[] =3D { DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1), DEFINE_PROP_STRING("romfile", PCIDevice, romfile), - DEFINE_PROP_UINT32("romsize", PCIDevice, romsize, -1), + DEFINE_PROP_UINT32("romsize", PCIDevice, romsize, UINT32_MAX), DEFINE_PROP_UINT32("rombar", PCIDevice, rom_bar, 1), DEFINE_PROP_BIT("multifunction", PCIDevice, cap_present, QEMU_PCI_CAP_MULTIFUNCTION_BITNR, false), @@ -2073,7 +2073,7 @@ static void pci_qdev_realize(DeviceState *qdev, Error= **errp) g_cmp_uint32, NULL); } =20 - if (pci_dev->romsize !=3D -1 && !is_power_of_2(pci_dev->romsize)) { + if (pci_dev->romsize !=3D UINT32_MAX && !is_power_of_2(pci_dev->romsiz= e)) { error_setg(errp, "ROM size %u is not a power of two", pci_dev->rom= size); return; } @@ -2359,7 +2359,7 @@ static void pci_add_option_rom(PCIDevice *pdev, bool = is_default_rom, return; } =20 - if (load_file || pdev->romsize =3D=3D -1) { + if (load_file || pdev->romsize =3D=3D UINT32_MAX) { path =3D qemu_find_file(QEMU_FILE_TYPE_BIOS, pdev->romfile); if (path =3D=3D NULL) { path =3D g_strdup(pdev->romfile); @@ -2378,7 +2378,7 @@ static void pci_add_option_rom(PCIDevice *pdev, bool = is_default_rom, pdev->romfile); return; } - if (pdev->romsize !=3D -1) { + if (pdev->romsize !=3D UINT_MAX) { if (size > pdev->romsize) { error_setg(errp, "romfile \"%s\" (%u bytes) " "is too large for ROM size %u", diff --git a/hw/xen/xen_pt_load_rom.c b/hw/xen/xen_pt_load_rom.c index 03422a8a7148..6bc64acd3352 100644 --- a/hw/xen/xen_pt_load_rom.c +++ b/hw/xen/xen_pt_load_rom.c @@ -53,7 +53,7 @@ void *pci_assign_dev_load_option_rom(PCIDevice *dev, } fseek(fp, 0, SEEK_SET); =20 - if (dev->romsize !=3D -1) { + if (dev->romsize !=3D UINT_MAX) { if (st.st_size > dev->romsize) { error_report("ROM BAR \"%s\" (%ld bytes) is too large for ROM = size %u", rom_file, (long) st.st_size, dev->romsize); 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Sat, 24 Feb 2024 01:25:46 -0800 (PST) From: Akihiko Odaki Date: Sat, 24 Feb 2024 18:24:45 +0900 Subject: [PATCH v7 13/16] hw/pci: Use UINT32_MAX as a default value for rombar MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240224-reuse-v7-13-29c14bcb952e@daynix.com> References: <20240224-reuse-v7-0-29c14bcb952e@daynix.com> In-Reply-To: <20240224-reuse-v7-0-29c14bcb952e@daynix.com> To: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" , Marcel Apfelbaum , Alex Williamson , =?utf-8?q?C=C3=A9dric_Le_Goater?= , Paolo Bonzini , =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , Eduardo Habkost , Sriram Yagnaraman , Jason Wang , Keith Busch , Klaus Jensen Cc: qemu-devel@nongnu.org, qemu-block@nongnu.org, Akihiko Odaki X-Mailer: b4 0.12.3 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=2607:f8b0:4864:20::42e; envelope-from=akihiko.odaki@daynix.com; helo=mail-pf1-x42e.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @daynix-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1708766787388100009 Currently there is no way to distinguish the case that rombar is explicitly specified as 1 and the case that rombar is not specified. Set rombar UINT32_MAX by default to distinguish these cases just as it is done for addr and romsize. It was confirmed that changing the default value to UINT32_MAX will not change the behavior by looking at occurences of rom_bar. $ git grep -w rom_bar hw/display/qxl.c:328: QXLRom *rom =3D memory_region_get_ram_ptr(&d->rom_= bar); hw/display/qxl.c:431: qxl_set_dirty(&qxl->rom_bar, 0, qxl->rom_size); hw/display/qxl.c:1048: QXLRom *rom =3D memory_region_get_ram_ptr(&qxl->r= om_bar); hw/display/qxl.c:2131: memory_region_init_rom(&qxl->rom_bar, OBJECT(qxl)= , "qxl.vrom", hw/display/qxl.c:2154: PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->rom_bar); hw/display/qxl.h:101: MemoryRegion rom_bar; hw/pci/pci.c:74: DEFINE_PROP_UINT32("rombar", PCIDevice, rom_bar, 1), hw/pci/pci.c:2329: if (!pdev->rom_bar) { hw/vfio/pci.c:1019: if (vdev->pdev.romfile || !vdev->pdev.rom_bar) { hw/xen/xen_pt_load_rom.c:29: if (dev->romfile || !dev->rom_bar) { include/hw/pci/pci_device.h:150: uint32_t rom_bar; rom_bar refers to a different variable in qxl. It is only tested if the value is 0 or not in the other places. This changes the semantics of UINT32_MAX, which has always been a valid value to explicitly say rombar is enabled to denote the implicit default value. Nobody should have been set UINT32_MAX to rombar however, considering that its meaning was no different from 1 and typing a literal UINT32_MAX (0xffffffff or 4294967295) is more troublesome. Signed-off-by: Akihiko Odaki --- hw/pci/pci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/pci/pci.c b/hw/pci/pci.c index 84df07a2789b..cb5ac46e9f27 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -71,7 +71,7 @@ static Property pci_props[] =3D { DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1), DEFINE_PROP_STRING("romfile", PCIDevice, romfile), DEFINE_PROP_UINT32("romsize", PCIDevice, romsize, UINT32_MAX), - DEFINE_PROP_UINT32("rombar", PCIDevice, rom_bar, 1), + DEFINE_PROP_UINT32("rombar", PCIDevice, rom_bar, UINT32_MAX), DEFINE_PROP_BIT("multifunction", PCIDevice, cap_present, QEMU_PCI_CAP_MULTIFUNCTION_BITNR, false), DEFINE_PROP_BIT("x-pcie-lnksta-dllla", PCIDevice, cap_present, --=20 2.43.2 From nobody Tue Nov 26 09:27:14 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; 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Tsirkin" , Marcel Apfelbaum , Alex Williamson , =?utf-8?q?C=C3=A9dric_Le_Goater?= , Paolo Bonzini , =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , Eduardo Habkost , Sriram Yagnaraman , Jason Wang , Keith Busch , Klaus Jensen Cc: qemu-devel@nongnu.org, qemu-block@nongnu.org, Akihiko Odaki X-Mailer: b4 0.12.3 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=2607:f8b0:4864:20::d29; envelope-from=akihiko.odaki@daynix.com; helo=mail-io1-xd29.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @daynix-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1708766795303100028 vfio determines if rombar is explicitly enabled by inspecting QDict. Inspecting QDict is not nice because QDict is untyped and depends on the details on the external interface. Add an infrastructure to determine if rombar is explicitly enabled to hw/pci. Signed-off-by: Akihiko Odaki --- include/hw/pci/pci_device.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/hw/pci/pci_device.h b/include/hw/pci/pci_device.h index ca151325085d..6be0f989ebe0 100644 --- a/include/hw/pci/pci_device.h +++ b/include/hw/pci/pci_device.h @@ -205,6 +205,11 @@ static inline uint16_t pci_get_bdf(PCIDevice *dev) return PCI_BUILD_BDF(pci_bus_num(pci_get_bus(dev)), dev->devfn); } =20 +static inline bool pci_rom_bar_explicitly_enabled(PCIDevice *dev) +{ + return dev->rom_bar && dev->rom_bar !=3D UINT32_MAX; +} + static inline void pci_set_power(PCIDevice *pci_dev, bool state) { /* --=20 2.43.2 From nobody Tue Nov 26 09:27:14 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1708766804; cv=none; d=zohomail.com; s=zohoarc; b=byRvsvNsi+S4rvr7zW9xe1dH44vxaTa9EVPDLWREaKYvxXzz/Q02WnDWos6yJj66+Wr72OHV40B++7MTkyf0hrXS2Q3pf0/sstYG6QydC+j05f1phKNSVXHuOUCs4aCgPn/E7x7Vj7uSHnY4Q26iBQ+/u0/QvJ10v1wEDJlvHjI= ARC-Message-Signature: i=1; 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Sat, 24 Feb 2024 01:25:56 -0800 (PST) From: Akihiko Odaki Date: Sat, 24 Feb 2024 18:24:47 +0900 Subject: [PATCH v7 15/16] vfio: Avoid inspecting option QDict for rombar MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240224-reuse-v7-15-29c14bcb952e@daynix.com> References: <20240224-reuse-v7-0-29c14bcb952e@daynix.com> In-Reply-To: <20240224-reuse-v7-0-29c14bcb952e@daynix.com> To: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" , Marcel Apfelbaum , Alex Williamson , =?utf-8?q?C=C3=A9dric_Le_Goater?= , Paolo Bonzini , =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , Eduardo Habkost , Sriram Yagnaraman , Jason Wang , Keith Busch , Klaus Jensen Cc: qemu-devel@nongnu.org, qemu-block@nongnu.org, Akihiko Odaki X-Mailer: b4 0.12.3 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=2607:f8b0:4864:20::52d; envelope-from=akihiko.odaki@daynix.com; helo=mail-pg1-x52d.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @daynix-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1708766805307100006 Use pci_rom_bar_explicitly_enabled() to determine if rombar is explicitly enabled. Signed-off-by: Akihiko Odaki --- hw/vfio/pci.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/hw/vfio/pci.c b/hw/vfio/pci.c index 4fa387f0430d..647f15b2a060 100644 --- a/hw/vfio/pci.c +++ b/hw/vfio/pci.c @@ -1012,7 +1012,6 @@ static void vfio_pci_size_rom(VFIOPCIDevice *vdev) { uint32_t orig, size =3D cpu_to_le32((uint32_t)PCI_ROM_ADDRESS_MASK); off_t offset =3D vdev->config_offset + PCI_ROM_ADDRESS; - DeviceState *dev =3D DEVICE(vdev); char *name; int fd =3D vdev->vbasedev.fd; =20 @@ -1046,7 +1045,7 @@ static void vfio_pci_size_rom(VFIOPCIDevice *vdev) } =20 if (vfio_opt_rom_in_denylist(vdev)) { - if (dev->opts && qdict_haskey(dev->opts, "rombar")) { + if (pci_rom_bar_explicitly_enabled(&vdev->pdev)) { warn_report("Device at %s is known to cause system instability" " issues during option rom execution", vdev->vbasedev.name); --=20 2.43.2 From nobody Tue Nov 26 09:27:14 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; 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Signed-off-by: Akihiko Odaki Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Markus Armbruster --- include/hw/qdev-core.h | 4 ---- hw/core/qdev.c | 1 - system/qdev-monitor.c | 12 +++++++----- 3 files changed, 7 insertions(+), 10 deletions(-) diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h index 9228e96c87e9..5954404dcbfe 100644 --- a/include/hw/qdev-core.h +++ b/include/hw/qdev-core.h @@ -237,10 +237,6 @@ struct DeviceState { * @pending_deleted_expires_ms: optional timeout for deletion events */ int64_t pending_deleted_expires_ms; - /** - * @opts: QDict of options for the device - */ - QDict *opts; /** * @hotplugged: was device added after PHASE_MACHINE_READY? */ diff --git a/hw/core/qdev.c b/hw/core/qdev.c index c68d0f7c512f..7349c9a86be8 100644 --- a/hw/core/qdev.c +++ b/hw/core/qdev.c @@ -706,7 +706,6 @@ static void device_finalize(Object *obj) dev->canonical_path =3D NULL; } =20 - qobject_unref(dev->opts); g_free(dev->id); } =20 diff --git a/system/qdev-monitor.c b/system/qdev-monitor.c index a13db763e5dd..71c00f62ee38 100644 --- a/system/qdev-monitor.c +++ b/system/qdev-monitor.c @@ -625,6 +625,7 @@ DeviceState *qdev_device_add_from_qdict(const QDict *op= ts, char *id; DeviceState *dev =3D NULL; BusState *bus =3D NULL; + QDict *properties; =20 driver =3D qdict_get_try_str(opts, "driver"); if (!driver) { @@ -705,13 +706,14 @@ DeviceState *qdev_device_add_from_qdict(const QDict *= opts, } =20 /* set properties */ - dev->opts =3D qdict_clone_shallow(opts); - qdict_del(dev->opts, "driver"); - qdict_del(dev->opts, "bus"); - qdict_del(dev->opts, "id"); + properties =3D qdict_clone_shallow(opts); + qdict_del(properties, "driver"); + qdict_del(properties, "bus"); + qdict_del(properties, "id"); =20 - object_set_properties_from_keyval(&dev->parent_obj, dev->opts, from_js= on, + object_set_properties_from_keyval(&dev->parent_obj, properties, from_j= son, errp); + qobject_unref(properties); if (*errp) { goto err_del_dev; } --=20 2.43.2