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[220.235.194.103]) by smtp.gmail.com with ESMTPSA id h18-20020a170902f2d200b001d913992d8csm11808208plc.242.2024.02.23.07.44.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 Feb 2024 07:44:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1708703098; x=1709307898; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=vnNcFhcPpHPQfTpWuGG2ElYVSBywzwh7uuGTk3mm7yg=; b=FyDL/kc4+Z8opU8dI6TpUv1TyIkaVc5/qyIh9RQyAxTZTee5tuLoHEXe0NyGBZud12 B+QzX6lEgsuKIVCy0z4AYeE23qRzMKa7dOY6Kmxl7v1BFjHLtrn/fArYaxhWyTgFrV2Q VCX8U0LGBchJG3WfmKnEGSW56Ls3//y2+TOqv+TRbfeBeWlRiApncU26m+AC1urxC9aD DtAUy3FYFC8kxzTVtNWrV4hDQuxTVTv7gqnLfsvFxoTsrfN5Ep3d7eJvt0T5W3PJtgf1 wOg8DjM51PE4T22wcV6AOaBxwBuHeqIBeh3IncNxJz+yV6aWbXZ6mkSmxMNI5WK4O87j OcDQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1708703098; x=1709307898; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vnNcFhcPpHPQfTpWuGG2ElYVSBywzwh7uuGTk3mm7yg=; b=ZXjioxN3361OxSwD5wQLzFRsUxhECDSb9FBmJQRZbQNJmi/fiWx7fQ3/f5yd6qiqnS cJ03UKqacvO+NsyW6bndmW43yYOog99nBHKzLs2W+rdDAqqs5RUkbQ6k73v0Gyz4Dzc6 jNq3vgbQeKuUCv6NqezJS5pRZiVu9S83jOtlitVOot3tnhwGZFiGKVo4CAes+S2BrGEC hmxNhdX4Q3/NkqrpMzfSXkWPIl+Eo0Dz3huxN08mwcqxJZgGZ3g8u7+5qvK91LbGvN9G +cMaOM1ch1ND/dyULwVnCR1uRQAtvO6MsqsbCPc+G6Bf+Qxg234sOBUBamX3r4IeN3mm tfnQ== X-Forwarded-Encrypted: i=1; AJvYcCXXz0MHxil5dYUpbSgyVyOBB/rwp3nFWiPnhQpGIk49lM8ZUiQN00+GUVr35pzQUWiRzXvX2NXxxY94j48ImdoXOnGN X-Gm-Message-State: AOJu0YzrQQg1MKnHxScovy7ifJ7kQb+5f0SlmnI2wwV/xO0iUY7zSRaB LMupPCKJv5W1EmlqsWdgxg9qbE9IY5usUzHCFfk3011z4jbPWX5f71tZaZXi X-Google-Smtp-Source: AGHT+IFU/fzcB8rjNfvaNP4ILkGFKhYCceEzjAr5KN6v/P/+8bDkO9Tz9ySqOt7bxJfxNM14jgjBLQ== X-Received: by 2002:a17:902:d489:b0:1dc:3cd:f97b with SMTP id c9-20020a170902d48900b001dc03cdf97bmr136264plg.32.1708703097676; Fri, 23 Feb 2024 07:44:57 -0800 (PST) From: Nicholas Piggin To: qemu-devel@nongnu.org Cc: Nicholas Piggin , qemu-ppc@nongnu.org, Daniel Henrique Barboza , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Harsh Prateek Bora , Glenn Miles Subject: [PULL 27/47] misc: Add a pca9554 GPIO device model Date: Sat, 24 Feb 2024 01:41:46 +1000 Message-ID: <20240223154211.1001692-28-npiggin@gmail.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20240223154211.1001692-1-npiggin@gmail.com> References: <20240223154211.1001692-1-npiggin@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=npiggin@gmail.com; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1708703745161100002 From: Glenn Miles Specs are available here: https://www.nxp.com/docs/en/data-sheet/PCA9554_9554A.pdf This is a simple model supporting the basic registers for GPIO mode. The device also supports an interrupt output line but the model does not yet support this. Reviewed-by: C=C3=A9dric Le Goater Signed-off-by: Glenn Miles Signed-off-by: Nicholas Piggin --- MAINTAINERS | 10 +- hw/misc/pca9554.c | 328 +++++++++++++++++++++++++++++++++ include/hw/misc/pca9554.h | 36 ++++ include/hw/misc/pca9554_regs.h | 19 ++ 4 files changed, 391 insertions(+), 2 deletions(-) create mode 100644 hw/misc/pca9554.c create mode 100644 include/hw/misc/pca9554.h create mode 100644 include/hw/misc/pca9554_regs.h diff --git a/MAINTAINERS b/MAINTAINERS index 3b409b42a5..992799171f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1170,9 +1170,7 @@ R: Joel Stanley L: qemu-arm@nongnu.org S: Maintained F: hw/*/*aspeed* -F: hw/misc/pca9552.c F: include/hw/*/*aspeed* -F: include/hw/misc/pca9552*.h F: hw/net/ftgmac100.c F: include/hw/net/ftgmac100.h F: docs/system/arm/aspeed.rst @@ -1544,6 +1542,14 @@ F: include/hw/pci-host/pnv* F: pc-bios/skiboot.lid F: tests/qtest/pnv* =20 +pca955x +M: Glenn Miles +L: qemu-ppc@nongnu.org +L: qemu-arm@nongnu.org +S: Odd Fixes +F: hw/misc/pca955*.c +F: include/hw/misc/pca955*.h + virtex_ml507 M: Edgar E. Iglesias L: qemu-ppc@nongnu.org diff --git a/hw/misc/pca9554.c b/hw/misc/pca9554.c new file mode 100644 index 0000000000..778b32e443 --- /dev/null +++ b/hw/misc/pca9554.c @@ -0,0 +1,328 @@ +/* + * PCA9554 I/O port + * + * Copyright (c) 2023, IBM Corporation. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qemu/module.h" +#include "qemu/bitops.h" +#include "hw/qdev-properties.h" +#include "hw/misc/pca9554.h" +#include "hw/misc/pca9554_regs.h" +#include "hw/irq.h" +#include "migration/vmstate.h" +#include "qapi/error.h" +#include "qapi/visitor.h" +#include "trace.h" +#include "qom/object.h" + +struct PCA9554Class { + /*< private >*/ + I2CSlaveClass parent_class; + /*< public >*/ +}; +typedef struct PCA9554Class PCA9554Class; + +DECLARE_CLASS_CHECKERS(PCA9554Class, PCA9554, + TYPE_PCA9554) + +#define PCA9554_PIN_LOW 0x0 +#define PCA9554_PIN_HIZ 0x1 + +static const char *pin_state[] =3D {"low", "high"}; + +static void pca9554_update_pin_input(PCA9554State *s) +{ + int i; + uint8_t config =3D s->regs[PCA9554_CONFIG]; + uint8_t output =3D s->regs[PCA9554_OUTPUT]; + uint8_t internal_state =3D config | output; + + for (i =3D 0; i < PCA9554_PIN_COUNT; i++) { + uint8_t bit_mask =3D 1 << i; + uint8_t internal_pin_state =3D (internal_state >> i) & 0x1; + uint8_t old_value =3D s->regs[PCA9554_INPUT] & bit_mask; + uint8_t new_value; + + switch (internal_pin_state) { + case PCA9554_PIN_LOW: + s->regs[PCA9554_INPUT] &=3D ~bit_mask; + break; + case PCA9554_PIN_HIZ: + /* + * pullup sets it to a logical 1 unless + * external device drives it low. + */ + if (s->ext_state[i] =3D=3D PCA9554_PIN_LOW) { + s->regs[PCA9554_INPUT] &=3D ~bit_mask; + } else { + s->regs[PCA9554_INPUT] |=3D bit_mask; + } + break; + default: + break; + } + + /* update irq state only if pin state changed */ + new_value =3D s->regs[PCA9554_INPUT] & bit_mask; + if (new_value !=3D old_value) { + if (new_value) { + /* changed from 0 to 1 */ + qemu_set_irq(s->gpio_out[i], 1); + } else { + /* changed from 1 to 0 */ + qemu_set_irq(s->gpio_out[i], 0); + } + } + } +} + +static uint8_t pca9554_read(PCA9554State *s, uint8_t reg) +{ + switch (reg) { + case PCA9554_INPUT: + return s->regs[PCA9554_INPUT] ^ s->regs[PCA9554_POLARITY]; + case PCA9554_OUTPUT: + case PCA9554_POLARITY: + case PCA9554_CONFIG: + return s->regs[reg]; + default: + qemu_log_mask(LOG_GUEST_ERROR, "%s: unexpected read to register %d= \n", + __func__, reg); + return 0xFF; + } +} + +static void pca9554_write(PCA9554State *s, uint8_t reg, uint8_t data) +{ + switch (reg) { + case PCA9554_OUTPUT: + case PCA9554_CONFIG: + s->regs[reg] =3D data; + pca9554_update_pin_input(s); + break; + case PCA9554_POLARITY: + s->regs[reg] =3D data; + break; + case PCA9554_INPUT: + default: + qemu_log_mask(LOG_GUEST_ERROR, "%s: unexpected write to register %= d\n", + __func__, reg); + } +} + +static uint8_t pca9554_recv(I2CSlave *i2c) +{ + PCA9554State *s =3D PCA9554(i2c); + uint8_t ret; + + ret =3D pca9554_read(s, s->pointer & 0x3); + + return ret; +} + +static int pca9554_send(I2CSlave *i2c, uint8_t data) +{ + PCA9554State *s =3D PCA9554(i2c); + + /* First byte sent by is the register address */ + if (s->len =3D=3D 0) { + s->pointer =3D data; + s->len++; + } else { + pca9554_write(s, s->pointer & 0x3, data); + } + + return 0; +} + +static int pca9554_event(I2CSlave *i2c, enum i2c_event event) +{ + PCA9554State *s =3D PCA9554(i2c); + + s->len =3D 0; + return 0; +} + +static void pca9554_get_pin(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + PCA9554State *s =3D PCA9554(obj); + int pin, rc; + uint8_t state; + + rc =3D sscanf(name, "pin%2d", &pin); + if (rc !=3D 1) { + error_setg(errp, "%s: error reading %s", __func__, name); + return; + } + if (pin < 0 || pin > PCA9554_PIN_COUNT) { + error_setg(errp, "%s invalid pin %s", __func__, name); + return; + } + + state =3D pca9554_read(s, PCA9554_CONFIG); + state |=3D pca9554_read(s, PCA9554_OUTPUT); + state =3D (state >> pin) & 0x1; + visit_type_str(v, name, (char **)&pin_state[state], errp); +} + +static void pca9554_set_pin(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + PCA9554State *s =3D PCA9554(obj); + int pin, rc, val; + uint8_t state, mask; + char *state_str; + + if (!visit_type_str(v, name, &state_str, errp)) { + return; + } + rc =3D sscanf(name, "pin%2d", &pin); + if (rc !=3D 1) { + error_setg(errp, "%s: error reading %s", __func__, name); + return; + } + if (pin < 0 || pin > PCA9554_PIN_COUNT) { + error_setg(errp, "%s invalid pin %s", __func__, name); + return; + } + + for (state =3D 0; state < ARRAY_SIZE(pin_state); state++) { + if (!strcmp(state_str, pin_state[state])) { + break; + } + } + if (state >=3D ARRAY_SIZE(pin_state)) { + error_setg(errp, "%s invalid pin state %s", __func__, state_str); + return; + } + + /* First, modify the output register bit */ + val =3D pca9554_read(s, PCA9554_OUTPUT); + mask =3D 0x1 << pin; + if (state =3D=3D PCA9554_PIN_LOW) { + val &=3D ~(mask); + } else { + val |=3D mask; + } + pca9554_write(s, PCA9554_OUTPUT, val); + + /* Then, clear the config register bit for output mode */ + val =3D pca9554_read(s, PCA9554_CONFIG); + val &=3D ~mask; + pca9554_write(s, PCA9554_CONFIG, val); +} + +static const VMStateDescription pca9554_vmstate =3D { + .name =3D "PCA9554", + .version_id =3D 0, + .minimum_version_id =3D 0, + .fields =3D (VMStateField[]) { + VMSTATE_UINT8(len, PCA9554State), + VMSTATE_UINT8(pointer, PCA9554State), + VMSTATE_UINT8_ARRAY(regs, PCA9554State, PCA9554_NR_REGS), + VMSTATE_UINT8_ARRAY(ext_state, PCA9554State, PCA9554_PIN_COUNT), + VMSTATE_I2C_SLAVE(i2c, PCA9554State), + VMSTATE_END_OF_LIST() + } +}; + +static void pca9554_reset(DeviceState *dev) +{ + PCA9554State *s =3D PCA9554(dev); + + s->regs[PCA9554_INPUT] =3D 0xFF; + s->regs[PCA9554_OUTPUT] =3D 0xFF; + s->regs[PCA9554_POLARITY] =3D 0x0; /* No pins are inverted */ + s->regs[PCA9554_CONFIG] =3D 0xFF; /* All pins are inputs */ + + memset(s->ext_state, PCA9554_PIN_HIZ, PCA9554_PIN_COUNT); + pca9554_update_pin_input(s); + + s->pointer =3D 0x0; + s->len =3D 0; +} + +static void pca9554_initfn(Object *obj) +{ + int pin; + + for (pin =3D 0; pin < PCA9554_PIN_COUNT; pin++) { + char *name; + + name =3D g_strdup_printf("pin%d", pin); + object_property_add(obj, name, "bool", pca9554_get_pin, pca9554_se= t_pin, + NULL, NULL); + g_free(name); + } +} + +static void pca9554_set_ext_state(PCA9554State *s, int pin, int level) +{ + if (s->ext_state[pin] !=3D level) { + s->ext_state[pin] =3D level; + pca9554_update_pin_input(s); + } +} + +static void pca9554_gpio_in_handler(void *opaque, int pin, int level) +{ + + PCA9554State *s =3D PCA9554(opaque); + + assert((pin >=3D 0) && (pin < PCA9554_PIN_COUNT)); + pca9554_set_ext_state(s, pin, level); +} + +static void pca9554_realize(DeviceState *dev, Error **errp) +{ + PCA9554State *s =3D PCA9554(dev); + + if (!s->description) { + s->description =3D g_strdup("pca9554"); + } + + qdev_init_gpio_out(dev, s->gpio_out, PCA9554_PIN_COUNT); + qdev_init_gpio_in(dev, pca9554_gpio_in_handler, PCA9554_PIN_COUNT); +} + +static Property pca9554_properties[] =3D { + DEFINE_PROP_STRING("description", PCA9554State, description), + DEFINE_PROP_END_OF_LIST(), +}; + +static void pca9554_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + I2CSlaveClass *k =3D I2C_SLAVE_CLASS(klass); + + k->event =3D pca9554_event; + k->recv =3D pca9554_recv; + k->send =3D pca9554_send; + dc->realize =3D pca9554_realize; + dc->reset =3D pca9554_reset; + dc->vmsd =3D &pca9554_vmstate; + device_class_set_props(dc, pca9554_properties); +} + +static const TypeInfo pca9554_info =3D { + .name =3D TYPE_PCA9554, + .parent =3D TYPE_I2C_SLAVE, + .instance_init =3D pca9554_initfn, + .instance_size =3D sizeof(PCA9554State), + .class_init =3D pca9554_class_init, + .class_size =3D sizeof(PCA9554Class), + .abstract =3D false, +}; + +static void pca9554_register_types(void) +{ + type_register_static(&pca9554_info); +} + +type_init(pca9554_register_types) diff --git a/include/hw/misc/pca9554.h b/include/hw/misc/pca9554.h new file mode 100644 index 0000000000..54bfc4c4c7 --- /dev/null +++ b/include/hw/misc/pca9554.h @@ -0,0 +1,36 @@ +/* + * PCA9554 I/O port + * + * Copyright (c) 2023, IBM Corporation. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#ifndef PCA9554_H +#define PCA9554_H + +#include "hw/i2c/i2c.h" +#include "qom/object.h" + +#define TYPE_PCA9554 "pca9554" +typedef struct PCA9554State PCA9554State; +DECLARE_INSTANCE_CHECKER(PCA9554State, PCA9554, + TYPE_PCA9554) + +#define PCA9554_NR_REGS 4 +#define PCA9554_PIN_COUNT 8 + +struct PCA9554State { + /*< private >*/ + I2CSlave i2c; + /*< public >*/ + + uint8_t len; + uint8_t pointer; + + uint8_t regs[PCA9554_NR_REGS]; + qemu_irq gpio_out[PCA9554_PIN_COUNT]; + uint8_t ext_state[PCA9554_PIN_COUNT]; + char *description; /* For debugging purpose only */ +}; + +#endif diff --git a/include/hw/misc/pca9554_regs.h b/include/hw/misc/pca9554_regs.h new file mode 100644 index 0000000000..602c4a90e0 --- /dev/null +++ b/include/hw/misc/pca9554_regs.h @@ -0,0 +1,19 @@ +/* + * PCA9554 I/O port registers + * + * Copyright (c) 2023, IBM Corporation. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#ifndef PCA9554_REGS_H +#define PCA9554_REGS_H + +/* + * Bits [0:1] are used to address a specific register. + */ +#define PCA9554_INPUT 0 /* read only input register */ +#define PCA9554_OUTPUT 1 /* read/write pin output state */ +#define PCA9554_POLARITY 2 /* Set polarity of input register */ +#define PCA9554_CONFIG 3 /* Set pins as inputs our ouputs */ + +#endif --=20 2.42.0