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Fri, 23 Feb 2024 05:09:54 -0800 (PST) X-Google-Smtp-Source: AGHT+IHiQYSWmODja1eQtpxRBKZ2tluaszOw2+BqWFo5r2ga3PS73eEAwnQqiY+K9X+lu8puL5n6fA== X-Received: by 2002:a05:6512:280e:b0:512:a9b7:c637 with SMTP id cf14-20020a056512280e00b00512a9b7c637mr1844941lfb.29.1708693793730; Fri, 23 Feb 2024 05:09:53 -0800 (PST) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, mcb30@ipxe.org Subject: [PATCH v2 1/7] target/i386: mask high bits of CR3 in 32-bit mode Date: Fri, 23 Feb 2024 14:09:42 +0100 Message-ID: <20240223130948.237186-2-pbonzini@redhat.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240223130948.237186-1-pbonzini@redhat.com> References: <20240223130948.237186-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.066, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1708694162177100003 Content-Type: text/plain; charset="utf-8" CR3 bits 63:32 are ignored in 32-bit mode (either legacy 2-level paging or PAE paging). Do this in mmu_translate() to remove the last case where get_physical_address() meaningfully drops the high bits of the address. Suggested-by: Richard Henderson Fixes: 4a1e9d4d11c ("target/i386: Use atomic operations for pte updates", 2= 022-10-18) Signed-off-by: Paolo Bonzini Reviewed-by: Zhao Liu Tested-by: Michael Brown --- target/i386/tcg/sysemu/excp_helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/i386/tcg/sysemu/excp_helper.c b/target/i386/tcg/sysemu/= excp_helper.c index 5b86f439add..11126c860d4 100644 --- a/target/i386/tcg/sysemu/excp_helper.c +++ b/target/i386/tcg/sysemu/excp_helper.c @@ -238,7 +238,7 @@ static bool mmu_translate(CPUX86State *env, const Trans= lateParams *in, /* * Page table level 3 */ - pte_addr =3D ((in->cr3 & ~0x1f) + ((addr >> 27) & 0x18)) & a20= _mask; + pte_addr =3D ((in->cr3 & 0xffffffe0ULL) + ((addr >> 27) & 0x18= )) & a20_mask; if (!ptw_translate(&pte_trans, pte_addr)) { return false; } @@ -306,7 +306,7 @@ static bool mmu_translate(CPUX86State *env, const Trans= lateParams *in, /* * Page table level 2 */ - pte_addr =3D ((in->cr3 & ~0xfff) + ((addr >> 20) & 0xffc)) & a20_m= ask; + pte_addr =3D ((in->cr3 & 0xfffff000ULL) + ((addr >> 20) & 0xffc)) = & a20_mask; if (!ptw_translate(&pte_trans, pte_addr)) { return false; } --=20 2.43.0 From nobody Tue Nov 26 08:25:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1708694120; cv=none; d=zohomail.com; s=zohoarc; b=GsdH9i5xd7re+XItm8+DvVvjMCeZN/vdw7z1yAyO4viECop8AuB+bwe7ltBvNgwVdER8tcjtlzyPtZ+ZOcXc97UxUrFxSxcidOuPPFY7NEbgH+ltURZ1KzYji2qo9lv94cVssYUclDp4gEn057jTDL8a8cHeKARyhjqJKuNDLoU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1708694120; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Fri, 23 Feb 2024 05:09:56 -0800 (PST) X-Google-Smtp-Source: AGHT+IGbyXI8/bhGIX9DCUPFb20uLYdjl2cELwWKjs0UhJhZOocwwcYlvsxqANiT90qMa0wLNg6W0A== X-Received: by 2002:ac2:4842:0:b0:512:a89f:3933 with SMTP id 2-20020ac24842000000b00512a89f3933mr1846837lfy.24.1708693796406; Fri, 23 Feb 2024 05:09:56 -0800 (PST) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, mcb30@ipxe.org Subject: [PATCH v2 2/7] target/i386: check validity of VMCB addresses Date: Fri, 23 Feb 2024 14:09:43 +0100 Message-ID: <20240223130948.237186-3-pbonzini@redhat.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240223130948.237186-1-pbonzini@redhat.com> References: <20240223130948.237186-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.066, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1708694121983100003 Content-Type: text/plain; charset="utf-8" MSR_VM_HSAVE_PA bits 0-11 are reserved, as are the bits above the maximum physical address width of the processor. Setting them to 1 causes a #GP (see "15.30.4 VM_HSAVE_PA MSR" in the AMD manual). The same is true of VMCB addresses passed to VMRUN/VMLOAD/VMSAVE, even though the manual is not clear on that. Fixes: 4a1e9d4d11c ("target/i386: Use atomic operations for pte updates", 2= 022-10-18) Signed-off-by: Paolo Bonzini Tested-by: Michael Brown --- target/i386/tcg/sysemu/misc_helper.c | 3 +++ target/i386/tcg/sysemu/svm_helper.c | 27 +++++++++++++++++++++------ 2 files changed, 24 insertions(+), 6 deletions(-) diff --git a/target/i386/tcg/sysemu/misc_helper.c b/target/i386/tcg/sysemu/= misc_helper.c index 7de0a6e866d..edb7c3d8940 100644 --- a/target/i386/tcg/sysemu/misc_helper.c +++ b/target/i386/tcg/sysemu/misc_helper.c @@ -212,6 +212,9 @@ void helper_wrmsr(CPUX86State *env) tlb_flush(cs); break; case MSR_VM_HSAVE_PA: + if (val & (0xfff | ((~0ULL) << env_archcpu(env)->phys_bits))) { + goto error; + } env->vm_hsave =3D val; break; #ifdef TARGET_X86_64 diff --git a/target/i386/tcg/sysemu/svm_helper.c b/target/i386/tcg/sysemu/s= vm_helper.c index 32ff0dbb13c..5d6de2294fa 100644 --- a/target/i386/tcg/sysemu/svm_helper.c +++ b/target/i386/tcg/sysemu/svm_helper.c @@ -164,14 +164,19 @@ void helper_vmrun(CPUX86State *env, int aflag, int ne= xt_eip_addend) uint64_t new_cr3; uint64_t new_cr4; =20 - cpu_svm_check_intercept_param(env, SVM_EXIT_VMRUN, 0, GETPC()); - if (aflag =3D=3D 2) { addr =3D env->regs[R_EAX]; } else { addr =3D (uint32_t)env->regs[R_EAX]; } =20 + /* Exceptions are checked before the intercept. */ + if (addr & (0xfff | ((~0ULL) << env_archcpu(env)->phys_bits))) { + raise_exception_err_ra(env, EXCP0D_GPF, 0, GETPC()); + } + + cpu_svm_check_intercept_param(env, SVM_EXIT_VMRUN, 0, GETPC()); + qemu_log_mask(CPU_LOG_TB_IN_ASM, "vmrun! " TARGET_FMT_lx "\n", addr); =20 env->vm_vmcb =3D addr; @@ -463,14 +468,19 @@ void helper_vmload(CPUX86State *env, int aflag) int mmu_idx =3D MMU_PHYS_IDX; target_ulong addr; =20 - cpu_svm_check_intercept_param(env, SVM_EXIT_VMLOAD, 0, GETPC()); - if (aflag =3D=3D 2) { addr =3D env->regs[R_EAX]; } else { addr =3D (uint32_t)env->regs[R_EAX]; } =20 + /* Exceptions are checked before the intercept. */ + if (addr & (0xfff | ((~0ULL) << env_archcpu(env)->phys_bits))) { + raise_exception_err_ra(env, EXCP0D_GPF, 0, GETPC()); + } + + cpu_svm_check_intercept_param(env, SVM_EXIT_VMLOAD, 0, GETPC()); + if (virtual_vm_load_save_enabled(env, SVM_EXIT_VMLOAD, GETPC())) { mmu_idx =3D MMU_NESTED_IDX; } @@ -519,14 +529,19 @@ void helper_vmsave(CPUX86State *env, int aflag) int mmu_idx =3D MMU_PHYS_IDX; target_ulong addr; =20 - cpu_svm_check_intercept_param(env, SVM_EXIT_VMSAVE, 0, GETPC()); - if (aflag =3D=3D 2) { addr =3D env->regs[R_EAX]; } else { addr =3D (uint32_t)env->regs[R_EAX]; } =20 + /* Exceptions are checked before the intercept. */ + if (addr & (0xfff | ((~0ULL) << env_archcpu(env)->phys_bits))) { + raise_exception_err_ra(env, EXCP0D_GPF, 0, GETPC()); + } + + cpu_svm_check_intercept_param(env, SVM_EXIT_VMSAVE, 0, GETPC()); + if (virtual_vm_load_save_enabled(env, SVM_EXIT_VMSAVE, GETPC())) { mmu_idx =3D MMU_NESTED_IDX; } --=20 2.43.0 From nobody Tue Nov 26 08:25:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1708693904; cv=none; d=zohomail.com; s=zohoarc; b=WXddOYgumpisI6Xl8QtIBbtjxP11AJTuAKca4mXPqHAJlEaM23JgeCDwilFwPcL9jRz95Ai3ZlcIEDIiRNi13wKniSoAhoY5iJj00arHesc9dOiJnVt1NMdnOvW8bdx9JfXfON6zZqPwzX34QlD3OulKsQqjiyKCaVU57tyfYOQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1708693904; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Fri, 23 Feb 2024 05:10:00 -0800 (PST) X-Google-Smtp-Source: AGHT+IH6ctPWsSITOZkh017u0lakxn8dLN3iAtpvysL3g4XP347kvxf6IuotRPjrhe/wn/Q3b2cE/g== X-Received: by 2002:a05:651c:1a07:b0:2d2:3c88:cd57 with SMTP id by7-20020a05651c1a0700b002d23c88cd57mr1559350ljb.32.1708693799826; Fri, 23 Feb 2024 05:09:59 -0800 (PST) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, mcb30@ipxe.org Subject: [PATCH v2 3/7] target/i386: introduce function to query MMU indices Date: Fri, 23 Feb 2024 14:09:44 +0100 Message-ID: <20240223130948.237186-4-pbonzini@redhat.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240223130948.237186-1-pbonzini@redhat.com> References: <20240223130948.237186-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.066, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1708693905351100001 Content-Type: text/plain; charset="utf-8" Remove knowledge of specific MMU indexes (other than MMU_NESTED_IDX and MMU_PHYS_IDX) from mmu_translate(). This will make it possible to split 32-bit and 64-bit MMU indexes. Signed-off-by: Paolo Bonzini Reviewed-by: Zhao Liu Tested-by: Michael Brown --- target/i386/cpu.h | 10 ++++++++++ target/i386/tcg/sysemu/excp_helper.c | 4 ++-- 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index dfe43b82042..8c271ca62e5 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2305,6 +2305,16 @@ uint64_t cpu_get_tsc(CPUX86State *env); #define MMU_NESTED_IDX 3 #define MMU_PHYS_IDX 4 =20 +static inline bool is_mmu_index_smap(int mmu_index) +{ + return mmu_index =3D=3D MMU_KSMAP_IDX; +} + +static inline bool is_mmu_index_user(int mmu_index) +{ + return mmu_index =3D=3D MMU_USER_IDX; +} + static inline int cpu_mmu_index_kernel(CPUX86State *env) { return !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP_IDX : diff --git a/target/i386/tcg/sysemu/excp_helper.c b/target/i386/tcg/sysemu/= excp_helper.c index 11126c860d4..a0d5ce39300 100644 --- a/target/i386/tcg/sysemu/excp_helper.c +++ b/target/i386/tcg/sysemu/excp_helper.c @@ -137,7 +137,7 @@ static bool mmu_translate(CPUX86State *env, const Trans= lateParams *in, const int32_t a20_mask =3D x86_get_a20_mask(env); const target_ulong addr =3D in->addr; const int pg_mode =3D in->pg_mode; - const bool is_user =3D (in->mmu_idx =3D=3D MMU_USER_IDX); + const bool is_user =3D is_mmu_index_user(in->mmu_idx); const MMUAccessType access_type =3D in->access_type; uint64_t ptep, pte, rsvd_mask; PTETranslate pte_trans =3D { @@ -363,7 +363,7 @@ do_check_protect_pse36: } =20 int prot =3D 0; - if (in->mmu_idx !=3D MMU_KSMAP_IDX || !(ptep & PG_USER_MASK)) { + if (!is_mmu_index_smap(in->mmu_idx) || !(ptep & PG_USER_MASK)) { prot |=3D PAGE_READ; if ((ptep & PG_RW_MASK) || !(is_user || (pg_mode & PG_MODE_WP))) { prot |=3D PAGE_WRITE; --=20 2.43.0 From nobody Tue Nov 26 08:25:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Fri, 23 Feb 2024 05:10:02 -0800 (PST) X-Google-Smtp-Source: AGHT+IGRgR/uJZHjMvnfc8TeK/IA48ymX6CSy2Ilr69bnEh/lJB5w8jWwgMOWQr2ePbdyg3hETSMyg== X-Received: by 2002:ac2:484f:0:b0:512:d91f:95ce with SMTP id 15-20020ac2484f000000b00512d91f95cemr1255447lfy.65.1708693802650; Fri, 23 Feb 2024 05:10:02 -0800 (PST) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, mcb30@ipxe.org Subject: [PATCH v2 4/7] target/i386: use separate MMU indexes for 32-bit accesses Date: Fri, 23 Feb 2024 14:09:45 +0100 Message-ID: <20240223130948.237186-5-pbonzini@redhat.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240223130948.237186-1-pbonzini@redhat.com> References: <20240223130948.237186-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.066, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1708694099980100003 Content-Type: text/plain; charset="utf-8" Accesses from a 32-bit environment (32-bit code segment for instruction accesses, EFER.LMA=3D=3D0 for processor accesses) have to mask away the upper 32 bits of the address. While a bit wasteful, the easiest way to do so is to use separate MMU indexes. These days, QEMU anyway is compiled with a fixed value for NB_MMU_MODES. Split MMU_USER_IDX, MMU_KSMAP_IDX and MMU_KNOSMAP_IDX in two. Signed-off-by: Paolo Bonzini Reviewed-by: Zhao Liu Tested-by: Michael Brown --- target/i386/cpu.h | 34 ++++++++++++++++++++-------- target/i386/cpu.c | 11 +++++---- target/i386/tcg/sysemu/excp_helper.c | 3 ++- 3 files changed, 33 insertions(+), 15 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 8c271ca62e5..ee4ad372021 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2299,27 +2299,41 @@ uint64_t cpu_get_tsc(CPUX86State *env); #define cpu_list x86_cpu_list =20 /* MMU modes definitions */ -#define MMU_KSMAP_IDX 0 -#define MMU_USER_IDX 1 -#define MMU_KNOSMAP_IDX 2 -#define MMU_NESTED_IDX 3 -#define MMU_PHYS_IDX 4 +#define MMU_KSMAP64_IDX 0 +#define MMU_KSMAP32_IDX 1 +#define MMU_USER64_IDX 2 +#define MMU_USER32_IDX 3 +#define MMU_KNOSMAP64_IDX 4 +#define MMU_KNOSMAP32_IDX 5 +#define MMU_PHYS_IDX 6 +#define MMU_NESTED_IDX 7 + +#ifdef CONFIG_USER_ONLY +#ifdef TARGET_X86_64 +#define MMU_USER_IDX MMU_USER64_IDX +#else +#define MMU_USER_IDX MMU_USER32_IDX +#endif +#endif =20 static inline bool is_mmu_index_smap(int mmu_index) { - return mmu_index =3D=3D MMU_KSMAP_IDX; + return (mmu_index & ~1) =3D=3D MMU_KSMAP64_IDX; } =20 static inline bool is_mmu_index_user(int mmu_index) { - return mmu_index =3D=3D MMU_USER_IDX; + return (mmu_index & ~1) =3D=3D MMU_USER64_IDX; } =20 static inline int cpu_mmu_index_kernel(CPUX86State *env) { - return !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP_IDX : - ((env->hflags & HF_CPL_MASK) < 3 && (env->eflags & AC_MASK)) - ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX; + int mmu_index_32 =3D (env->hflags & HF_LMA_MASK) ? 1 : 0; + int mmu_index_base =3D + !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP64_IDX : + ((env->hflags & HF_CPL_MASK) < 3 && (env->eflags & AC_MASK)) ? MMU= _KNOSMAP64_IDX : MMU_KSMAP64_IDX; + + return mmu_index_base + mmu_index_32; } =20 #define CC_DST (env->cc_dst) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 7f908236767..647371198c7 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7732,13 +7732,16 @@ static bool x86_cpu_has_work(CPUState *cs) return x86_cpu_pending_interrupt(cs, cs->interrupt_request) !=3D 0; } =20 -static int x86_cpu_mmu_index(CPUState *cs, bool ifetch) +static int x86_cpu_mmu_index(CPUState *env, bool ifetch) { CPUX86State *env =3D cpu_env(cs); + int mmu_index_32 =3D (env->hflags & HF_CS64_MASK) ? 1 : 0; + int mmu_index_base =3D + (env->hflags & HF_CPL_MASK) =3D=3D 3 ? MMU_USER64_IDX : + !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP64_IDX : + (env->eflags & AC_MASK) ? MMU_KNOSMAP64_IDX : MMU_KSMAP64_IDX; =20 - return (env->hflags & HF_CPL_MASK) =3D=3D 3 ? MMU_USER_IDX : - (!(env->hflags & HF_SMAP_MASK) || (env->eflags & AC_MASK)) - ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX; + return mmu_index_base + mmu_index_32; } =20 static void x86_disas_set_info(CPUState *cs, disassemble_info *info) diff --git a/target/i386/tcg/sysemu/excp_helper.c b/target/i386/tcg/sysemu/= excp_helper.c index a0d5ce39300..b2c525e1a92 100644 --- a/target/i386/tcg/sysemu/excp_helper.c +++ b/target/i386/tcg/sysemu/excp_helper.c @@ -545,7 +545,8 @@ static bool get_physical_address(CPUX86State *env, vadd= r addr, if (likely(use_stage2)) { in.cr3 =3D env->nested_cr3; in.pg_mode =3D env->nested_pg_mode; - in.mmu_idx =3D MMU_USER_IDX; + in.mmu_idx =3D + env->nested_pg_mode & PG_MODE_LMA ? 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Fri, 23 Feb 2024 05:10:05 -0800 (PST) X-Google-Smtp-Source: AGHT+IEIJqa1kCDqzvcX+AZfKIMGR9z8LAdaWECreorePR5UXPeClDga9RvcymOWIITASeL46Arw0w== X-Received: by 2002:a19:4304:0:b0:512:bdd3:150d with SMTP id q4-20020a194304000000b00512bdd3150dmr1214901lfa.52.1708693805139; Fri, 23 Feb 2024 05:10:05 -0800 (PST) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, mcb30@ipxe.org Subject: [PATCH v2 5/7] target/i386: Fix physical address truncation Date: Fri, 23 Feb 2024 14:09:46 +0100 Message-ID: <20240223130948.237186-6-pbonzini@redhat.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240223130948.237186-1-pbonzini@redhat.com> References: <20240223130948.237186-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.066, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1708693987612100007 Content-Type: text/plain; charset="utf-8" The address translation logic in get_physical_address() will currently truncate physical addresses to 32 bits unless long mode is enabled. This is incorrect when using physical address extensions (PAE) outside of long mode, with the result that a 32-bit operating system using PAE to access memory above 4G will experience undefined behaviour. The truncation code was originally introduced in commit 33dfdb5 ("x86: only allow real mode to access 32bit without LMA"), where it applied only to translations performed while paging is disabled (and so cannot affect guests using PAE). Commit 9828198 ("target/i386: Add MMU_PHYS_IDX and MMU_NESTED_IDX") rearranged the code such that the truncation also applied to the use of MMU_PHYS_IDX and MMU_NESTED_IDX. Commit 4a1e9d4 ("target/i386: Use atomic operations for pte updates") brought this truncation into scope for page table entry accesses, and is the first commit for which a Windows 10 32-bit guest will reliably fail to boot if memory above 4G is present. The truncation code however is not completely redundant. Even though the maximum address size for any executed instruction is 32 bits, helpers for operations such as BOUND, FSAVE or XSAVE may ask get_physical_address() to translate an address outside of the 32-bit range, if invoked with an argument that is close to the 4G boundary. Likewise for processor accesses, for example TSS or IDT accesses, when EFER.LMA=3D=3D0. So, move the address truncation in get_physical_address() so that it applies to 32-bit MMU indexes, but not to MMU_PHYS_IDX and MMU_NESTED_IDX. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2040 Fixes: 4a1e9d4d11c ("target/i386: Use atomic operations for pte updates", 2= 022-10-18) Co-developed-by: Michael Brown Signed-off-by: Michael Brown Signed-off-by: Paolo Bonzini Reviewed-by: Zhao Liu Tested-by: Michael Brown --- target/i386/cpu.h | 6 ++++++ target/i386/cpu.c | 2 +- target/i386/tcg/sysemu/excp_helper.c | 12 +++++------- 3 files changed, 12 insertions(+), 8 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index ee4ad372021..8a165889de6 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2326,6 +2326,12 @@ static inline bool is_mmu_index_user(int mmu_index) return (mmu_index & ~1) =3D=3D MMU_USER64_IDX; } =20 +static inline bool is_mmu_index_32(int mmu_index) +{ + assert(mmu_index < MMU_PHYS_IDX); + return mmu_index & 1; +} + static inline int cpu_mmu_index_kernel(CPUX86State *env) { int mmu_index_32 =3D (env->hflags & HF_LMA_MASK) ? 1 : 0; diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 647371198c7..ba6d7b80a7f 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7732,7 +7732,7 @@ static bool x86_cpu_has_work(CPUState *cs) return x86_cpu_pending_interrupt(cs, cs->interrupt_request) !=3D 0; } =20 -static int x86_cpu_mmu_index(CPUState *env, bool ifetch) +static int x86_cpu_mmu_index(CPUState *cs, bool ifetch) { CPUX86State *env =3D cpu_env(cs); int mmu_index_32 =3D (env->hflags & HF_CS64_MASK) ? 1 : 0; diff --git a/target/i386/tcg/sysemu/excp_helper.c b/target/i386/tcg/sysemu/= excp_helper.c index b2c525e1a92..8bcdd2906d5 100644 --- a/target/i386/tcg/sysemu/excp_helper.c +++ b/target/i386/tcg/sysemu/excp_helper.c @@ -558,6 +558,10 @@ static bool get_physical_address(CPUX86State *env, vad= dr addr, break; =20 default: + if (is_mmu_index_32(mmu_idx)) { + addr =3D (uint32_t)addr; + } + if (likely(env->cr[0] & CR0_PG_MASK)) { in.cr3 =3D env->cr[3]; in.mmu_idx =3D mmu_idx; @@ -581,14 +585,8 @@ static bool get_physical_address(CPUX86State *env, vad= dr addr, break; } =20 - /* Translation disabled. */ + /* No translation needed. */ out->paddr =3D addr & x86_get_a20_mask(env); -#ifdef TARGET_X86_64 - if (!(env->hflags & HF_LMA_MASK)) { - /* Without long mode we can only address 32bits in real mode */ - out->paddr =3D (uint32_t)out->paddr; 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Fri, 23 Feb 2024 05:10:09 -0800 (PST) X-Google-Smtp-Source: AGHT+IG/17Hzai2aF6IpN1JeVAujUYEnr9TXJ5hfb32xxXPplJ4No4SSWzxTDHIXWEbSX1cWdo+L4A== X-Received: by 2002:a19:e005:0:b0:512:be87:af7 with SMTP id x5-20020a19e005000000b00512be870af7mr1225884lfg.46.1708693808507; Fri, 23 Feb 2024 05:10:08 -0800 (PST) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, mcb30@ipxe.org Subject: [PATCH v2 6/7] target/i386: remove unnecessary/wrong application of the A20 mask Date: Fri, 23 Feb 2024 14:09:47 +0100 Message-ID: <20240223130948.237186-7-pbonzini@redhat.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240223130948.237186-1-pbonzini@redhat.com> References: <20240223130948.237186-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.066, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1708694162186100004 Content-Type: text/plain; charset="utf-8" If ptw_translate() does a MMU_PHYS_IDX access, the A20 mask is already applied in get_physical_address(), which is called via probe_access_full() and x86_cpu_tlb_fill(). If ptw_translate() on the other hand does a MMU_NESTED_IDX access, the A20 mask must not be applied to the address that is looked up in the nested page tables; it must be applied only to the addresses that hold the NPT entries (which is achieved via MMU_PHYS_IDX, per the previous paragraph). Therefore, we can remove A20 masking from the computation of the page table entry's address, and let get_physical_address() or mmu_translate() apply it when they know they are returning a host-physical address. Fixes: 4a1e9d4d11c ("target/i386: Use atomic operations for pte updates", 2= 022-10-18) Signed-off-by: Paolo Bonzini Tested-by: Michael Brown --- target/i386/tcg/sysemu/excp_helper.c | 21 ++++++++------------- 1 file changed, 8 insertions(+), 13 deletions(-) diff --git a/target/i386/tcg/sysemu/excp_helper.c b/target/i386/tcg/sysemu/= excp_helper.c index 8bcdd2906d5..2ddc08b4bb6 100644 --- a/target/i386/tcg/sysemu/excp_helper.c +++ b/target/i386/tcg/sysemu/excp_helper.c @@ -164,8 +164,7 @@ static bool mmu_translate(CPUX86State *env, const Trans= lateParams *in, /* * Page table level 5 */ - pte_addr =3D ((in->cr3 & ~0xfff) + - (((addr >> 48) & 0x1ff) << 3)) & a20_mask; + pte_addr =3D (in->cr3 & ~0xfff) + (((addr >> 48) & 0x1ff) = << 3); if (!ptw_translate(&pte_trans, pte_addr)) { return false; } @@ -189,8 +188,7 @@ static bool mmu_translate(CPUX86State *env, const Trans= lateParams *in, /* * Page table level 4 */ - pte_addr =3D ((pte & PG_ADDRESS_MASK) + - (((addr >> 39) & 0x1ff) << 3)) & a20_mask; + pte_addr =3D (pte & PG_ADDRESS_MASK) + (((addr >> 39) & 0x1ff)= << 3); if (!ptw_translate(&pte_trans, pte_addr)) { return false; } @@ -210,8 +208,7 @@ static bool mmu_translate(CPUX86State *env, const Trans= lateParams *in, /* * Page table level 3 */ - pte_addr =3D ((pte & PG_ADDRESS_MASK) + - (((addr >> 30) & 0x1ff) << 3)) & a20_mask; + pte_addr =3D (pte & PG_ADDRESS_MASK) + (((addr >> 30) & 0x1ff)= << 3); if (!ptw_translate(&pte_trans, pte_addr)) { return false; } @@ -238,7 +235,7 @@ static bool mmu_translate(CPUX86State *env, const Trans= lateParams *in, /* * Page table level 3 */ - pte_addr =3D ((in->cr3 & 0xffffffe0ULL) + ((addr >> 27) & 0x18= )) & a20_mask; + pte_addr =3D (in->cr3 & 0xffffffe0ULL) + ((addr >> 27) & 0x18); if (!ptw_translate(&pte_trans, pte_addr)) { return false; } @@ -260,8 +257,7 @@ static bool mmu_translate(CPUX86State *env, const Trans= lateParams *in, /* * Page table level 2 */ - pte_addr =3D ((pte & PG_ADDRESS_MASK) + - (((addr >> 21) & 0x1ff) << 3)) & a20_mask; + pte_addr =3D (pte & PG_ADDRESS_MASK) + (((addr >> 21) & 0x1ff) << = 3); if (!ptw_translate(&pte_trans, pte_addr)) { return false; } @@ -287,8 +283,7 @@ static bool mmu_translate(CPUX86State *env, const Trans= lateParams *in, /* * Page table level 1 */ - pte_addr =3D ((pte & PG_ADDRESS_MASK) + - (((addr >> 12) & 0x1ff) << 3)) & a20_mask; + pte_addr =3D (pte & PG_ADDRESS_MASK) + (((addr >> 12) & 0x1ff) << = 3); if (!ptw_translate(&pte_trans, pte_addr)) { return false; } @@ -306,7 +301,7 @@ static bool mmu_translate(CPUX86State *env, const Trans= lateParams *in, /* * Page table level 2 */ - pte_addr =3D ((in->cr3 & 0xfffff000ULL) + ((addr >> 20) & 0xffc)) = & a20_mask; + pte_addr =3D (in->cr3 & 0xfffff000ULL) + ((addr >> 20) & 0xffc); if (!ptw_translate(&pte_trans, pte_addr)) { return false; } @@ -335,7 +330,7 @@ static bool mmu_translate(CPUX86State *env, const Trans= lateParams *in, /* * Page table level 1 */ - pte_addr =3D ((pte & ~0xfffu) + ((addr >> 10) & 0xffc)) & a20_mask; + pte_addr =3D (pte & ~0xfffu) + ((addr >> 10) & 0xffc); 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Fri, 23 Feb 2024 05:10:10 -0800 (PST) X-Google-Smtp-Source: AGHT+IElP3c5/uDGrDGmeAi97RUXbnQQgyKcu1VdqWxjWVIWvgYhFWLy7diaD3riy6szGHec702ezw== X-Received: by 2002:a2e:a78e:0:b0:2d2:39ab:eee1 with SMTP id c14-20020a2ea78e000000b002d239abeee1mr1705178ljf.32.1708693810148; Fri, 23 Feb 2024 05:10:10 -0800 (PST) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, mcb30@ipxe.org Subject: [PATCH v2 7/7] target/i386: leave the A20 bit set in the final NPT walk Date: Fri, 23 Feb 2024 14:09:48 +0100 Message-ID: <20240223130948.237186-8-pbonzini@redhat.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240223130948.237186-1-pbonzini@redhat.com> References: <20240223130948.237186-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.066, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1708694087956100001 Content-Type: text/plain; charset="utf-8" The A20 mask is only applied to the final memory access. Nested page tables are always walked with the raw guest-physical address. Unlike the previous patch, in this one the masking must be kept, but it was done too early. Fixes: 4a1e9d4d11c ("target/i386: Use atomic operations for pte updates", 2= 022-10-18) Signed-off-by: Paolo Bonzini Tested-by: Michael Brown --- target/i386/tcg/sysemu/excp_helper.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/target/i386/tcg/sysemu/excp_helper.c b/target/i386/tcg/sysemu/= excp_helper.c index 2ddc08b4bb6..8f7011d9663 100644 --- a/target/i386/tcg/sysemu/excp_helper.c +++ b/target/i386/tcg/sysemu/excp_helper.c @@ -134,7 +134,6 @@ static inline bool ptw_setl(const PTETranslate *in, uin= t32_t old, uint32_t set) static bool mmu_translate(CPUX86State *env, const TranslateParams *in, TranslateResult *out, TranslateFault *err) { - const int32_t a20_mask =3D x86_get_a20_mask(env); const target_ulong addr =3D in->addr; const int pg_mode =3D in->pg_mode; const bool is_user =3D is_mmu_index_user(in->mmu_idx); @@ -417,10 +416,13 @@ do_check_protect_pse36: } } =20 - /* align to page_size */ - paddr =3D (pte & a20_mask & PG_ADDRESS_MASK & ~(page_size - 1)) - | (addr & (page_size - 1)); + /* merge offset within page */ + paddr =3D (pte & PG_ADDRESS_MASK & ~(page_size - 1)) | (addr & (page_s= ize - 1)); =20 + /* + * Note that NPT is walked (for both paging structures and final guest + * addresses) using the address with the A20 bit set. + */ if (in->ptw_idx =3D=3D MMU_NESTED_IDX) { CPUTLBEntryFull *full; int flags, nested_page_size; @@ -459,7 +461,7 @@ do_check_protect_pse36: } } =20 - out->paddr =3D paddr; + out->paddr =3D paddr & x86_get_a20_mask(env); out->prot =3D prot; out->page_size =3D page_size; return true; --=20 2.43.0