From nobody Tue Nov 26 10:39:05 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1708684651; cv=none; d=zohomail.com; s=zohoarc; b=HDUU59b4bzN5KCMOEFSO03yBS12FDzOKgBJ6gGmXkMFwYCUJiUhp7axU5Xc47CaeDcH+803hww4GUf//H98H8h0zl0YUqnGLI//Wuz2SgBToL4UK9qBSZsSlBYPSffKan81qtbdJTsBWuxoVqiBAJqVr/Kgrws6LLMTxlK0VB1o= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1708684651; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=I31I7PNlT8l0yu6sMTs/gx1em9tUJzHwmFltErIrEVA=; b=ULW+H5+UA9KRsvVqGgEe33coay2yk8W1IO7TM8R+HL2PGVMToITfTNYgOwbiUqhWW8amAk4uHC/bC8m9nPpW5im3jgO8uMsMKt3DiW8uoCdMQ9hBvJjvQ2J0BgQXlCFWyn9M0xGaldQNMDajhQ2Sbjc5YnDcj7cy91o7OfNbvlI= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1708684651884532.4726845091504; Fri, 23 Feb 2024 02:37:31 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rdSst-0003nq-R3; Fri, 23 Feb 2024 05:34:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rdSsX-0003ds-7c; Fri, 23 Feb 2024 05:34:06 -0500 Received: from szxga05-in.huawei.com ([45.249.212.191]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rdSsP-0001w7-Jw; Fri, 23 Feb 2024 05:34:04 -0500 Received: from mail.maildlp.com (unknown [172.19.88.214]) by szxga05-in.huawei.com (SkyGuard) with ESMTP id 4Th5p62cf2z1FHw0; Fri, 23 Feb 2024 18:28:46 +0800 (CST) Received: from kwepemi500008.china.huawei.com (unknown [7.221.188.139]) by mail.maildlp.com (Postfix) with ESMTPS id 3AF7D1A016B; Fri, 23 Feb 2024 18:33:40 +0800 (CST) Received: from huawei.com (10.67.174.55) by kwepemi500008.china.huawei.com (7.221.188.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.35; Fri, 23 Feb 2024 18:33:39 +0800 To: , , , , , , CC: Subject: [RFC PATCH v3 06/21] target/arm: Add support for Non-maskable Interrupt Date: Fri, 23 Feb 2024 10:32:06 +0000 Message-ID: <20240223103221.1142518-7-ruanjinjie@huawei.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240223103221.1142518-1-ruanjinjie@huawei.com> References: <20240223103221.1142518-1-ruanjinjie@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.67.174.55] X-ClientProxiedBy: dggems706-chm.china.huawei.com (10.3.19.183) To kwepemi500008.china.huawei.com (7.221.188.139) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=45.249.212.191; envelope-from=ruanjinjie@huawei.com; helo=szxga05-in.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jinjie Ruan From: Jinjie Ruan via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1708684652617100009 Content-Type: text/plain; charset="utf-8" This only implements the external delivery method via the GICv3. Signed-off-by: Jinjie Ruan --- v3: - Not include CPU_INTERRUPT_NMI when FEAT_NMI not enabled - Add ARM_CPU_VNMI. - Refator nmi mask in arm_excp_unmasked(). - Test SCTLR_ELx.NMI for ALLINT mask for NMI. --- target/arm/cpu-qom.h | 4 +++- target/arm/cpu.c | 54 ++++++++++++++++++++++++++++++++++++-------- target/arm/cpu.h | 4 ++++ target/arm/helper.c | 2 ++ 4 files changed, 54 insertions(+), 10 deletions(-) diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h index 8e032691db..e0c9e18036 100644 --- a/target/arm/cpu-qom.h +++ b/target/arm/cpu-qom.h @@ -36,11 +36,13 @@ DECLARE_CLASS_CHECKERS(AArch64CPUClass, AARCH64_CPU, #define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU #define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX) =20 -/* Meanings of the ARMCPU object's four inbound GPIO lines */ +/* Meanings of the ARMCPU object's six inbound GPIO lines */ #define ARM_CPU_IRQ 0 #define ARM_CPU_FIQ 1 #define ARM_CPU_VIRQ 2 #define ARM_CPU_VFIQ 3 +#define ARM_CPU_NMI 4 +#define ARM_CPU_VNMI 5 =20 /* For M profile, some registers are banked secure vs non-secure; * these are represented as a 2-element array where the first element diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 5fa86bc8d5..d40ada9c75 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -126,11 +126,20 @@ static bool arm_cpu_has_work(CPUState *cs) { ARMCPU *cpu =3D ARM_CPU(cs); =20 - return (cpu->power_state !=3D PSCI_OFF) - && cs->interrupt_request & - (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD - | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ | CPU_INTERRUPT_VSERR - | CPU_INTERRUPT_EXITTB); + if (cpu_isar_feature(aa64_nmi, cpu)) { + return (cpu->power_state !=3D PSCI_OFF) + && cs->interrupt_request & + (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD + | CPU_INTERRUPT_NMI | CPU_INTERRUPT_VNMI + | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ | CPU_INTERRUPT_VSE= RR + | CPU_INTERRUPT_EXITTB); + } else { + return (cpu->power_state !=3D PSCI_OFF) + && cs->interrupt_request & + (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD + | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ | CPU_INTERRUPT_VSE= RR + | CPU_INTERRUPT_EXITTB); + } } =20 static int arm_cpu_mmu_index(CPUState *cs, bool ifetch) @@ -668,6 +677,7 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsi= gned int excp_idx, CPUARMState *env =3D cpu_env(cs); bool pstate_unmasked; bool unmasked =3D false; + bool nmi_unmasked =3D true; =20 /* * Don't take exceptions if they target a lower EL. @@ -678,13 +688,26 @@ static inline bool arm_excp_unmasked(CPUState *cs, un= signed int excp_idx, return false; } =20 + if (cpu_isar_feature(aa64_nmi, env_archcpu(env))) { + nmi_unmasked =3D (cur_el =3D=3D target_el) && + (((env->cp15.sctlr_el[target_el] & SCTLR_NMI) && + (env->allint & PSTATE_ALLINT)) || + ((env->cp15.sctlr_el[target_el] & SCTLR_SPINTMASK)= && + (env->pstate & PSTATE_SP))); + nmi_unmasked =3D !nmi_unmasked; + } + switch (excp_idx) { + case EXCP_NMI: + pstate_unmasked =3D nmi_unmasked; + break; + case EXCP_FIQ: - pstate_unmasked =3D !(env->daif & PSTATE_F); + pstate_unmasked =3D (!(env->daif & PSTATE_F)) & nmi_unmasked; break; =20 case EXCP_IRQ: - pstate_unmasked =3D !(env->daif & PSTATE_I); + pstate_unmasked =3D (!(env->daif & PSTATE_I)) & nmi_unmasked; break; =20 case EXCP_VFIQ: @@ -804,6 +827,16 @@ static bool arm_cpu_exec_interrupt(CPUState *cs, int i= nterrupt_request) =20 /* The prioritization of interrupts is IMPLEMENTATION DEFINED. */ =20 + if (cpu_isar_feature(aa64_nmi, env_archcpu(env))) { + if (interrupt_request & CPU_INTERRUPT_NMI) { + excp_idx =3D EXCP_NMI; + target_el =3D arm_phys_excp_target_el(cs, excp_idx, cur_el, se= cure); + if (arm_excp_unmasked(cs, excp_idx, target_el, + cur_el, secure, hcr_el2)) { + goto found; + } + } + } if (interrupt_request & CPU_INTERRUPT_FIQ) { excp_idx =3D EXCP_FIQ; target_el =3D arm_phys_excp_target_el(cs, excp_idx, cur_el, secure= ); @@ -929,7 +962,9 @@ static void arm_cpu_set_irq(void *opaque, int irq, int = level) [ARM_CPU_IRQ] =3D CPU_INTERRUPT_HARD, [ARM_CPU_FIQ] =3D CPU_INTERRUPT_FIQ, [ARM_CPU_VIRQ] =3D CPU_INTERRUPT_VIRQ, - [ARM_CPU_VFIQ] =3D CPU_INTERRUPT_VFIQ + [ARM_CPU_VFIQ] =3D CPU_INTERRUPT_VFIQ, + [ARM_CPU_NMI] =3D CPU_INTERRUPT_NMI, + [ARM_CPU_VNMI] =3D CPU_INTERRUPT_VNMI }; =20 if (!arm_feature(env, ARM_FEATURE_EL2) && @@ -957,6 +992,7 @@ static void arm_cpu_set_irq(void *opaque, int irq, int = level) break; case ARM_CPU_IRQ: case ARM_CPU_FIQ: + case ARM_CPU_NMI: if (level) { cpu_interrupt(cs, mask[irq]); } else { @@ -1355,7 +1391,7 @@ static void arm_cpu_initfn(Object *obj) */ qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4); } else { - qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4); + qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 6); } =20 qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs, diff --git a/target/arm/cpu.h b/target/arm/cpu.h index f9646dbbfb..b23be7fc24 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -60,6 +60,8 @@ #define EXCP_DIVBYZERO 23 /* v7M DIVBYZERO UsageFault */ #define EXCP_VSERR 24 #define EXCP_GPC 25 /* v9 Granule Protection Check Fault */ +#define EXCP_NMI 26 +#define EXCP_VNMI 27 /* NB: add new EXCP_ defines to the array in arm_log_exception() too */ =20 #define ARMV7M_EXCP_RESET 1 @@ -79,6 +81,8 @@ #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2 #define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3 #define CPU_INTERRUPT_VSERR CPU_INTERRUPT_TGT_INT_0 +#define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_4 +#define CPU_INTERRUPT_VNMI CPU_INTERRUPT_TGT_EXT_0 =20 /* The usual mapping for an AArch64 system register to its AArch32 * counterpart is for the 32 bit world to have access to the lower diff --git a/target/arm/helper.c b/target/arm/helper.c index b01f23b939..376e0d91ff 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10629,6 +10629,8 @@ void arm_log_exception(CPUState *cs) [EXCP_DIVBYZERO] =3D "v7M DIVBYZERO UsageFault", [EXCP_VSERR] =3D "Virtual SERR", [EXCP_GPC] =3D "Granule Protection Check", + [EXCP_NMI] =3D "NMI", + [EXCP_VNMI] =3D "virtual NMI" }; =20 if (idx >=3D 0 && idx < ARRAY_SIZE(excnames)) { --=20 2.34.1