From nobody Mon Feb 9 19:40:33 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1708684748; cv=none; d=zohomail.com; s=zohoarc; b=O4+f4bLuiEijftxji1isig656nxaHbB0MFyjaLtRA9prZkeWOUswzhIFHx45bHlZnkTcCtB1slCADjuItCzthYKGmarX1C0oJKM6Iqni6ub079OKbj6ajFSFLk/ETijovNrsrLw1+aT93+7zIawRBImLBo8BFeYQ10PJ5lgQ5Ig= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1708684748; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=mCTxOPPl1INGB9MTJ3WPY43KqYBXQ9q/npvKny6REuE=; b=N+4iWhvp4Vz6iGwGZK3u64En6/YzPXa3Daql8l6ln2ecEzQNSO4m5idTf2XSxyCzR7hxZ0mQNnQjsQmI7z/5+AF0L9dP3AW5hi7OJafKOEmHxV25Xc9Yyo4theiGqs6X+0Tpwha8hbQpdnDwtZSNwqonS03lZZnGt2dzbvJAW4g= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1708684748820734.385149728915; Fri, 23 Feb 2024 02:39:08 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rdSu3-0005Fz-9y; Fri, 23 Feb 2024 05:35:39 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rdSsZ-0003fZ-65; Fri, 23 Feb 2024 05:34:08 -0500 Received: from szxga05-in.huawei.com ([45.249.212.191]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rdSsW-0001yk-8q; Fri, 23 Feb 2024 05:34:06 -0500 Received: from mail.maildlp.com (unknown [172.19.88.214]) by szxga05-in.huawei.com (SkyGuard) with ESMTP id 4Th5pH5gLLz1FLHj; Fri, 23 Feb 2024 18:28:55 +0800 (CST) Received: from kwepemi500008.china.huawei.com (unknown [7.221.188.139]) by mail.maildlp.com (Postfix) with ESMTPS id A338D1A016B; Fri, 23 Feb 2024 18:33:49 +0800 (CST) Received: from huawei.com (10.67.174.55) by kwepemi500008.china.huawei.com (7.221.188.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.35; Fri, 23 Feb 2024 18:33:49 +0800 To: , , , , , , CC: Subject: [RFC PATCH v3 17/21] hw/intc/arm_gicv3: Add NMI handling CPU interface registers Date: Fri, 23 Feb 2024 10:32:17 +0000 Message-ID: <20240223103221.1142518-18-ruanjinjie@huawei.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240223103221.1142518-1-ruanjinjie@huawei.com> References: <20240223103221.1142518-1-ruanjinjie@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.67.174.55] X-ClientProxiedBy: dggems706-chm.china.huawei.com (10.3.19.183) To kwepemi500008.china.huawei.com (7.221.188.139) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=45.249.212.191; envelope-from=ruanjinjie@huawei.com; helo=szxga05-in.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jinjie Ruan From: Jinjie Ruan via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1708684750933100003 Content-Type: text/plain; charset="utf-8" Add the NMIAR CPU interface registers which deal with acknowledging NMI. When introduce NMI interrupt, there are some updates to the semantics for t= he register ICC_IAR1_EL1 and ICC_HPPIR1_EL1. For ICC_IAR1_EL1 register, it should return 1022 if the intid has super priority. And for ICC_NMIAR1_EL1 register, it should return 1023 if the intid do not have super priority. Howerever, these are not necessary for ICC_HPPIR1_EL1 register. Signed-off-by: Jinjie Ruan --- hw/intc/arm_gicv3_cpuif.c | 46 ++++++++++++++++++++++++++++++++++++--- hw/intc/gicv3_internal.h | 1 + 2 files changed, 44 insertions(+), 3 deletions(-) diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c index e1a60d8c15..f5bf8df32b 100644 --- a/hw/intc/arm_gicv3_cpuif.c +++ b/hw/intc/arm_gicv3_cpuif.c @@ -1097,7 +1097,8 @@ static uint64_t icc_hppir0_value(GICv3CPUState *cs, C= PUARMState *env) return cs->hppi.irq; } =20 -static uint64_t icc_hppir1_value(GICv3CPUState *cs, CPUARMState *env) +static uint64_t icc_hppir1_value(GICv3CPUState *cs, CPUARMState *env, + bool is_nmi, bool is_hppi) { /* Return the highest priority pending interrupt register value * for group 1. @@ -1108,6 +1109,16 @@ static uint64_t icc_hppir1_value(GICv3CPUState *cs, = CPUARMState *env) return INTID_SPURIOUS; } =20 + if (!is_hppi) { + if (is_nmi && (!cs->hppi.superprio)) { + return INTID_SPURIOUS; + } + + if ((!is_nmi) && cs->hppi.superprio) { + return INTID_NMI; + } + } + /* Check whether we can return the interrupt or if we should return * a special identifier, as per the CheckGroup1ForSpecialIdentifiers * pseudocode. (We can simplify a little because for us ICC_SRE_EL1.RM @@ -1168,7 +1179,30 @@ static uint64_t icc_iar1_read(CPUARMState *env, cons= t ARMCPRegInfo *ri) if (!icc_hppi_can_preempt(cs)) { intid =3D INTID_SPURIOUS; } else { - intid =3D icc_hppir1_value(cs, env); + intid =3D icc_hppir1_value(cs, env, false, false); + } + + if (!gicv3_intid_is_special(intid)) { + icc_activate_irq(cs, intid); + } + + trace_gicv3_icc_iar1_read(gicv3_redist_affid(cs), intid); + return intid; +} + +static uint64_t icc_nmiar1_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + GICv3CPUState *cs =3D icc_cs_from_env(env); + uint64_t intid; + + if (icv_access(env, HCR_IMO)) { + return icv_iar_read(env, ri); + } + + if (!icc_hppi_can_preempt(cs)) { + intid =3D INTID_SPURIOUS; + } else { + intid =3D icc_hppir1_value(cs, env, true, false); } =20 if (!gicv3_intid_is_special(intid)) { @@ -1555,7 +1589,7 @@ static uint64_t icc_hppir1_read(CPUARMState *env, con= st ARMCPRegInfo *ri) return icv_hppir_read(env, ri); } =20 - value =3D icc_hppir1_value(cs, env); + value =3D icc_hppir1_value(cs, env, false, true); trace_gicv3_icc_hppir1_read(gicv3_redist_affid(cs), value); return value; } @@ -2344,6 +2378,12 @@ static const ARMCPRegInfo gicv3_cpuif_reginfo[] =3D { .access =3D PL1_R, .accessfn =3D gicv3_irq_access, .readfn =3D icc_iar1_read, }, + { .name =3D "ICC_NMIAR1_EL1", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 12, .crm =3D 9, .opc2 =3D 5, + .type =3D ARM_CP_IO | ARM_CP_NO_RAW, + .access =3D PL1_R, .accessfn =3D gicv3_irq_access, + .readfn =3D icc_nmiar1_read, + }, { .name =3D "ICC_EOIR1_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 12, .crm =3D 12, .opc2 =3D 1, .type =3D ARM_CP_IO | ARM_CP_NO_RAW, diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h index 8d793243f4..93e56b3726 100644 --- a/hw/intc/gicv3_internal.h +++ b/hw/intc/gicv3_internal.h @@ -511,6 +511,7 @@ FIELD(VTE, RDBASE, 42, RDBASE_PROCNUM_LENGTH) /* Special interrupt IDs */ #define INTID_SECURE 1020 #define INTID_NONSECURE 1021 +#define INTID_NMI 1022 #define INTID_SPURIOUS 1023 =20 /* Functions internal to the emulated GICv3 */ --=20 2.34.1