From nobody Tue Nov 26 10:48:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1708684548; cv=none; d=zohomail.com; s=zohoarc; b=L/JsVRoYR9vKJHlT0c2Y21AKNvR7o3Kxi2hMSgaWw4A2rbcPArWSUmMDjfSCAOOobWkdipossWkQQo276ceDwkLsgxqjSBKSrqPoYrRfF9zyYX/NU6jLkaRg75bpO5mA9Yv5M+4K3tn9FPxEhB2tVWnNX0NIzgOpdCIxffsjrlA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1708684548; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=mu6CWHfun1+q4bT7NKwsgJI/lsseRig06ac4YH8RJo8=; b=l/XfBrsTuR9345C6mm1qQKE1Sa8ejRPop2HDuN9TCu4fan8fTqHfiw000l7DHZc7Jf2YDpb3lAWnELAo3bQK5KXZJAXxvmeV8xPnMzhO12KTRR6BUxqewHYFYPcCaYjY1u4bMr2Og3zq884wznJ9hoDaJ3rH82TFqYCGiwLLS3Q= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1708684548486424.8409145231186; Fri, 23 Feb 2024 02:35:48 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rdSsr-0003nT-4T; Fri, 23 Feb 2024 05:34:25 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rdSsY-0003e1-3p; Fri, 23 Feb 2024 05:34:06 -0500 Received: from szxga05-in.huawei.com ([45.249.212.191]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rdSsV-0001yj-8n; Fri, 23 Feb 2024 05:34:05 -0500 Received: from mail.maildlp.com (unknown [172.19.88.214]) by szxga05-in.huawei.com (SkyGuard) with ESMTP id 4Th5pG6dzQz1FLHM; Fri, 23 Feb 2024 18:28:54 +0800 (CST) Received: from kwepemi500008.china.huawei.com (unknown [7.221.188.139]) by mail.maildlp.com (Postfix) with ESMTPS id C626C1A016B; Fri, 23 Feb 2024 18:33:48 +0800 (CST) Received: from huawei.com (10.67.174.55) by kwepemi500008.china.huawei.com (7.221.188.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.35; Fri, 23 Feb 2024 18:33:48 +0800 To: , , , , , , CC: Subject: [RFC PATCH v3 16/21] hw/intc: Enable FEAT_GICv3_NMI Feature Date: Fri, 23 Feb 2024 10:32:16 +0000 Message-ID: <20240223103221.1142518-17-ruanjinjie@huawei.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240223103221.1142518-1-ruanjinjie@huawei.com> References: <20240223103221.1142518-1-ruanjinjie@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.67.174.55] X-ClientProxiedBy: dggems706-chm.china.huawei.com (10.3.19.183) To kwepemi500008.china.huawei.com (7.221.188.139) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=45.249.212.191; envelope-from=ruanjinjie@huawei.com; helo=szxga05-in.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jinjie Ruan From: Jinjie Ruan via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1708684550367100011 Content-Type: text/plain; charset="utf-8" Added properties to enable FEAT_GICv3_NMI feature, setup distributor and redistributor registers to indicate NMI support. Signed-off-by: Jinjie Ruan Reviewed-by: Richard Henderson --- hw/intc/arm_gicv3_common.c | 1 + hw/intc/arm_gicv3_dist.c | 2 ++ hw/intc/gicv3_internal.h | 1 + include/hw/intc/arm_gicv3_common.h | 1 + 4 files changed, 5 insertions(+) diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c index c52f060026..2d2cea6858 100644 --- a/hw/intc/arm_gicv3_common.c +++ b/hw/intc/arm_gicv3_common.c @@ -569,6 +569,7 @@ static Property arm_gicv3_common_properties[] =3D { DEFINE_PROP_UINT32("num-irq", GICv3State, num_irq, 32), DEFINE_PROP_UINT32("revision", GICv3State, revision, 3), DEFINE_PROP_BOOL("has-lpi", GICv3State, lpi_enable, 0), + DEFINE_PROP_BOOL("has-nmi", GICv3State, nmi_support, 0), DEFINE_PROP_BOOL("has-security-extensions", GICv3State, security_extn,= 0), /* * Compatibility property: force 8 bits of physical priority, even diff --git a/hw/intc/arm_gicv3_dist.c b/hw/intc/arm_gicv3_dist.c index 2f7280c524..65e7ca29cf 100644 --- a/hw/intc/arm_gicv3_dist.c +++ b/hw/intc/arm_gicv3_dist.c @@ -412,6 +412,7 @@ static bool gicd_readl(GICv3State *s, hwaddr offset, * by GICD_TYPER.IDbits) * MBIS =3D=3D 0 (message-based SPIs not supported) * SecurityExtn =3D=3D 1 if security extns supported + * NMI =3D 1 if Non-maskable interrupt property is supported * CPUNumber =3D=3D 0 since for us ARE is always 1 * ITLinesNumber =3D=3D (((max SPI IntID + 1) / 32) - 1) */ @@ -425,6 +426,7 @@ static bool gicd_readl(GICv3State *s, hwaddr offset, bool dvis =3D s->revision >=3D 4; =20 *data =3D (1 << 25) | (1 << 24) | (dvis << 18) | (sec_extn << 10) | + (s->nmi_support << GICD_TYPER_NMI_SHIFT) | (s->lpi_enable << GICD_TYPER_LPIS_SHIFT) | (0xf << 19) | itlinesnumber; return true; diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h index a1fc34597e..8d793243f4 100644 --- a/hw/intc/gicv3_internal.h +++ b/hw/intc/gicv3_internal.h @@ -70,6 +70,7 @@ #define GICD_CTLR_E1NWF (1U << 7) #define GICD_CTLR_RWP (1U << 31) =20 +#define GICD_TYPER_NMI_SHIFT 9 #define GICD_TYPER_LPIS_SHIFT 17 =20 /* 16 bits EventId */ diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3= _common.h index df4380141d..16c5fa7256 100644 --- a/include/hw/intc/arm_gicv3_common.h +++ b/include/hw/intc/arm_gicv3_common.h @@ -251,6 +251,7 @@ struct GICv3State { uint32_t num_irq; uint32_t revision; bool lpi_enable; + bool nmi_support; bool security_extn; bool force_8bit_prio; bool irq_reset_nonsecure; --=20 2.34.1