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Wed, 21 Feb 2024 13:32:04 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, richard.henderson@linaro.org, max.chou@sifive.com, Daniel Henrique Barboza Subject: [PATCH v6 5/9] target/riscv: remove 'cpu_vl' global Date: Wed, 21 Feb 2024 18:31:36 -0300 Message-ID: <20240221213140.365232-6-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240221213140.365232-1-dbarboza@ventanamicro.com> References: <20240221213140.365232-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=dbarboza@ventanamicro.com; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1708551282505100003 Content-Type: text/plain; charset="utf-8" At this moment the global is used only in do_vsetvl(). Do a direct env load in do_vsetvl() to read 'vl' and remove the global. Suggested-by: Richard Henderson Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/riscv/insn_trans/trans_rvv.c.inc | 2 +- target/riscv/translate.c | 3 +-- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr= ans/trans_rvv.c.inc index 58299d9bb8..69f32d081e 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -157,7 +157,7 @@ static bool do_vsetvl(DisasContext *s, int rd, int rs1,= TCGv s2) =20 if (rd =3D=3D 0 && rs1 =3D=3D 0) { s1 =3D tcg_temp_new(); - tcg_gen_mov_tl(s1, cpu_vl); + tcg_gen_ld_tl(s1, tcg_env, offsetof(CPURISCVState, vl)); } else if (rs1 =3D=3D 0) { /* As the mask is at least one bit, RV_VLEN_MAX is >=3D VLMAX */ s1 =3D tcg_constant_tl(RV_VLEN_MAX); diff --git a/target/riscv/translate.c b/target/riscv/translate.c index f2f0593830..3040f5e0e4 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -38,7 +38,7 @@ #undef HELPER_H =20 /* global register indices */ -static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl; +static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc; static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */ static TCGv load_res; static TCGv load_val; @@ -1320,7 +1320,6 @@ void riscv_translate_init(void) } =20 cpu_pc =3D tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, pc), "p= c"); - cpu_vl =3D tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, vl), "v= l"); load_res =3D tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, load_= res), "load_res"); load_val =3D tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, load_= val), --=20 2.43.2