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Wed, 21 Feb 2024 10:21:18 -0800 (PST) From: nifan.cxl@gmail.com To: qemu-devel@nongnu.org Cc: jonathan.cameron@huawei.com, linux-cxl@vger.kernel.org, gregory.price@memverge.com, ira.weiny@intel.com, dan.j.williams@intel.com, a.manzanares@samsung.com, dave@stgolabs.net, nmtadam.samsung@gmail.com, nifan.cxl@gmail.com, jim.harris@samsung.com, Fan Ni Subject: [PATCH v4 06/10] hw/mem/cxl_type3: Add host backend and address space handling for DC regions Date: Wed, 21 Feb 2024 10:15:59 -0800 Message-ID: <20240221182020.1086096-7-nifan.cxl@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240221182020.1086096-1-nifan.cxl@gmail.com> References: <20240221182020.1086096-1-nifan.cxl@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::532; envelope-from=nifan.cxl@gmail.com; helo=mail-pg1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1708539723460100001 Content-Type: text/plain; charset="utf-8" From: Fan Ni Add (file/memory backed) host backend, all the dynamic capacity regions will share a single, large enough host backend. Set up address space for DC regions to support read/write operations to dynamic capacity for DCD. With the change, following supports are added: 1. Add a new property to type3 device "volatile-dc-memdev" to point to host memory backend for dynamic capacity. Currently, all dc regions share one one host backend. 2. Add namespace for dynamic capacity for read/write support; 3. Create cdat entries for each dynamic capacity region; 4. Fix dvsec range registers to include DC regions. Signed-off-by: Fan Ni --- hw/cxl/cxl-mailbox-utils.c | 16 ++- hw/mem/cxl_type3.c | 188 ++++++++++++++++++++++++++++-------- include/hw/cxl/cxl_device.h | 4 + 3 files changed, 165 insertions(+), 43 deletions(-) diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c index 7d2b74c9c5..f95e417683 100644 --- a/hw/cxl/cxl-mailbox-utils.c +++ b/hw/cxl/cxl-mailbox-utils.c @@ -621,7 +621,8 @@ static CXLRetCode cmd_firmware_update_get_info(const st= ruct cxl_cmd *cmd, size_t *len_out, CXLCCI *cci) { - CXLDeviceState *cxl_dstate =3D &CXL_TYPE3(cci->d)->cxl_dstate; + CXLType3Dev *ct3d =3D CXL_TYPE3(cci->d); + CXLDeviceState *cxl_dstate =3D &ct3d->cxl_dstate; struct { uint8_t slots_supported; uint8_t slot_info; @@ -635,7 +636,8 @@ static CXLRetCode cmd_firmware_update_get_info(const st= ruct cxl_cmd *cmd, QEMU_BUILD_BUG_ON(sizeof(*fw_info) !=3D 0x50); =20 if ((cxl_dstate->vmem_size < CXL_CAPACITY_MULTIPLIER) || - (cxl_dstate->pmem_size < CXL_CAPACITY_MULTIPLIER)) { + (cxl_dstate->pmem_size < CXL_CAPACITY_MULTIPLIER) || + (ct3d->dc.total_capacity < CXL_CAPACITY_MULTIPLIER)) { return CXL_MBOX_INTERNAL_ERROR; } =20 @@ -792,7 +794,8 @@ static CXLRetCode cmd_identify_memory_device(const stru= ct cxl_cmd *cmd, CXLDeviceState *cxl_dstate =3D &ct3d->cxl_dstate; =20 if ((!QEMU_IS_ALIGNED(cxl_dstate->vmem_size, CXL_CAPACITY_MULTIPLIER))= || - (!QEMU_IS_ALIGNED(cxl_dstate->pmem_size, CXL_CAPACITY_MULTIPLIER))= ) { + (!QEMU_IS_ALIGNED(cxl_dstate->pmem_size, CXL_CAPACITY_MULTIPLIER))= || + (!QEMU_IS_ALIGNED(ct3d->dc.total_capacity, CXL_CAPACITY_MULTIPLIER= ))) { return CXL_MBOX_INTERNAL_ERROR; } =20 @@ -834,9 +837,11 @@ static CXLRetCode cmd_ccls_get_partition_info(const st= ruct cxl_cmd *cmd, uint64_t next_pmem; } QEMU_PACKED *part_info =3D (void *)payload_out; QEMU_BUILD_BUG_ON(sizeof(*part_info) !=3D 0x20); + CXLType3Dev *ct3d =3D container_of(cxl_dstate, CXLType3Dev, cxl_dstate= ); =20 if ((!QEMU_IS_ALIGNED(cxl_dstate->vmem_size, CXL_CAPACITY_MULTIPLIER))= || - (!QEMU_IS_ALIGNED(cxl_dstate->pmem_size, CXL_CAPACITY_MULTIPLIER))= ) { + (!QEMU_IS_ALIGNED(cxl_dstate->pmem_size, CXL_CAPACITY_MULTIPLIER))= || + (!QEMU_IS_ALIGNED(ct3d->dc.total_capacity, CXL_CAPACITY_MULTIPLIER= ))) { return CXL_MBOX_INTERNAL_ERROR; } =20 @@ -1178,7 +1183,8 @@ static CXLRetCode cmd_media_clear_poison(const struct= cxl_cmd *cmd, struct clear_poison_pl *in =3D (void *)payload_in; =20 dpa =3D ldq_le_p(&in->dpa); - if (dpa + CXL_CACHE_LINE_SIZE > cxl_dstate->static_mem_size) { + if (dpa + CXL_CACHE_LINE_SIZE > cxl_dstate->static_mem_size + + ct3d->dc.total_capacity) { return CXL_MBOX_INVALID_PA; } =20 diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c index 6e5f908fb1..b966fa4f10 100644 --- a/hw/mem/cxl_type3.c +++ b/hw/mem/cxl_type3.c @@ -30,6 +30,7 @@ #include "hw/pci/msix.h" =20 #define DWORD_BYTE 4 +#define CXL_CAPACITY_MULTIPLIER (256 * MiB) =20 /* Default CDAT entries for a memory region */ enum { @@ -44,7 +45,8 @@ enum { =20 static void ct3_build_cdat_entries_for_mr(CDATSubHeader **cdat_table, int dsmad_handle, uint64_t size, - bool is_pmem, uint64_t dpa_base) + bool is_pmem, bool is_dynamic, + uint64_t dpa_base) { g_autofree CDATDsmas *dsmas =3D NULL; g_autofree CDATDslbis *dslbis0 =3D NULL; @@ -60,7 +62,8 @@ static void ct3_build_cdat_entries_for_mr(CDATSubHeader *= *cdat_table, .length =3D sizeof(*dsmas), }, .DSMADhandle =3D dsmad_handle, - .flags =3D is_pmem ? CDAT_DSMAS_FLAG_NV : 0, + .flags =3D (is_pmem ? CDAT_DSMAS_FLAG_NV : 0) | + (is_dynamic ? CDAT_DSMAS_FLAG_DYNAMIC_CAP : 0), .DPA_base =3D dpa_base, .DPA_length =3D size, }; @@ -148,12 +151,13 @@ static int ct3_build_cdat_table(CDATSubHeader ***cdat= _table, void *priv) g_autofree CDATSubHeader **table =3D NULL; CXLType3Dev *ct3d =3D priv; MemoryRegion *volatile_mr =3D NULL, *nonvolatile_mr =3D NULL; + MemoryRegion *dc_mr =3D NULL; uint64_t vmr_size =3D 0, pmr_size =3D 0; int dsmad_handle =3D 0; int cur_ent =3D 0; int len =3D 0; =20 - if (!ct3d->hostpmem && !ct3d->hostvmem) { + if (!ct3d->hostpmem && !ct3d->hostvmem && !ct3d->dc.num_regions) { return 0; } =20 @@ -175,21 +179,51 @@ static int ct3_build_cdat_table(CDATSubHeader ***cdat= _table, void *priv) pmr_size =3D memory_region_size(nonvolatile_mr); } =20 + if (ct3d->dc.num_regions) { + if (ct3d->dc.host_dc) { + dc_mr =3D host_memory_backend_get_memory(ct3d->dc.host_dc); + if (!dc_mr) { + return -EINVAL; + } + len +=3D CT3_CDAT_NUM_ENTRIES * ct3d->dc.num_regions; + } else { + return -EINVAL; + } + } + table =3D g_malloc0(len * sizeof(*table)); =20 /* Now fill them in */ if (volatile_mr) { ct3_build_cdat_entries_for_mr(table, dsmad_handle++, vmr_size, - false, 0); + false, false, 0); cur_ent =3D CT3_CDAT_NUM_ENTRIES; } =20 if (nonvolatile_mr) { uint64_t base =3D vmr_size; ct3_build_cdat_entries_for_mr(&(table[cur_ent]), dsmad_handle++, - pmr_size, true, base); + pmr_size, true, false, base); cur_ent +=3D CT3_CDAT_NUM_ENTRIES; } + + if (dc_mr) { + int i; + uint64_t region_base =3D vmr_size + pmr_size; + + /* FIXME: Currently we assume the dynamic capacity to be volatile.= */ + for (i =3D 0; i < ct3d->dc.num_regions; i++) { + ct3_build_cdat_entries_for_mr(&(table[cur_ent]), + dsmad_handle++, + ct3d->dc.regions[i].len, + false, true, region_base); + ct3d->dc.regions[i].dsmadhandle =3D dsmad_handle - 1; + + cur_ent +=3D CT3_CDAT_NUM_ENTRIES; + region_base +=3D ct3d->dc.regions[i].len; + } + } + assert(len =3D=3D cur_ent); =20 *cdat_table =3D g_steal_pointer(&table); @@ -299,11 +333,24 @@ static void build_dvsecs(CXLType3Dev *ct3d) range2_size_hi =3D ct3d->hostpmem->size >> 32; range2_size_lo =3D (2 << 5) | (2 << 2) | 0x3 | (ct3d->hostpmem->size & 0xF0000000); + } else if (ct3d->dc.host_dc) { + range2_size_hi =3D ct3d->dc.host_dc->size >> 32; + range2_size_lo =3D (2 << 5) | (2 << 2) | 0x3 | + (ct3d->dc.host_dc->size & 0xF0000000); } - } else { + } else if (ct3d->hostpmem) { range1_size_hi =3D ct3d->hostpmem->size >> 32; range1_size_lo =3D (2 << 5) | (2 << 2) | 0x3 | (ct3d->hostpmem->size & 0xF0000000); + if (ct3d->dc.host_dc) { + range2_size_hi =3D ct3d->dc.host_dc->size >> 32; + range2_size_lo =3D (2 << 5) | (2 << 2) | 0x3 | + (ct3d->dc.host_dc->size & 0xF0000000); + } + } else { + range1_size_hi =3D ct3d->dc.host_dc->size >> 32; + range1_size_lo =3D (2 << 5) | (2 << 2) | 0x3 | + (ct3d->dc.host_dc->size & 0xF0000000); } =20 dvsec =3D (uint8_t *)&(CXLDVSECDevice){ @@ -570,19 +617,32 @@ static void ct3d_reg_write(void *opaque, hwaddr offse= t, uint64_t value, } } =20 -/* - * TODO: dc region configuration will be updated once host backend and add= ress - * space support is added for DCD. - */ static bool cxl_create_dc_regions(CXLType3Dev *ct3d, Error **errp) { int i; + MemoryRegion *dc_mr; + uint64_t dc_size =3D 0; uint64_t region_base =3D 0; - uint64_t region_len =3D 2 * GiB; - uint64_t decode_len =3D 2 * GiB; + uint64_t region_len; + uint64_t decode_len; uint64_t blk_size =3D 2 * MiB; CXLDCDRegion *region; =20 + dc_mr =3D host_memory_backend_get_memory(ct3d->dc.host_dc); + dc_size =3D memory_region_size(dc_mr); + region_len =3D DIV_ROUND_UP(dc_size, ct3d->dc.num_regions); + + if (region_len * ct3d->dc.num_regions > dc_size) { + error_setg(errp, "host backend size must be multiples of region le= n"); + return false; + } + if (region_len % CXL_CAPACITY_MULTIPLIER !=3D 0) { + error_setg(errp, "DC region size is unaligned to %lx", + CXL_CAPACITY_MULTIPLIER); + return false; + } + decode_len =3D region_len; + if (ct3d->hostvmem) { region_base +=3D ct3d->hostvmem->size; } @@ -599,6 +659,7 @@ static bool cxl_create_dc_regions(CXLType3Dev *ct3d, Er= ror **errp) region->flags =3D 0; =20 region_base +=3D region->len; + ct3d->dc.total_capacity +=3D region->len; } =20 return true; @@ -608,7 +669,8 @@ static bool cxl_setup_memory(CXLType3Dev *ct3d, Error *= *errp) { DeviceState *ds =3D DEVICE(ct3d); =20 - if (!ct3d->hostmem && !ct3d->hostvmem && !ct3d->hostpmem) { + if (!ct3d->hostmem && !ct3d->hostvmem && !ct3d->hostpmem + && !ct3d->dc.num_regions) { error_setg(errp, "at least one memdev property must be set"); return false; } else if (ct3d->hostmem && ct3d->hostpmem) { @@ -672,9 +734,38 @@ static bool cxl_setup_memory(CXLType3Dev *ct3d, Error = **errp) g_free(p_name); } =20 - if (!cxl_create_dc_regions(ct3d, errp)) { - error_setg(errp, "setup DC regions failed"); - return false; + ct3d->dc.total_capacity =3D 0; + if (ct3d->dc.num_regions) { + MemoryRegion *dc_mr; + char *dc_name; + + if (!ct3d->dc.host_dc) { + error_setg(errp, "dynamic capacity must have a backing device"= ); + return false; + } + + dc_mr =3D host_memory_backend_get_memory(ct3d->dc.host_dc); + if (!dc_mr) { + error_setg(errp, "dynamic capacity must have a backing device"= ); + return false; + } + + /* FIXME: set dc as volatile for now */ + memory_region_set_nonvolatile(dc_mr, false); + memory_region_set_enabled(dc_mr, true); + host_memory_backend_set_mapped(ct3d->dc.host_dc, true); + if (ds->id) { + dc_name =3D g_strdup_printf("cxl-dcd-dpa-dc-space:%s", ds->id); + } else { + dc_name =3D g_strdup("cxl-dcd-dpa-dc-space"); + } + address_space_init(&ct3d->dc.host_dc_as, dc_mr, dc_name); + g_free(dc_name); + + if (!cxl_create_dc_regions(ct3d, errp)) { + error_setg(errp, "setup DC regions failed"); + return false; + } } =20 return true; @@ -766,6 +857,9 @@ err_release_cdat: err_free_special_ops: g_free(regs->special_ops); err_address_space_free: + if (ct3d->dc.host_dc) { + address_space_destroy(&ct3d->dc.host_dc_as); + } if (ct3d->hostpmem) { address_space_destroy(&ct3d->hostpmem_as); } @@ -784,6 +878,9 @@ static void ct3_exit(PCIDevice *pci_dev) pcie_aer_exit(pci_dev); cxl_doe_cdat_release(cxl_cstate); g_free(regs->special_ops); + if (ct3d->dc.host_dc) { + address_space_destroy(&ct3d->dc.host_dc_as); + } if (ct3d->hostpmem) { address_space_destroy(&ct3d->hostpmem_as); } @@ -862,16 +959,24 @@ static int cxl_type3_hpa_to_as_and_dpa(CXLType3Dev *c= t3d, AddressSpace **as, uint64_t *dpa_offset) { - MemoryRegion *vmr =3D NULL, *pmr =3D NULL; + MemoryRegion *vmr =3D NULL, *pmr =3D NULL, *dc_mr =3D NULL; + uint64_t vmr_size =3D 0, pmr_size =3D 0, dc_size =3D 0; =20 if (ct3d->hostvmem) { vmr =3D host_memory_backend_get_memory(ct3d->hostvmem); + vmr_size =3D memory_region_size(vmr); } if (ct3d->hostpmem) { pmr =3D host_memory_backend_get_memory(ct3d->hostpmem); + pmr_size =3D memory_region_size(pmr); + } + if (ct3d->dc.host_dc) { + dc_mr =3D host_memory_backend_get_memory(ct3d->dc.host_dc); + /* Do we want dc_size to be dc_mr->size or not?? */ + dc_size =3D ct3d->dc.total_capacity; } =20 - if (!vmr && !pmr) { + if (!vmr && !pmr && !dc_mr) { return -ENODEV; } =20 @@ -879,19 +984,18 @@ static int cxl_type3_hpa_to_as_and_dpa(CXLType3Dev *c= t3d, return -EINVAL; } =20 - if (*dpa_offset > ct3d->cxl_dstate.static_mem_size) { + if (*dpa_offset >=3D vmr_size + pmr_size + dc_size) { return -EINVAL; } =20 - if (vmr) { - if (*dpa_offset < memory_region_size(vmr)) { - *as =3D &ct3d->hostvmem_as; - } else { - *as =3D &ct3d->hostpmem_as; - *dpa_offset -=3D memory_region_size(vmr); - } - } else { + if (*dpa_offset < vmr_size) { + *as =3D &ct3d->hostvmem_as; + } else if (*dpa_offset < vmr_size + pmr_size) { *as =3D &ct3d->hostpmem_as; + *dpa_offset -=3D vmr_size; + } else { + *as =3D &ct3d->dc.host_dc_as; + *dpa_offset -=3D (vmr_size + pmr_size); } =20 return 0; @@ -973,6 +1077,8 @@ static Property ct3_props[] =3D { DEFINE_PROP_UINT64("sn", CXLType3Dev, sn, UI64_NULL), DEFINE_PROP_STRING("cdat", CXLType3Dev, cxl_cstate.cdat.filename), DEFINE_PROP_UINT8("num-dc-regions", CXLType3Dev, dc.num_regions, 0), + DEFINE_PROP_LINK("volatile-dc-memdev", CXLType3Dev, dc.host_dc, + TYPE_MEMORY_BACKEND, HostMemoryBackend *), DEFINE_PROP_END_OF_LIST(), }; =20 @@ -1039,33 +1145,39 @@ static void set_lsa(CXLType3Dev *ct3d, const void *= buf, uint64_t size, =20 static bool set_cacheline(CXLType3Dev *ct3d, uint64_t dpa_offset, uint8_t = *data) { - MemoryRegion *vmr =3D NULL, *pmr =3D NULL; + MemoryRegion *vmr =3D NULL, *pmr =3D NULL, *dc_mr =3D NULL; AddressSpace *as; + uint64_t vmr_size =3D 0, pmr_size =3D 0, dc_size =3D 0; =20 if (ct3d->hostvmem) { vmr =3D host_memory_backend_get_memory(ct3d->hostvmem); + vmr_size =3D memory_region_size(vmr); } if (ct3d->hostpmem) { pmr =3D host_memory_backend_get_memory(ct3d->hostpmem); + pmr_size =3D memory_region_size(pmr); } + if (ct3d->dc.host_dc) { + dc_mr =3D host_memory_backend_get_memory(ct3d->dc.host_dc); + dc_size =3D ct3d->dc.total_capacity; + } =20 - if (!vmr && !pmr) { + if (!vmr && !pmr && !dc_mr) { return false; } =20 - if (dpa_offset + CXL_CACHE_LINE_SIZE > ct3d->cxl_dstate.static_mem_siz= e) { + if (dpa_offset + CXL_CACHE_LINE_SIZE > vmr_size + pmr_size + dc_size) { return false; } =20 - if (vmr) { - if (dpa_offset < memory_region_size(vmr)) { - as =3D &ct3d->hostvmem_as; - } else { - as =3D &ct3d->hostpmem_as; - dpa_offset -=3D memory_region_size(vmr); - } - } else { + if (dpa_offset < vmr_size) { + as =3D &ct3d->hostvmem_as; + } else if (dpa_offset < vmr_size + pmr_size) { as =3D &ct3d->hostpmem_as; + dpa_offset -=3D vmr_size; + } else { + as =3D &ct3d->dc.host_dc_as; + dpa_offset -=3D (vmr_size + pmr_size); } =20 address_space_write(as, dpa_offset, MEMTXATTRS_UNSPECIFIED, &data, diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h index 80188db670..2f244da9a1 100644 --- a/include/hw/cxl/cxl_device.h +++ b/include/hw/cxl/cxl_device.h @@ -467,6 +467,10 @@ struct CXLType3Dev { uint64_t poison_list_overflow_ts; =20 struct dynamic_capacity { + HostMemoryBackend *host_dc; + AddressSpace host_dc_as; + uint64_t total_capacity; /* 256M aligned */ + uint8_t num_regions; /* 0-8 regions */ CXLDCDRegion regions[DCD_MAX_REGION_NUM]; } dc; --=20 2.43.0