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Wed, 21 Feb 2024 10:21:13 -0800 (PST) From: nifan.cxl@gmail.com To: qemu-devel@nongnu.org Cc: jonathan.cameron@huawei.com, linux-cxl@vger.kernel.org, gregory.price@memverge.com, ira.weiny@intel.com, dan.j.williams@intel.com, a.manzanares@samsung.com, dave@stgolabs.net, nmtadam.samsung@gmail.com, nifan.cxl@gmail.com, jim.harris@samsung.com, Fan Ni Subject: [PATCH v4 02/10] hw/cxl/cxl-mailbox-utils: Add dynamic capacity region representative and mailbox command support Date: Wed, 21 Feb 2024 10:15:55 -0800 Message-ID: <20240221182020.1086096-3-nifan.cxl@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240221182020.1086096-1-nifan.cxl@gmail.com> References: <20240221182020.1086096-1-nifan.cxl@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::530; envelope-from=nifan.cxl@gmail.com; helo=mail-pg1-x530.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1708539751363100009 Content-Type: text/plain; charset="utf-8" From: Fan Ni Per cxl spec r3.1, add dynamic capacity region representative based on Table 8-165 and extend the cxl type3 device definition to include dc region information. Also, based on info in 8.2.9.9.9.1, add 'Get Dynamic Capacity Configuration' mailbox support. Note: decode_len of a dc region is aligned to 256*MiB, divided by 256 * MiB before returned to the host for "Get Dynamic Capacity Configurati= on" mailbox command. Signed-off-by: Fan Ni --- hw/cxl/cxl-mailbox-utils.c | 110 ++++++++++++++++++++++++++++++++++++ include/hw/cxl/cxl_device.h | 16 ++++++ 2 files changed, 126 insertions(+) diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c index ba1d9901df..88e3b733e3 100644 --- a/hw/cxl/cxl-mailbox-utils.c +++ b/hw/cxl/cxl-mailbox-utils.c @@ -22,6 +22,7 @@ =20 #define CXL_CAPACITY_MULTIPLIER (256 * MiB) #define CXL_DC_EVENT_LOG_SIZE 8 +#define CXL_SPEC_AFTER_R30 =20 /* * How to add a new command, example. The command set FOO, with cmd BAR. @@ -80,6 +81,8 @@ enum { #define GET_POISON_LIST 0x0 #define INJECT_POISON 0x1 #define CLEAR_POISON 0x2 + DCD_CONFIG =3D 0x48, + #define GET_DC_CONFIG 0x0 PHYSICAL_SWITCH =3D 0x51, #define IDENTIFY_SWITCH_DEVICE 0x0 #define GET_PHYSICAL_PORT_STATE 0x1 @@ -1238,6 +1241,103 @@ static CXLRetCode cmd_media_clear_poison(const stru= ct cxl_cmd *cmd, return CXL_MBOX_SUCCESS; } =20 +/* + * CXL r3.1 section 8.2.9.9.9.1: Get Dynamic Capacity Configuration + * (Opcode: 4800h) + */ +static CXLRetCode cmd_dcd_get_dyn_cap_config(const struct cxl_cmd *cmd, + uint8_t *payload_in, + size_t len_in, + uint8_t *payload_out, + size_t *len_out, + CXLCCI *cci) +{ + CXLType3Dev *ct3d =3D CXL_TYPE3(cci->d); + struct get_dyn_cap_config_in_pl { + uint8_t region_cnt; + uint8_t start_region_id; + } QEMU_PACKED; + + struct get_dyn_cap_config_out_pl { + uint8_t num_regions; + uint8_t regions_returned; + uint8_t rsvd1[6]; + struct { + uint64_t base; + uint64_t decode_len; + uint64_t region_len; + uint64_t block_size; + uint32_t dsmadhandle; + uint8_t flags; + uint8_t rsvd2[3]; + } QEMU_PACKED records[]; + /* + * if cxl spec version >=3D 3.1, extra output payload as defined + * in struct get_dyn_cap_config_out_pl_extra comes here. + */ + } QEMU_PACKED; + + struct get_dyn_cap_config_in_pl *in =3D (void *)payload_in; + struct get_dyn_cap_config_out_pl *out =3D (void *)payload_out; + uint16_t record_count =3D 0; + uint16_t i; + uint16_t out_pl_len; + uint8_t start_region_id =3D in->start_region_id; +#ifdef CXL_SPEC_AFTER_R30 + struct get_dyn_cap_config_out_pl_extra { + uint32_t num_extents_supported; + uint32_t num_extents_available; + uint32_t num_tags_supported; + uint32_t num_tags_available; + } QEMU_PACKED; + struct get_dyn_cap_config_out_pl_extra *extra_out; +#endif + + if (start_region_id >=3D ct3d->dc.num_regions) { + return CXL_MBOX_INVALID_INPUT; + } + + record_count =3D MIN(ct3d->dc.num_regions - in->start_region_id, + in->region_cnt); + + out_pl_len =3D sizeof(*out) + record_count * sizeof(out->records[0]); +#ifdef CXL_SPEC_AFTER_R30 + extra_out =3D (struct get_dyn_cap_config_out_pl_extra *)(payload_out + + out_pl_len); + out_pl_len +=3D sizeof(struct get_dyn_cap_config_out_pl_extra); +#endif + assert(out_pl_len <=3D CXL_MAILBOX_MAX_PAYLOAD_SIZE); + + out->num_regions =3D ct3d->dc.num_regions; +#ifdef CXL_SPEC_AFTER_R30 + out->regions_returned =3D record_count; +#endif + for (i =3D 0; i < record_count; i++) { + stq_le_p(&out->records[i].base, + ct3d->dc.regions[start_region_id + i].base); + stq_le_p(&out->records[i].decode_len, + ct3d->dc.regions[start_region_id + i].decode_len / + CXL_CAPACITY_MULTIPLIER); + stq_le_p(&out->records[i].region_len, + ct3d->dc.regions[start_region_id + i].len); + stq_le_p(&out->records[i].block_size, + ct3d->dc.regions[start_region_id + i].block_size); + stl_le_p(&out->records[i].dsmadhandle, + ct3d->dc.regions[start_region_id + i].dsmadhandle); + out->records[i].flags =3D ct3d->dc.regions[start_region_id + i].fl= ags; + } +#ifdef CXL_SPEC_AFTER_R30 + /*FIXME: need to set valid values in the future*/ + stq_le_p(&extra_out->num_extents_supported, 0); + stq_le_p(&extra_out->num_extents_available, 0); + stq_le_p(&extra_out->num_tags_supported, 0); + stq_le_p(&extra_out->num_tags_available, 0); +#endif + + *len_out =3D out_pl_len; + return CXL_MBOX_SUCCESS; +} + #define IMMEDIATE_CONFIG_CHANGE (1 << 1) #define IMMEDIATE_DATA_CHANGE (1 << 2) #define IMMEDIATE_POLICY_CHANGE (1 << 3) @@ -1282,6 +1382,11 @@ static const struct cxl_cmd cxl_cmd_set[256][256] = =3D { cmd_media_clear_poison, 72, 0 }, }; =20 +static const struct cxl_cmd cxl_cmd_set_dcd[256][256] =3D { + [DCD_CONFIG][GET_DC_CONFIG] =3D { "DCD_GET_DC_CONFIG", + cmd_dcd_get_dyn_cap_config, 2, 0 }, +}; + static const struct cxl_cmd cxl_cmd_set_sw[256][256] =3D { [INFOSTAT][IS_IDENTIFY] =3D { "IDENTIFY", cmd_infostat_identify, 0, 0 = }, [INFOSTAT][BACKGROUND_OPERATION_STATUS] =3D { "BACKGROUND_OPERATION_ST= ATUS", @@ -1487,7 +1592,12 @@ void cxl_initialize_mailbox_swcci(CXLCCI *cci, Devic= eState *intf, =20 void cxl_initialize_mailbox_t3(CXLCCI *cci, DeviceState *d, size_t payload= _max) { + CXLType3Dev *ct3d =3D CXL_TYPE3(d); + cxl_copy_cci_commands(cci, cxl_cmd_set); + if (ct3d->dc.num_regions) { + cxl_copy_cci_commands(cci, cxl_cmd_set_dcd); + } cci->d =3D d; =20 /* No separation for PCI MB as protocol handled in PCI device */ diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h index 3cf3077afa..6df7fecdf1 100644 --- a/include/hw/cxl/cxl_device.h +++ b/include/hw/cxl/cxl_device.h @@ -422,6 +422,17 @@ typedef struct CXLPoison { typedef QLIST_HEAD(, CXLPoison) CXLPoisonList; #define CXL_POISON_LIST_LIMIT 256 =20 +#define DCD_MAX_REGION_NUM 8 + +typedef struct CXLDCDRegion { + uint64_t base; + uint64_t decode_len; /* aligned to 256*MiB */ + uint64_t len; + uint64_t block_size; + uint32_t dsmadhandle; + uint8_t flags; +} CXLDCDRegion; + struct CXLType3Dev { /* Private */ PCIDevice parent_obj; @@ -454,6 +465,11 @@ struct CXLType3Dev { unsigned int poison_list_cnt; bool poison_list_overflowed; uint64_t poison_list_overflow_ts; + + struct dynamic_capacity { + uint8_t num_regions; /* 0-8 regions */ + CXLDCDRegion regions[DCD_MAX_REGION_NUM]; + } dc; }; =20 #define TYPE_CXL_TYPE3 "cxl-type3" --=20 2.43.0