From nobody Tue Nov 26 11:44:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1708529069; cv=none; d=zohomail.com; s=zohoarc; b=WV9+BH9F0kln98K2tLZFDGsaVAE4bjsQkpo8s3+cOpYQsflfifdaCc303eliAXfmQSmUDQMgt+JGlXvdh/vO8gQcrRuEKKN5r+AvvTvV9Rsh2HC1NpqWt3+A8kaBZ9Hm020/iNmqDz6ajIfxh327mOdGqDZxhPheD8cCXvFULnM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1708529069; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=NRA9JDVh2earMqNOS/wj86lbDqLT8isJrTaRbQsC+ow=; b=Vj6gxcLk/lByxrMuyKAs9xGJ0FgSAl3d7b3/QroakNNUQt9qt/BduTOvFEb1VLvXDS4AuyJua4gpIyQg1eirSdbW5TsdhDchw0kbyog8PWOm/S38t6z5C9r11O+akS4bWjcFBaUHVSu3z2CyKhFc/aprIHdAevUPsH5UzniXsqY= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1708529069559322.71731029116324; Wed, 21 Feb 2024 07:24:29 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rcoNM-0006Gg-1U; Wed, 21 Feb 2024 10:19:12 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rcoJv-00010D-2b; Wed, 21 Feb 2024 10:15:44 -0500 Received: from szxga04-in.huawei.com ([45.249.212.190]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rcmLz-0004pX-Lo; Wed, 21 Feb 2024 08:09:42 -0500 Received: from mail.maildlp.com (unknown [172.19.163.44]) by szxga04-in.huawei.com (SkyGuard) with ESMTP id 4TfxQr4FQPz1xnx5; Wed, 21 Feb 2024 21:08:04 +0800 (CST) Received: from kwepemi500008.china.huawei.com (unknown [7.221.188.139]) by mail.maildlp.com (Postfix) with ESMTPS id 4E4A11402CC; Wed, 21 Feb 2024 21:09:27 +0800 (CST) Received: from huawei.com (10.67.174.55) by kwepemi500008.china.huawei.com (7.221.188.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Wed, 21 Feb 2024 21:09:26 +0800 To: , , , , , , CC: Subject: [RFC PATCH v2 06/22] target/arm: Add support for Non-maskable Interrupt Date: Wed, 21 Feb 2024 13:08:07 +0000 Message-ID: <20240221130823.677762-7-ruanjinjie@huawei.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240221130823.677762-1-ruanjinjie@huawei.com> References: <20240221130823.677762-1-ruanjinjie@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.67.174.55] X-ClientProxiedBy: dggems706-chm.china.huawei.com (10.3.19.183) To kwepemi500008.china.huawei.com (7.221.188.139) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=45.249.212.190; envelope-from=ruanjinjie@huawei.com; helo=szxga04-in.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jinjie Ruan From: Jinjie Ruan via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1708529071567100007 Content-Type: text/plain; charset="utf-8" This only implements the external delivery method via the GICv3. Signed-off-by: Jinjie Ruan --- target/arm/cpu-qom.h | 3 ++- target/arm/cpu.c | 39 ++++++++++++++++++++++++++++++++++----- target/arm/cpu.h | 2 ++ target/arm/helper.c | 1 + 4 files changed, 39 insertions(+), 6 deletions(-) diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h index 8e032691db..66d555a605 100644 --- a/target/arm/cpu-qom.h +++ b/target/arm/cpu-qom.h @@ -36,11 +36,12 @@ DECLARE_CLASS_CHECKERS(AArch64CPUClass, AARCH64_CPU, #define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU #define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX) =20 -/* Meanings of the ARMCPU object's four inbound GPIO lines */ +/* Meanings of the ARMCPU object's five inbound GPIO lines */ #define ARM_CPU_IRQ 0 #define ARM_CPU_FIQ 1 #define ARM_CPU_VIRQ 2 #define ARM_CPU_VFIQ 3 +#define ARM_CPU_NMI 4 =20 /* For M profile, some registers are banked secure vs non-secure; * these are represented as a 2-element array where the first element diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 5e5978c302..055670343e 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -128,7 +128,7 @@ static bool arm_cpu_has_work(CPUState *cs) =20 return (cpu->power_state !=3D PSCI_OFF) && cs->interrupt_request & - (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD + (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ | CPU_INTERRUPT_VSERR | CPU_INTERRUPT_EXITTB); } @@ -668,6 +668,7 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsi= gned int excp_idx, CPUARMState *env =3D cpu_env(cs); bool pstate_unmasked; bool unmasked =3D false; + bool nmi_unmasked =3D false; =20 /* * Don't take exceptions if they target a lower EL. @@ -678,13 +679,29 @@ static inline bool arm_excp_unmasked(CPUState *cs, un= signed int excp_idx, return false; } =20 + nmi_unmasked =3D (!(env->allint & PSTATE_ALLINT)) & + (!((env->cp15.sctlr_el[target_el] & SCTLR_SPINTMASK) && + (env->pstate & PSTATE_SP) && cur_el =3D=3D target_el)); + switch (excp_idx) { + case EXCP_NMI: + pstate_unmasked =3D nmi_unmasked; + break; + case EXCP_FIQ: - pstate_unmasked =3D !(env->daif & PSTATE_F); + if (cpu_isar_feature(aa64_nmi, env_archcpu(env))) { + pstate_unmasked =3D (!(env->daif & PSTATE_F)) & nmi_unmasked; + } else { + pstate_unmasked =3D !(env->daif & PSTATE_F); + } break; =20 case EXCP_IRQ: - pstate_unmasked =3D !(env->daif & PSTATE_I); + if (cpu_isar_feature(aa64_nmi, env_archcpu(env))) { + pstate_unmasked =3D (!(env->daif & PSTATE_I)) & nmi_unmasked; + } else { + pstate_unmasked =3D !(env->daif & PSTATE_I); + } break; =20 case EXCP_VFIQ: @@ -804,6 +821,16 @@ static bool arm_cpu_exec_interrupt(CPUState *cs, int i= nterrupt_request) =20 /* The prioritization of interrupts is IMPLEMENTATION DEFINED. */ =20 + if (cpu_isar_feature(aa64_nmi, env_archcpu(env))) { + if (interrupt_request & CPU_INTERRUPT_NMI) { + excp_idx =3D EXCP_NMI; + target_el =3D arm_phys_excp_target_el(cs, excp_idx, cur_el, se= cure); + if (arm_excp_unmasked(cs, excp_idx, target_el, + cur_el, secure, hcr_el2)) { + goto found; + } + } + } if (interrupt_request & CPU_INTERRUPT_FIQ) { excp_idx =3D EXCP_FIQ; target_el =3D arm_phys_excp_target_el(cs, excp_idx, cur_el, secure= ); @@ -929,7 +956,8 @@ static void arm_cpu_set_irq(void *opaque, int irq, int = level) [ARM_CPU_IRQ] =3D CPU_INTERRUPT_HARD, [ARM_CPU_FIQ] =3D CPU_INTERRUPT_FIQ, [ARM_CPU_VIRQ] =3D CPU_INTERRUPT_VIRQ, - [ARM_CPU_VFIQ] =3D CPU_INTERRUPT_VFIQ + [ARM_CPU_VFIQ] =3D CPU_INTERRUPT_VFIQ, + [ARM_CPU_NMI] =3D CPU_INTERRUPT_NMI }; =20 if (!arm_feature(env, ARM_FEATURE_EL2) && @@ -957,6 +985,7 @@ static void arm_cpu_set_irq(void *opaque, int irq, int = level) break; case ARM_CPU_IRQ: case ARM_CPU_FIQ: + case ARM_CPU_NMI: if (level) { cpu_interrupt(cs, mask[irq]); } else { @@ -1358,7 +1387,7 @@ static void arm_cpu_initfn(Object *obj) */ qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4); } else { - qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4); + qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 5); } =20 qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs, diff --git a/target/arm/cpu.h b/target/arm/cpu.h index f9646dbbfb..5257343bcb 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -60,6 +60,7 @@ #define EXCP_DIVBYZERO 23 /* v7M DIVBYZERO UsageFault */ #define EXCP_VSERR 24 #define EXCP_GPC 25 /* v9 Granule Protection Check Fault */ +#define EXCP_NMI 26 /* NB: add new EXCP_ defines to the array in arm_log_exception() too */ =20 #define ARMV7M_EXCP_RESET 1 @@ -79,6 +80,7 @@ #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2 #define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3 #define CPU_INTERRUPT_VSERR CPU_INTERRUPT_TGT_INT_0 +#define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_4 =20 /* The usual mapping for an AArch64 system register to its AArch32 * counterpart is for the 32 bit world to have access to the lower diff --git a/target/arm/helper.c b/target/arm/helper.c index 211156d640..bd7858e02e 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10626,6 +10626,7 @@ void arm_log_exception(CPUState *cs) [EXCP_DIVBYZERO] =3D "v7M DIVBYZERO UsageFault", [EXCP_VSERR] =3D "Virtual SERR", [EXCP_GPC] =3D "Granule Protection Check", + [EXCP_NMI] =3D "NMI" }; =20 if (idx >=3D 0 && idx < ARRAY_SIZE(excnames)) { --=20 2.34.1