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Wed, 21 Feb 2024 21:07:17 +0800 (CST) Received: from kwepemi500008.china.huawei.com (unknown [7.221.188.139]) by mail.maildlp.com (Postfix) with ESMTPS id 787D114011B; Wed, 21 Feb 2024 21:09:26 +0800 (CST) Received: from huawei.com (10.67.174.55) by kwepemi500008.china.huawei.com (7.221.188.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Wed, 21 Feb 2024 21:09:25 +0800 To: , , , , , , CC: Subject: [RFC PATCH v2 05/22] target/arm: Support MSR access to ALLINT Date: Wed, 21 Feb 2024 13:08:06 +0000 Message-ID: <20240221130823.677762-6-ruanjinjie@huawei.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240221130823.677762-1-ruanjinjie@huawei.com> References: <20240221130823.677762-1-ruanjinjie@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.67.174.55] X-ClientProxiedBy: dggems706-chm.china.huawei.com (10.3.19.183) To kwepemi500008.china.huawei.com (7.221.188.139) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=45.249.212.190; envelope-from=ruanjinjie@huawei.com; helo=szxga04-in.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jinjie Ruan From: Jinjie Ruan via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1708529304127100003 Content-Type: text/plain; charset="utf-8" Support ALLINT msr access as follow: mrs , ALLINT // read allint msr ALLINT, // write allint with imm Signed-off-by: Jinjie Ruan --- target/arm/helper.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index a3062cb2ad..211156d640 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4618,6 +4618,31 @@ static void aa64_daif_write(CPUARMState *env, const = ARMCPRegInfo *ri, env->daif =3D value & PSTATE_DAIF; } =20 +static void aa64_allint_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + env->allint =3D value & PSTATE_ALLINT; +} + +static uint64_t aa64_allint_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + return env->allint & PSTATE_ALLINT; +} + +static CPAccessResult aa64_allint_access(CPUARMState *env, + const ARMCPRegInfo *ri, bool isre= ad) +{ + if (arm_current_el(env) =3D=3D 0) { + return CP_ACCESS_TRAP_UNCATEGORIZED; + } + + if (arm_current_el(env) =3D=3D 1 && arm_is_el2_enabled(env) && + cpu_isar_feature(aa64_hcx, env_archcpu(env)) && + (env->cp15.hcrx_el2 & HCRX_TALLINT)) + return CP_ACCESS_TRAP_EL2; + return CP_ACCESS_OK; +} + static uint64_t aa64_pan_read(CPUARMState *env, const ARMCPRegInfo *ri) { return env->pstate & PSTATE_PAN; @@ -5437,6 +5462,13 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { .access =3D PL0_RW, .accessfn =3D aa64_daif_access, .fieldoffset =3D offsetof(CPUARMState, daif), .writefn =3D aa64_daif_write, .resetfn =3D arm_cp_reset_ignore }, + { .name =3D "ALLINT", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .opc2 =3D 0, .crn =3D 4, .crm =3D 3, + .type =3D ARM_CP_NO_RAW, + .access =3D PL1_RW, .accessfn =3D aa64_allint_access, + .fieldoffset =3D offsetof(CPUARMState, allint), + .writefn =3D aa64_allint_write, .readfn =3D aa64_allint_read, + .resetfn =3D arm_cp_reset_ignore }, { .name =3D "FPCR", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .opc2 =3D 0, .crn =3D 4, .crm =3D 4, .access =3D PL0_RW, .type =3D ARM_CP_FPU | ARM_CP_SUPPRESS_TB_END, --=20 2.34.1