From nobody Tue Nov 26 10:40:06 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1708530498563250.08343979054462; Wed, 21 Feb 2024 07:48:18 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rcoZp-0004QT-7s; Wed, 21 Feb 2024 10:32:05 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rcoOV-0002YR-9s; Wed, 21 Feb 2024 10:20:23 -0500 Received: from isrv.corpit.ru ([86.62.121.231]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rchuQ-0002gG-Vc; Wed, 21 Feb 2024 03:24:57 -0500 Received: from tsrv.corpit.ru (tsrv.tls.msk.ru [192.168.177.2]) by isrv.corpit.ru (Postfix) with ESMTP id D1CA24F3E9; Wed, 21 Feb 2024 11:21:22 +0300 (MSK) Received: from tls.msk.ru (mjt.wg.tls.msk.ru [192.168.177.130]) by tsrv.corpit.ru (Postfix) with SMTP id 9B42E860C8; Wed, 21 Feb 2024 11:21:01 +0300 (MSK) Received: (nullmailer pid 2142118 invoked by uid 1000); Wed, 21 Feb 2024 08:20:58 -0000 From: Michael Tokarev To: qemu-devel@nongnu.org Cc: qemu-stable@nongnu.org, Richard Henderson , Peter Maydell , Gustavo Romero , Michael Tokarev Subject: [Stable-8.2.2 43/60] target/arm: Split out make_svemte_desc Date: Wed, 21 Feb 2024 11:20:31 +0300 Message-Id: <20240221082058.2141850-43-mjt@tls.msk.ru> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=86.62.121.231; envelope-from=mjt@tls.msk.ru; helo=isrv.corpit.ru X-Spam_score_int: -68 X-Spam_score: -6.9 X-Spam_bar: ------ X-Spam_report: (-6.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1708530499545100007 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Share code that creates mtedesc and embeds within simd_desc. Cc: qemu-stable@nongnu.org Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Tested-by: Gustavo Romero Message-id: 20240207025210.8837-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell (cherry picked from commit 96fcc9982b4aad7aced7fbff046048bbccc6cb0c) Signed-off-by: Michael Tokarev diff --git a/target/arm/tcg/translate-a64.h b/target/arm/tcg/translate-a64.h index 96ba39b37e..7b811b8ac5 100644 --- a/target/arm/tcg/translate-a64.h +++ b/target/arm/tcg/translate-a64.h @@ -28,6 +28,8 @@ bool logic_imm_decode_wmask(uint64_t *result, unsigned in= t immn, bool sve_access_check(DisasContext *s); bool sme_enabled_check(DisasContext *s); bool sme_enabled_check_with_svcr(DisasContext *s, unsigned); +uint32_t make_svemte_desc(DisasContext *s, unsigned vsz, uint32_t nregs, + uint32_t msz, bool is_write, uint32_t data); =20 /* This function corresponds to CheckStreamingSVEEnabled. */ static inline bool sme_sm_enabled_check(DisasContext *s) diff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c index 8f0dfc884e..46c7fce8b4 100644 --- a/target/arm/tcg/translate-sme.c +++ b/target/arm/tcg/translate-sme.c @@ -206,7 +206,7 @@ static bool trans_LDST1(DisasContext *s, arg_LDST1 *a) =20 TCGv_ptr t_za, t_pg; TCGv_i64 addr; - int svl, desc =3D 0; + uint32_t desc; bool be =3D s->be_data =3D=3D MO_BE; bool mte =3D s->mte_active[0]; =20 @@ -224,18 +224,11 @@ static bool trans_LDST1(DisasContext *s, arg_LDST1 *a) tcg_gen_shli_i64(addr, cpu_reg(s, a->rm), a->esz); tcg_gen_add_i64(addr, addr, cpu_reg_sp(s, a->rn)); =20 - if (mte) { - desc =3D FIELD_DP32(desc, MTEDESC, MIDX, get_mem_index(s)); - desc =3D FIELD_DP32(desc, MTEDESC, TBI, s->tbid); - desc =3D FIELD_DP32(desc, MTEDESC, TCMA, s->tcma); - desc =3D FIELD_DP32(desc, MTEDESC, WRITE, a->st); - desc =3D FIELD_DP32(desc, MTEDESC, SIZEM1, (1 << a->esz) - 1); - desc <<=3D SVE_MTEDESC_SHIFT; - } else { + if (!mte) { addr =3D clean_data_tbi(s, addr); } - svl =3D streaming_vec_reg_size(s); - desc =3D simd_desc(svl, svl, desc); + + desc =3D make_svemte_desc(s, streaming_vec_reg_size(s), 1, a->esz, a->= st, 0); =20 fns[a->esz][be][a->v][mte][a->st](tcg_env, t_za, t_pg, addr, tcg_constant_i32(desc)); diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c index a88e523cba..508f7b6bbd 100644 --- a/target/arm/tcg/translate-sve.c +++ b/target/arm/tcg/translate-sve.c @@ -4437,18 +4437,18 @@ static const uint8_t dtype_esz[16] =3D { 3, 2, 1, 3 }; =20 -static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr, - int dtype, uint32_t mte_n, bool is_write, - gen_helper_gvec_mem *fn) +uint32_t make_svemte_desc(DisasContext *s, unsigned vsz, uint32_t nregs, + uint32_t msz, bool is_write, uint32_t data) { - unsigned vsz =3D vec_full_reg_size(s); - TCGv_ptr t_pg; uint32_t sizem1; - int desc =3D 0; + uint32_t desc =3D 0; =20 - assert(mte_n >=3D 1 && mte_n <=3D 4); - sizem1 =3D (mte_n << dtype_msz(dtype)) - 1; + /* Assert all of the data fits, with or without MTE enabled. */ + assert(nregs >=3D 1 && nregs <=3D 4); + sizem1 =3D (nregs << msz) - 1; assert(sizem1 <=3D R_MTEDESC_SIZEM1_MASK >> R_MTEDESC_SIZEM1_SHIFT); + assert(data < 1u << SVE_MTEDESC_SHIFT); + if (s->mte_active[0]) { desc =3D FIELD_DP32(desc, MTEDESC, MIDX, get_mem_index(s)); desc =3D FIELD_DP32(desc, MTEDESC, TBI, s->tbid); @@ -4456,7 +4456,18 @@ static void do_mem_zpa(DisasContext *s, int zt, int = pg, TCGv_i64 addr, desc =3D FIELD_DP32(desc, MTEDESC, WRITE, is_write); desc =3D FIELD_DP32(desc, MTEDESC, SIZEM1, sizem1); desc <<=3D SVE_MTEDESC_SHIFT; - } else { + } + return simd_desc(vsz, vsz, desc | data); +} + +static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr, + int dtype, uint32_t nregs, bool is_write, + gen_helper_gvec_mem *fn) +{ + TCGv_ptr t_pg; + uint32_t desc; + + if (!s->mte_active[0]) { addr =3D clean_data_tbi(s, addr); } =20 @@ -4465,7 +4476,8 @@ static void do_mem_zpa(DisasContext *s, int zt, int p= g, TCGv_i64 addr, * registers as pointers, so encode the regno into the data field. * For consistency, do this even for LD1. */ - desc =3D simd_desc(vsz, vsz, zt | desc); + desc =3D make_svemte_desc(s, vec_full_reg_size(s), nregs, + dtype_msz(dtype), is_write, zt); t_pg =3D tcg_temp_new_ptr(); =20 tcg_gen_addi_ptr(t_pg, tcg_env, pred_full_reg_offset(s, pg)); @@ -5224,25 +5236,16 @@ static void do_mem_zpz(DisasContext *s, int zt, int= pg, int zm, int scale, TCGv_i64 scalar, int msz, bool is_write, gen_helper_gvec_mem_scatter *fn) { - unsigned vsz =3D vec_full_reg_size(s); TCGv_ptr t_zm =3D tcg_temp_new_ptr(); TCGv_ptr t_pg =3D tcg_temp_new_ptr(); TCGv_ptr t_zt =3D tcg_temp_new_ptr(); - int desc =3D 0; - - if (s->mte_active[0]) { - desc =3D FIELD_DP32(desc, MTEDESC, MIDX, get_mem_index(s)); - desc =3D FIELD_DP32(desc, MTEDESC, TBI, s->tbid); - desc =3D FIELD_DP32(desc, MTEDESC, TCMA, s->tcma); - desc =3D FIELD_DP32(desc, MTEDESC, WRITE, is_write); - desc =3D FIELD_DP32(desc, MTEDESC, SIZEM1, (1 << msz) - 1); - desc <<=3D SVE_MTEDESC_SHIFT; - } - desc =3D simd_desc(vsz, vsz, desc | scale); + uint32_t desc; =20 tcg_gen_addi_ptr(t_pg, tcg_env, pred_full_reg_offset(s, pg)); tcg_gen_addi_ptr(t_zm, tcg_env, vec_full_reg_offset(s, zm)); tcg_gen_addi_ptr(t_zt, tcg_env, vec_full_reg_offset(s, zt)); + + desc =3D make_svemte_desc(s, vec_full_reg_size(s), 1, msz, is_write, s= cale); fn(tcg_env, t_zt, t_pg, t_zm, scalar, tcg_constant_i32(desc)); } =20 --=20 2.39.2