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[176.184.23.7]) by smtp.gmail.com with ESMTPSA id cc3-20020a5d5c03000000b0033d5e3c6835sm5702004wrb.5.2024.02.20.11.26.33 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 20 Feb 2024 11:26:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1708457195; x=1709061995; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=0RVEkk0ogowsJDDVW8v8EcldTsxXvilqXAuAAWzLt3Q=; b=NY+du7T46AqjeUgJFPaKf7G+EmRMSVst4J9BmNCBncaqtOnZMfbbg1Wlp9uaFzUGIo jHvftrUhtVvYCALWB1Uu25xIUmoKEZxGg/0G9sK58Ni7oplx+WPGVvK33XBQGg7V6/+6 Y2n9QcA9FF9r8WcW75hMVGLauZr0v92LY38r1omqMj+H8aXgJdr1TDrlBrEFVBTayAUu 9a29RQF1qloQdTnZQS2IYI3V3zT48dGdkPazPpq27Gcq+4/AFZEOysJ512Id9isI3yMj 65U5l9yf1WtPZocWZNquacJ2wZ6S0UYOz0qxjjbXPaa3fgJ/22skldS/08ATD1e8De4k kuHA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1708457195; x=1709061995; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0RVEkk0ogowsJDDVW8v8EcldTsxXvilqXAuAAWzLt3Q=; b=oltCqkMJuTNq4TPihijNUHR2jOzsqfyK816JeSA6KnZWjn/6Ue/gTjaBA/0vQ/mWQf /OnJv5pC0bYbxXv4XoUs8Hw5OR2aqU0kxrgrH3quKGQlUhZ5EsR/i649pTbNGRP5lUzu T0MK51nsyPrsY7b8XsxFNVAUEK3trUEZ3pB6fV8LIDYumrRwQVihZ5OJC1mveBNyX7vZ APjsGfItUxej+B8BQrSgYZBX35cgi5RzXT78h7rlGb3B2kEfpVFcRbiWWx7+iQ0CUdgH CRuCn5jTmO+jfYlWytMd3HZX0GV+/E2aDjPJajQ4xwspGTCX9bLOBHQJXXsy+dRztau+ u9cg== X-Gm-Message-State: AOJu0Yx8/7PS9NeIwNfvPt51Hg4E9T5FZb4FE9PVhgI7eCJpgMIlVM1o c0u2EJT+uvFvq0oWi9fNAxOhXKhnPV6vTt6Gg6UC3Q+A+by8giW1WP8H8gxuMqLZw7MKa1U8ylV W X-Google-Smtp-Source: AGHT+IFox4Q9/V4AdMzkU6lVT6BShOrcavRkGAyHvZxrcUWfxCk8r0+a6Z/ZBS7SzB+9Yh6T0i3Ryw== X-Received: by 2002:a5d:430d:0:b0:33a:eb10:e9e8 with SMTP id h13-20020a5d430d000000b0033aeb10e9e8mr10366269wrq.43.1708457194876; Tue, 20 Feb 2024 11:26:34 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Eduardo Habkost , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Mark Cave-Ayland , Bernhard Beschow , Richard Henderson , Markus Armbruster , Alexander Graf , Anton Johansson , Paolo Bonzini , Thomas Huth , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [RFC PATCH 1/2] target/alpha: Expose TMR and SMP IRQ lines via QDev Date: Tue, 20 Feb 2024 20:26:24 +0100 Message-ID: <20240220192625.17944-2-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240220192625.17944-1-philmd@linaro.org> References: <20240220192625.17944-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=philmd@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1708457285688100001 In order to remove calls to cpu_interrupt() from hw/ code, expose the TMR and SMP interrupts via QDev as named GPIOs. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/alpha/cpu.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index bf70173a25..619cd54593 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -25,6 +25,31 @@ #include "cpu.h" #include "exec/exec-all.h" =20 +#ifndef CONFIG_USER_ONLY +static void alpha_cpu_tmr_irq(void *opaque, int irq, int level) +{ + DeviceState *dev =3D opaque; + CPUState *cs =3D CPU(dev); + + if (level) { + cs->interrupt_request |=3D CPU_INTERRUPT_TIMER; + } else { + cs->interrupt_request &=3D ~CPU_INTERRUPT_TIMER; + } +} + +static void alpha_cpu_smp_irq(void *opaque, int irq, int level) +{ + DeviceState *dev =3D opaque; + CPUState *cs =3D CPU(dev); + + if (level) { + cs->interrupt_request |=3D CPU_INTERRUPT_SMP; + } else { + cs->interrupt_request &=3D ~CPU_INTERRUPT_SMP; + } +} +#endif =20 static void alpha_cpu_set_pc(CPUState *cs, vaddr value) { @@ -89,6 +114,11 @@ static void alpha_cpu_realizefn(DeviceState *dev, Error= **errp) =20 qemu_init_vcpu(cs); =20 +#ifndef CONFIG_USER_ONLY + qdev_init_gpio_in_named(dev, alpha_cpu_tmr_irq, "TMR", 1); + qdev_init_gpio_in_named(dev, alpha_cpu_smp_irq, "SMP", 1); +#endif + acc->parent_realize(dev, errp); } =20 --=20 2.41.0