From nobody Thu Nov 14 17:42:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1708438465; cv=none; d=zohomail.com; s=zohoarc; b=Cj8zOWRRV3HVTtyuNV89R4CIc0kwNLtwFYgOggHC2HYrmjOukmWYL7f+3NH5BUq7GBfGM3fM/axVQ2irExz0rT5I0CmisdSOp+GR5Ia8PpQqzmLVjUEXHJR7B4XZZ6JXW31KqhOItUfTFnq5PyPtlJspugZ3hOg8Tsb+cUY1Bo0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1708438465; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=3oy1cTPiODjDyZVTXKgWROO+B+tLSOmUJ82ad3KEC3Q=; b=lNvK3VpoVvrBGJx4nKGLMUsOC4ZueYTTFn8v6Hq84h7eNskDjWWFhW+vopprdymzIORkBxekvnLi25jL03Jn2y+4hQIknd/JD0qu8rUBrrv0pkfl/2wDOTejzZ7tVpGXyBiQ+JerVV4z84FA1DPtQh11PsnuBynWBuMZKH1gSTk= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1708438465259951.2165480950773; Tue, 20 Feb 2024 06:14:25 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rcQsE-00027I-Ci; Tue, 20 Feb 2024 09:13:30 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rcP5i-00006M-9S; Tue, 20 Feb 2024 07:19:18 -0500 Received: from szxga05-in.huawei.com ([45.249.212.191]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rcP5b-0004ML-Ev; Tue, 20 Feb 2024 07:19:15 -0500 Received: from mail.maildlp.com (unknown [172.19.163.44]) by szxga05-in.huawei.com (SkyGuard) with ESMTP id 4TfJH52HHpz1FL8R; Tue, 20 Feb 2024 20:14:09 +0800 (CST) Received: from kwepemi500008.china.huawei.com (unknown [7.221.188.139]) by mail.maildlp.com (Postfix) with ESMTPS id 071F6140118; Tue, 20 Feb 2024 20:19:00 +0800 (CST) Received: from huawei.com (10.67.174.55) by kwepemi500008.china.huawei.com (7.221.188.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Tue, 20 Feb 2024 20:18:59 +0800 To: , , , , , , CC: Subject: [RFC PATCH 1/3] target/arm: Implement FEAT_NMI to support Non-maskable Interrupt Date: Tue, 20 Feb 2024 12:17:50 +0000 Message-ID: <20240220121752.490665-2-ruanjinjie@huawei.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240220121752.490665-1-ruanjinjie@huawei.com> References: <20240220121752.490665-1-ruanjinjie@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.67.174.55] X-ClientProxiedBy: dggems705-chm.china.huawei.com (10.3.19.182) To kwepemi500008.china.huawei.com (7.221.188.139) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=45.249.212.191; envelope-from=ruanjinjie@huawei.com; helo=szxga05-in.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Tue, 20 Feb 2024 09:13:26 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jinjie Ruan From: Jinjie Ruan via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1708438466607100003 Content-Type: text/plain; charset="utf-8" Enable Non-maskable Interrupt feature. Enable HCRX register feature to support TALLINT read/write. Add support for enable/disable NMI at qemu startup as below: qemu-system-aarch64 -cpu cortex-a53/a57/a72/a76,nmi=3D[on/off] Add support for allint read/write as follow: mrs , ALLINT // read allint msr ALLINT, // write allint with imm msr ALLINT, # // write allint with 1 or 0 Signed-off-by: Jinjie Ruan --- target/arm/cpu-features.h | 5 +++++ target/arm/cpu.h | 2 ++ target/arm/cpu64.c | 31 +++++++++++++++++++++++++++++++ target/arm/helper.c | 33 +++++++++++++++++++++++++++++++++ target/arm/internals.h | 1 + target/arm/tcg/a64.decode | 1 + target/arm/tcg/cpu64.c | 11 +++++++++++ target/arm/tcg/helper-a64.c | 25 +++++++++++++++++++++++++ target/arm/tcg/helper-a64.h | 1 + target/arm/tcg/translate-a64.c | 10 ++++++++++ 10 files changed, 120 insertions(+) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index 7567854db6..2ad1179be7 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -681,6 +681,11 @@ static inline bool isar_feature_aa64_sme(const ARMISAR= egisters *id) return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SME) !=3D 0; } =20 +static inline bool isar_feature_aa64_nmi(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, NMI) !=3D 0; +} + static inline bool isar_feature_aa64_tgran4_lpa2(const ARMISARegisters *id) { return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4) >=3D 1; diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 63f31e0d98..ea6e8d6501 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -261,6 +261,7 @@ typedef struct CPUArchState { uint32_t btype; /* BTI branch type. spsr[11:10]. */ uint64_t daif; /* exception masks, in the bits they are in PSTATE */ uint64_t svcr; /* PSTATE.{SM,ZA} in the bits they are in SVCR */ + uint64_t allint; /* All IRQ or FIQ interrupt mask, in the bit in PSTAT= E */ =20 uint64_t elr_el[4]; /* AArch64 exception link regs */ uint64_t sp_el[4]; /* AArch64 banked stack pointers */ @@ -1543,6 +1544,7 @@ FIELD(VTCR, SL2, 33, 1) #define PSTATE_D (1U << 9) #define PSTATE_BTYPE (3U << 10) #define PSTATE_SSBS (1U << 12) +#define PSTATE_ALLINT (1U << 13) #define PSTATE_IL (1U << 20) #define PSTATE_SS (1U << 21) #define PSTATE_PAN (1U << 22) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 8e30a7993e..3a5a3fda1b 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -295,6 +295,22 @@ static void cpu_arm_set_sve(Object *obj, bool value, E= rror **errp) cpu->isar.id_aa64pfr0 =3D t; } =20 +static bool cpu_arm_get_nmi(Object *obj, Error **errp) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + return cpu_isar_feature(aa64_nmi, cpu); +} + +static void cpu_arm_set_nmi(Object *obj, bool value, Error **errp) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + uint64_t t; + + t =3D cpu->isar.id_aa64pfr1; + t =3D FIELD_DP64(t, ID_AA64PFR1, NMI, value); + cpu->isar.id_aa64pfr1 =3D t; +} + void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp) { uint32_t vq_map =3D cpu->sme_vq.map; @@ -472,6 +488,11 @@ void aarch64_add_sme_properties(Object *obj) #endif } =20 +void aarch64_add_nmi_properties(Object *obj) +{ + object_property_add_bool(obj, "nmi", cpu_arm_get_nmi, cpu_arm_set_nmi); +} + void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) { ARMPauthFeature features =3D cpu_isar_feature(pauth_feature, cpu); @@ -593,9 +614,14 @@ void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp) =20 static void aarch64_a57_initfn(Object *obj) { + uint64_t t; ARMCPU *cpu =3D ARM_CPU(obj); =20 cpu->dtb_compatible =3D "arm,cortex-a57"; + t =3D cpu->isar.id_aa64mmfr1; + t =3D FIELD_DP64(t, ID_AA64MMFR1, HCX, 1); /* FEAT_HCX */ + cpu->isar.id_aa64mmfr1 =3D t; + aarch64_add_nmi_properties(obj); set_feature(&cpu->env, ARM_FEATURE_V8); set_feature(&cpu->env, ARM_FEATURE_NEON); set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); @@ -650,9 +676,14 @@ static void aarch64_a57_initfn(Object *obj) =20 static void aarch64_a53_initfn(Object *obj) { + uint64_t t; ARMCPU *cpu =3D ARM_CPU(obj); =20 cpu->dtb_compatible =3D "arm,cortex-a53"; + t =3D cpu->isar.id_aa64mmfr1; + t =3D FIELD_DP64(t, ID_AA64MMFR1, HCX, 1); /* FEAT_HCX */ + cpu->isar.id_aa64mmfr1 =3D t; + aarch64_add_nmi_properties(obj); set_feature(&cpu->env, ARM_FEATURE_V8); set_feature(&cpu->env, ARM_FEATURE_NEON); set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); diff --git a/target/arm/helper.c b/target/arm/helper.c index 90c4fb72ce..1194e1e2db 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4618,6 +4618,28 @@ static void aa64_daif_write(CPUARMState *env, const = ARMCPRegInfo *ri, env->daif =3D value & PSTATE_DAIF; } =20 +static void aa64_allint_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + if (cpu_isar_feature(aa64_nmi, env_archcpu(env))) { + env->allint =3D value & PSTATE_ALLINT; + } +} + +static CPAccessResult aa64_allint_access(CPUARMState *env, + const ARMCPRegInfo *ri, bool isre= ad) +{ + if (arm_current_el(env) =3D=3D 0) { + return CP_ACCESS_TRAP_UNCATEGORIZED; + } + + if (arm_current_el(env) =3D=3D 1 && arm_is_el2_enabled(env) && + cpu_isar_feature(aa64_hcx, env_archcpu(env)) && + (env->cp15.hcrx_el2 & HCRX_TALLINT)) + return CP_ACCESS_TRAP_EL2; + return CP_ACCESS_OK; +} + static uint64_t aa64_pan_read(CPUARMState *env, const ARMCPRegInfo *ri) { return env->pstate & PSTATE_PAN; @@ -5437,6 +5459,12 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { .access =3D PL0_RW, .accessfn =3D aa64_daif_access, .fieldoffset =3D offsetof(CPUARMState, daif), .writefn =3D aa64_daif_write, .resetfn =3D arm_cp_reset_ignore }, + { .name =3D "ALLINT", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .opc2 =3D 0, .crn =3D 4, .crm =3D 3, + .type =3D ARM_CP_NO_RAW, + .access =3D PL1_RW, .accessfn =3D aa64_allint_access, + .fieldoffset =3D offsetof(CPUARMState, allint), + .writefn =3D aa64_allint_write, .resetfn =3D arm_cp_reset_ignore }, { .name =3D "FPCR", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .opc2 =3D 0, .crn =3D 4, .crm =3D 4, .access =3D PL0_RW, .type =3D ARM_CP_FPU | ARM_CP_SUPPRESS_TB_END, @@ -6056,6 +6084,11 @@ static void hcrx_write(CPUARMState *env, const ARMCP= RegInfo *ri, valid_mask |=3D HCRX_MSCEN | HCRX_MCE2; } =20 + /* FEAT_NMI adds TALLINT */ + if (cpu_isar_feature(aa64_nmi, env_archcpu(env))) { + valid_mask |=3D HCRX_TALLINT; + } + /* Clear RES0 bits. */ env->cp15.hcrx_el2 =3D value & valid_mask; } diff --git a/target/arm/internals.h b/target/arm/internals.h index 50bff44549..2b9f287c52 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1466,6 +1466,7 @@ void aarch64_max_tcg_initfn(Object *obj); void aarch64_add_pauth_properties(Object *obj); void aarch64_add_sve_properties(Object *obj); void aarch64_add_sme_properties(Object *obj); +void aarch64_add_nmi_properties(Object *obj); #endif =20 /* Read the CONTROL register as the MRS instruction would. */ diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index 8a20dce3c8..3588080024 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -207,6 +207,7 @@ MSR_i_DIT 1101 0101 0000 0 011 0100 .... 010 1111= 1 @msr_i MSR_i_TCO 1101 0101 0000 0 011 0100 .... 100 11111 @msr_i MSR_i_DAIFSET 1101 0101 0000 0 011 0100 .... 110 11111 @msr_i MSR_i_DAIFCLEAR 1101 0101 0000 0 011 0100 .... 111 11111 @msr_i +MSR_i_ALLINT 1101 0101 0000 0 001 0100 .... 000 11111 @msr_i MSR_i_SVCR 1101 0101 0000 0 011 0100 0 mask:2 imm:1 011 11111 =20 # MRS, MSR (register), SYS, SYSL. These are all essentially the diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 5fba2c0f04..e08eb0ce94 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -293,9 +293,14 @@ static void aarch64_a55_initfn(Object *obj) =20 static void aarch64_a72_initfn(Object *obj) { + uint64_t t; ARMCPU *cpu =3D ARM_CPU(obj); =20 cpu->dtb_compatible =3D "arm,cortex-a72"; + t =3D cpu->isar.id_aa64mmfr1; + t =3D FIELD_DP64(t, ID_AA64MMFR1, HCX, 1); /* FEAT_HCX */ + cpu->isar.id_aa64mmfr1 =3D t; + aarch64_add_nmi_properties(obj); set_feature(&cpu->env, ARM_FEATURE_V8); set_feature(&cpu->env, ARM_FEATURE_NEON); set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); @@ -348,9 +353,14 @@ static void aarch64_a72_initfn(Object *obj) =20 static void aarch64_a76_initfn(Object *obj) { + uint64_t t; ARMCPU *cpu =3D ARM_CPU(obj); =20 cpu->dtb_compatible =3D "arm,cortex-a76"; + t =3D cpu->isar.id_aa64mmfr1; + t =3D FIELD_DP64(t, ID_AA64MMFR1, HCX, 1); /* FEAT_HCX */ + cpu->isar.id_aa64mmfr1 =3D t; + aarch64_add_nmi_properties(obj); set_feature(&cpu->env, ARM_FEATURE_V8); set_feature(&cpu->env, ARM_FEATURE_NEON); set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); @@ -1175,6 +1185,7 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64PFR1, RAS_FRAC, 0); /* FEAT_RASv1p1 + FEAT= _DoubleFault */ t =3D FIELD_DP64(t, ID_AA64PFR1, SME, 1); /* FEAT_SME */ t =3D FIELD_DP64(t, ID_AA64PFR1, CSV2_FRAC, 0); /* FEAT_CSV2_2 */ + t =3D FIELD_DP64(t, ID_AA64PFR1, NMI, 0); /* FEAT_NMI */ cpu->isar.id_aa64pfr1 =3D t; =20 t =3D cpu->isar.id_aa64mmfr0; diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c index ebaa7f00df..9b2a7cd891 100644 --- a/target/arm/tcg/helper-a64.c +++ b/target/arm/tcg/helper-a64.c @@ -66,6 +66,31 @@ void HELPER(msr_i_spsel)(CPUARMState *env, uint32_t imm) update_spsel(env, imm); } =20 +static void allint_check(CPUARMState *env, uint32_t op, + uint32_t imm, uintptr_t ra) +{ + /* ALLINT update to PSTATE.*/ + if (arm_current_el(env) =3D=3D 0) { + raise_exception_ra(env, EXCP_UDEF, + syn_aa64_sysregtrap(0, extract32(op, 0, 3), + extract32(op, 3, 3), 4, + imm, 0x1f, 0), + exception_target_el(env), ra); + } + /* todo */ +} + +void HELPER(msr_i_allint)(CPUARMState *env, uint32_t imm) +{ + allint_check(env, 0x8, imm, GETPC()); + if (imm =3D=3D 1) { + env->allint |=3D PSTATE_ALLINT; + } else { + env->allint &=3D ~PSTATE_ALLINT; + } + arm_rebuild_hflags(env); +} + static void daif_check(CPUARMState *env, uint32_t op, uint32_t imm, uintptr_t ra) { diff --git a/target/arm/tcg/helper-a64.h b/target/arm/tcg/helper-a64.h index 575a5dab7d..3aec703d4a 100644 --- a/target/arm/tcg/helper-a64.h +++ b/target/arm/tcg/helper-a64.h @@ -22,6 +22,7 @@ DEF_HELPER_FLAGS_1(rbit64, TCG_CALL_NO_RWG_SE, i64, i64) DEF_HELPER_2(msr_i_spsel, void, env, i32) DEF_HELPER_2(msr_i_daifset, void, env, i32) DEF_HELPER_2(msr_i_daifclear, void, env, i32) +DEF_HELPER_2(msr_i_allint, void, env, i32) DEF_HELPER_3(vfp_cmph_a64, i64, f16, f16, ptr) DEF_HELPER_3(vfp_cmpeh_a64, i64, f16, f16, ptr) DEF_HELPER_3(vfp_cmps_a64, i64, f32, f32, ptr) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 340265beb0..f1800f7c71 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -2036,6 +2036,16 @@ static bool trans_MSR_i_DAIFCLEAR(DisasContext *s, a= rg_i *a) return true; } =20 +static bool trans_MSR_i_ALLINT(DisasContext *s, arg_i *a) +{ + if (!dc_isar_feature(aa64_nmi, s) || s->current_el =3D=3D 0) { + return false; + } + gen_helper_msr_i_allint(tcg_env, tcg_constant_i32(a->imm)); + s->base.is_jmp =3D DISAS_TOO_MANY; + return true; +} + static bool trans_MSR_i_SVCR(DisasContext *s, arg_MSR_i_SVCR *a) { if (!dc_isar_feature(aa64_sme, s) || a->mask =3D=3D 0) { --=20 2.34.1