From nobody Thu Nov 14 17:12:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.intel.com ARC-Seal: i=1; a=rsa-sha256; t=1708420406; cv=none; d=zohomail.com; s=zohoarc; b=M1pMlJIeTJSk60yngOoXT7saW1FjdLifyA4GiUkRpvGcGtwI5v6LgQFtnNl5zEjhg5ngz3DZEnWO0sVmL70OFzr2GelFrs5uP1U7c7+3LoiK/GqGLal7ro7v/Eq1HFkvh33OzwmmKxK5bUHiqQb3GjXg3PLJ1HmG20xYQ8ZVXqs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1708420406; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=xlHVDIczWDzsqvnRJ1iEbajqyhhtoEAGnHkRgqd3qOk=; b=R0nIkqzYVCCnuxjq1sE096eCgpDVM1DczrseBeyBPBbMOqcpN04tMizjBR+GF55+4X9UxRVZ5TeFJGQKbISHrVa1NiRMiINX0MqkIX3hFDkkNtQbyNcgr5xJKQfniuzMWQ0WnsRtA6kvqUwzhMTsOWv9ObBsxm1Hp5FF3HDUsBU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1708420406028855.0682605391528; Tue, 20 Feb 2024 01:13:26 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rcMB0-0001Dh-6m; Tue, 20 Feb 2024 04:12:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rcMAy-00012Z-2d; Tue, 20 Feb 2024 04:12:32 -0500 Received: from mgamail.intel.com ([192.198.163.17]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rcMAw-0003Tv-0l; Tue, 20 Feb 2024 04:12:31 -0500 Received: from orviesa007.jf.intel.com ([10.64.159.147]) by fmvoesa111.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Feb 2024 01:12:28 -0800 Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.36]) by orviesa007.jf.intel.com with ESMTP; 20 Feb 2024 01:12:23 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1708420350; x=1739956350; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=L0AbdOq+EtfWgzb7EW1UTRtjP/6zXcB3r698FBuEvgE=; b=GotJBlCOWiDbORUrFW9FJJP0MFSK+B1f7F/ibCay2WDFrsCEYfL7Lu5Q Se71/DNobx7db5OmZ4L0NsuLWLnY4VFS13qRPSd7cNZ6MSn+QhfoGAnbD MXm8Je/oAlVQuC6zHwsKn43f+y1c8syzoXjAEnbx65JU/GWMx8Dg3ygRx lgdj8WuCplKH+7UXhD8PhWiyXy0A26GZeyOgkdfSL/oYx5TXcO2WP+XjA ca87IWVT/J7yFJH22wkwuSonvWg3z0wjd+d5EzCIAmHkkV/hLpHj/aQ5z QdCxAx6DWBH7zcQKoyS0t5dlRcsjaYbWR1AeE94/eVgOtPHf6vvVaPVBl A==; X-IronPort-AV: E=McAfee;i="6600,9927,10989"; a="2375048" X-IronPort-AV: E=Sophos;i="6.06,172,1705392000"; d="scan'208";a="2375048" X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.06,172,1705392000"; d="scan'208";a="5013156" From: Zhao Liu To: =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Eduardo Habkost , Marcel Apfelbaum , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , "Michael S . Tsirkin" , Paolo Bonzini , Richard Henderson , Eric Blake , Markus Armbruster , Marcelo Tosatti , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Peter Maydell , Jonathan Cameron , Sia Jee Heng Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Zhenyu Wang , Dapeng Mi , Yongwei Ma , Zhao Liu Subject: [RFC 8/8] qemu-options: Add the cache topology description of -smp Date: Tue, 20 Feb 2024 17:25:04 +0800 Message-Id: <20240220092504.726064-9-zhao1.liu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240220092504.726064-1-zhao1.liu@linux.intel.com> References: <20240220092504.726064-1-zhao1.liu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=192.198.163.17; envelope-from=zhao1.liu@linux.intel.com; helo=mgamail.intel.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.072, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1708420406500100001 Content-Type: text/plain; charset="utf-8" From: Zhao Liu Signed-off-by: Zhao Liu --- qemu-options.hx | 54 ++++++++++++++++++++++++++++++++++++++++++------- 1 file changed, 47 insertions(+), 7 deletions(-) diff --git a/qemu-options.hx b/qemu-options.hx index 70eaf3256685..85c78c99a3b0 100644 --- a/qemu-options.hx +++ b/qemu-options.hx @@ -281,7 +281,9 @@ ERST =20 DEF("smp", HAS_ARG, QEMU_OPTION_smp, "-smp [[cpus=3D]n][,maxcpus=3Dmaxcpus][,drawers=3Ddrawers][,books=3Dbo= oks][,sockets=3Dsockets]\n" - " [,dies=3Ddies][,clusters=3Dclusters][,cores=3Dcores][,= threads=3Dthreads]\n" + " [,dies=3Ddies][,clusters=3Dclusters][,modules=3Dmodule= s][,cores=3Dcores]\n" + " [,threads=3Dthreads][,l1d-cache=3Dlevel][,l1i-cache=3D= level][,l2-cache=3Dlevel]\n" + " [,l3-cache=3Dlevel]\n" " set the number of initial CPUs to 'n' [default=3D1]\n" " maxcpus=3D maximum number of total CPUs, including\n" " offline CPUs for hotplug, etc\n" @@ -290,9 +292,14 @@ DEF("smp", HAS_ARG, QEMU_OPTION_smp, " sockets=3D number of sockets in one book\n" " dies=3D number of dies in one socket\n" " clusters=3D number of clusters in one die\n" - " cores=3D number of cores in one cluster\n" + " modules=3D number of modules in one cluster\n" + " cores=3D number of cores in one module\n" " threads=3D number of threads in one core\n" - "Note: Different machines may have different subsets of the CPU topolo= gy\n" + " l1d-cache=3D topology level of L1 D-cache\n" + " l1i-cache=3D topology level of L1 I-cache\n" + " l2-cache=3D topology level of L2 cache\n" + " l3-cache=3D topology level of L3 cache\n" + "Note: Different machines may have different subsets of the CPU and ca= che topology\n" " parameters supported, so the actual meaning of the supported pa= rameters\n" " will vary accordingly. For example, for a machine type that sup= ports a\n" " three-level CPU hierarchy of sockets/cores/threads, the paramet= ers will\n" @@ -306,7 +313,7 @@ DEF("smp", HAS_ARG, QEMU_OPTION_smp, " must be set as 1 in the purpose of correct parsing.\n", QEMU_ARCH_ALL) SRST -``-smp [[cpus=3D]n][,maxcpus=3Dmaxcpus][,sockets=3Dsockets][,dies=3Ddies][= ,clusters=3Dclusters][,cores=3Dcores][,threads=3Dthreads]`` +``-smp [[cpus=3D]n][,maxcpus=3Dmaxcpus][,drawers=3Ddrawers][,books=3Dbooks= ][,sockets=3Dsockets][,dies=3Ddies][,clusters=3Dclusters][,modules=3Dmodule= s][,cores=3Dcores][,threads=3Dthreads][,l1d-cache=3Dlevel][,l1i-cache=3Dlev= el][,l2-cache=3Dlevel][,l3-cache=3Dlevel]`` Simulate a SMP system with '\ ``n``\ ' CPUs initially present on the machine type board. On boards supporting CPU hotplug, the optional '\ ``maxcpus``\ ' parameter can be set to enable further CPUs to be @@ -320,15 +327,34 @@ SRST Both parameters are subject to an upper limit that is determined by the specific machine type chosen. =20 + CPU topology parameters include '\ ``drawers``\ ', '\ ``books``\ ', + '\ ``sockets``\ ', '\ ``dies``\ ', '\ ``clusters``\ ', '\ ``modules``\= ', + '\ ``cores``\ ' and '\ ``threads``\ '. These CPU parameters accept only + integers and are used to specify the number of specific topology domai= ns + under the corresponding topology level. + To control reporting of CPU topology information, values of the topolo= gy parameters can be specified. Machines may only support a subset of the - parameters and different machines may have different subsets supported - which vary depending on capacity of the corresponding CPU targets. So - for a particular machine type board, an expected topology hierarchy can + CPU topology parameters and different machines may have different subs= ets + supported which vary depending on capacity of the corresponding CPU ta= rgets. + So for a particular machine type board, an expected topology hierarchy= can be defined through the supported sub-option. Unsupported parameters can also be provided in addition to the sub-option, but their values must = be set as 1 in the purpose of correct parsing. =20 + Cache topology parameters include '\ ``l1d-cache``\ ', '\ ``l1i-cache`= `\ ', + '\ ``l2-cache``\ ' and '\ ``l3-cache``\ '. These cache topology parame= ters + accept the strings of CPU topology levels (such as '\ ``drawer``\ ', '= \ ``book``\ ', + '\ ``socket``\ ', '\ ``die``\ ', '\ ``cluster``\ ', '\ ``module``\ ', + '\ ``core``\ ' or '\ ``thread``\ '). Exactly which topology level stri= ngs + could be accepted as the parameter depends on the machine's support fo= r the + corresponding CPU topology level. + + Machines may also only support a subset of the cache topology paramete= rs. + Unsupported cache topology parameters will be omitted, and correspondi= ngly, + the target CPU's cache topology will use the its default cache topology + setting. + Either the initial CPU count, or at least one of the topology paramete= rs must be specified. The specified parameters must be greater than zero, explicit configuration like "cpus=3D0" is not allowed. Values for any @@ -354,6 +380,20 @@ SRST =20 -smp 32,sockets=3D2,dies=3D2,modules=3D2,cores=3D2,threads=3D2,max= cpus=3D32 =20 + The following sub-option defines a CPU topology hierarchy (2 sockets + totally on the machine, 2 dies per socket, 2 modules per die, 2 cores = per + module, 2 threads per core) with 3-level cache topology hierarchy (L1 + D-cache per core, L1 I-cache per core, L2 cache per core and L3 cache = per + die) for PC machines which support sockets/dies/modules/cores/threads. + Some members of the CPU topology option can be omitted but their values + will be automatically computed. Some members of the cache topology + option can also be omitted and target CPU will use the default topolog= y.: + + :: + + -smp 32,sockets=3D2,dies=3D2,modules=3D2,cores=3D2,threads=3D2,max= cpus=3D32,\ + l1d-cache=3Dcore,l1i-cache=3Dcore,l2-cache=3Dcore,l3-cache=3D= die + The following sub-option defines a CPU topology hierarchy (2 sockets totally on the machine, 2 clusters per socket, 2 cores per cluster, 2 threads per core) for ARM virt machines which support sockets/cluste= rs --=20 2.34.1