From nobody Thu Nov 14 18:09:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.intel.com ARC-Seal: i=1; a=rsa-sha256; t=1708420438; cv=none; d=zohomail.com; s=zohoarc; b=i1KYONCSPUN34GMj6roGsGisAyYp6JTAVSlZYqT7dD4c+85nJiD8zi/MDzGX721vkfExFbufTWGXXaEFhNI7glMzJzzHdYYErEfZ0XMn8or3r6tEUGcYRknYTUdvNZUveyFPUtfGB+g6+q26yzW8DQaGiIFTYE39RoPOouztTFA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1708420438; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=cUYeLAZW0KBw1vwajpBZMV3SU2/ZD+h09pXDANbjwB0=; b=PaAWXMkQGE5FxVwDu6I9Bm6RsuGqh5xlsZo8Pql96KQbKRi1XLODOotMF7j8BNrCIh6LYAIgkfb5a2jh1y5bfEFyWhjy3GiRPTiMrquzqpxo8EgI1kq5peTfq81efLa1Dff4KSp0DUcZxbFVNCN3qUDAaRJBFOBE8POLPUjI1bs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1708420438156254.20434207252038; Tue, 20 Feb 2024 01:13:58 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rcMAr-0000vC-CQ; Tue, 20 Feb 2024 04:12:25 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rcMAj-0000pV-P8; Tue, 20 Feb 2024 04:12:17 -0500 Received: from mgamail.intel.com ([192.198.163.17]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rcMAg-0003Nd-R0; Tue, 20 Feb 2024 04:12:16 -0500 Received: from orviesa007.jf.intel.com ([10.64.159.147]) by fmvoesa111.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Feb 2024 01:12:12 -0800 Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.36]) by orviesa007.jf.intel.com with ESMTP; 20 Feb 2024 01:12:06 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1708420335; x=1739956335; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=nmSGxPZR9yko6kQTreGOACQxkbHYm1OXOe8DkqwHjxw=; b=XKaqLwq0ko/Oio7cv+9iZA8MGZEw0IJYsvE5kVu1t8nRLtgAGctNyJKX Sjve9UHWglmFsvjKxJp8loYY9DDz07KXWRhVfn14TWivz6t0eiWS/Ea81 HYQdN1QLGAYwsE1Flczpaub4sFwxS+mzS8Am/D1WF7MMUVjYUAus056Sq QWSKPiDB6y5UxQMz2rj67CY89XtPHEXUB1S/cyo3ieypUGQdypbSlxTBT LHkwbo1BSStaxWCbyJkUg4c/xrxBCyy7DAdxWXdik7Q8OhvPsDS3vay90 vPeQz57tjszZqcd9LfHu1t4Mqc7NTINVtJFhkxJtQSt3mbNQWgAceO57w Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10989"; a="2375008" X-IronPort-AV: E=Sophos;i="6.06,172,1705392000"; d="scan'208";a="2375008" X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.06,172,1705392000"; d="scan'208";a="5013025" From: Zhao Liu To: =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Eduardo Habkost , Marcel Apfelbaum , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , "Michael S . Tsirkin" , Paolo Bonzini , Richard Henderson , Eric Blake , Markus Armbruster , Marcelo Tosatti , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Peter Maydell , Jonathan Cameron , Sia Jee Heng Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Zhenyu Wang , Dapeng Mi , Yongwei Ma , Zhao Liu Subject: [RFC 5/8] i386/cpu: Support thread and module level cache topology Date: Tue, 20 Feb 2024 17:25:01 +0800 Message-Id: <20240220092504.726064-6-zhao1.liu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240220092504.726064-1-zhao1.liu@linux.intel.com> References: <20240220092504.726064-1-zhao1.liu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=192.198.163.17; envelope-from=zhao1.liu@linux.intel.com; helo=mgamail.intel.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.072, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1708420438536100001 Content-Type: text/plain; charset="utf-8" From: Zhao Liu Allows cache to be defined at the thread and module level. This increases flexibility for x86 users to customize their cache topology. Signed-off-by: Zhao Liu --- target/i386/cpu.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 725d7e70182d..d7cb0f1e49b4 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -241,9 +241,15 @@ static uint32_t max_thread_ids_for_cache(X86CPUTopoInf= o *topo_info, uint32_t num_ids =3D 0; =20 switch (share_level) { + case CPU_TOPO_LEVEL_THREAD: + num_ids =3D 1; + break; case CPU_TOPO_LEVEL_CORE: num_ids =3D 1 << apicid_core_offset(topo_info); break; + case CPU_TOPO_LEVEL_MODULE: + num_ids =3D 1 << apicid_module_offset(topo_info); + break; case CPU_TOPO_LEVEL_DIE: num_ids =3D 1 << apicid_die_offset(topo_info); break; @@ -251,10 +257,6 @@ static uint32_t max_thread_ids_for_cache(X86CPUTopoInf= o *topo_info, num_ids =3D 1 << apicid_pkg_offset(topo_info); break; default: - /* - * Currently there is no use case for SMT and MODULE, so use - * assert directly to facilitate debugging. - */ g_assert_not_reached(); } =20 --=20 2.34.1