From nobody Fri Nov 1 07:34:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1708363985; cv=none; d=zohomail.com; s=zohoarc; b=ASTndUrqPdRrgWe94QGeJlUZyGbB6GbIwc8JJ8lw80tnV87qJumS5Lz6sW/kgTOv04p5rsn88eK7tGBU2dlfeqdjvhlxL0t2rGjXA0wvyarff95fjUB4Gdieg6PT3oxJcChfPXNcsMx9cIC7WABWGWtZRrFSYtzkEeagLSv7XPo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1708363985; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=F4bM9rd1ver07psa+i00iT/WWFtvlZanoEpEN43MAOI=; b=MtY6AbPwJRCvBTXKWwoz3jSBuF9v/F9tJXz5ybepUP/57195T56cPaGsORBUsQewlnJmuRllhv78/KIr5JNA8TavMnKBpsHyuQhTOZa37KyuP0NGjJM9h1tYfacTbqtuwMbrppLLC4vYAGyN4+FTgsZJXUbPkKvWEfV62Qp/6HE= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1708363985474782.9787714156583; Mon, 19 Feb 2024 09:33:05 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rc7Vj-000411-W9; Mon, 19 Feb 2024 12:33:00 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rc7Vi-00040Q-8Z for qemu-devel@nongnu.org; Mon, 19 Feb 2024 12:32:58 -0500 Received: from frasgout.his.huawei.com ([185.176.79.56]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rc7Vg-0004Pw-5M for qemu-devel@nongnu.org; Mon, 19 Feb 2024 12:32:58 -0500 Received: from mail.maildlp.com (unknown [172.18.186.231]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4TdqJQ6cJFz6JB3W; Tue, 20 Feb 2024 01:28:38 +0800 (CST) Received: from lhrpeml500005.china.huawei.com (unknown [7.191.163.240]) by mail.maildlp.com (Postfix) with ESMTPS id 8B52B140D30; Tue, 20 Feb 2024 01:32:53 +0800 (CST) Received: from SecurePC-101-06.china.huawei.com (10.122.247.231) by lhrpeml500005.china.huawei.com (7.191.163.240) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Mon, 19 Feb 2024 17:32:53 +0000 To: , Peter Maydell , Gregory Price , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Sajjan Rao , Dimitrios Palyvos , , Paolo Bonzini , Eduardo Habkost , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= CC: , Subject: [PATCH v2 2/3] target/i386: Enable page walking from MMIO memory Date: Mon, 19 Feb 2024 17:31:52 +0000 Message-ID: <20240219173153.12114-3-Jonathan.Cameron@huawei.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240219173153.12114-1-Jonathan.Cameron@huawei.com> References: <20240219173153.12114-1-Jonathan.Cameron@huawei.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.122.247.231] X-ClientProxiedBy: lhrpeml100006.china.huawei.com (7.191.160.224) To lhrpeml500005.china.huawei.com (7.191.163.240) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=jonathan.cameron@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01, WEIRD_PORT=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jonathan Cameron From: Jonathan Cameron via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1708363987372100003 From: Gregory Price CXL emulation of interleave requires read and write hooks due to requirement for subpage granularity. The Linux kernel stack now enables using this memory as conventional memory in a separate NUMA node. If a process is deliberately forced to run from that node $ numactl --membind=3D1 ls the page table walk on i386 fails. Useful part of backtrace: (cpu=3Dcpu@entry=3D0x555556fd9000, fmt=3Dfmt@entry=3D0x555555fe3378 "cp= u_io_recompile: could not find TB for pc=3D%p") at ../../cpu-target.c:359 (retaddr=3D0, addr=3D19595792376, attrs=3D..., xlat=3D, = cpu=3D0x555556fd9000, out_offset=3D) at ../../accel/tcg/cputlb.c:1339 (cpu=3D0x555556fd9000, full=3D0x7fffee0d96e0, ret_be=3Dret_be@entry=3D0= , addr=3D19595792376, size=3Dsize@entry=3D8, mmu_idx=3D4, type=3DMMU_DATA_L= OAD, ra=3D0) at ../../accel/tcg/cputlb.c:2030 (cpu=3Dcpu@entry=3D0x555556fd9000, p=3Dp@entry=3D0x7ffff56fddc0, mmu_id= x=3D, type=3Dtype@entry=3DMMU_DATA_LOAD, memop=3D, ra=3Dra@entry=3D0) at ../../accel/tcg/cputlb.c:2356 (cpu=3Dcpu@entry=3D0x555556fd9000, addr=3Daddr@entry=3D19595792376, oi= =3Doi@entry=3D52, ra=3Dra@entry=3D0, access_type=3Daccess_type@entry=3DMMU_= DATA_LOAD) at ../../accel/tcg/cputlb.c:2439 at ../../accel/tcg/ldst_common.c.inc:301 at ../../target/i386/tcg/sysemu/excp_helper.c:173 (err=3D0x7ffff56fdf80, out=3D0x7ffff56fdf70, mmu_idx=3D0, access_type= =3DMMU_INST_FETCH, addr=3D18446744072116178925, env=3D0x555556fdb7c0) at ../../target/i386/tcg/sysemu/excp_helper.c:578 (cs=3D0x555556fd9000, addr=3D18446744072116178925, size=3D, access_type=3DMMU_INST_FETCH, mmu_idx=3D0, probe=3D, ret= addr=3D0) at ../../target/i386/tcg/sysemu/excp_helper.c:604 Avoid this by plumbing the address all the way down from x86_cpu_tlb_fill() where is available as retaddr to the actual accessors which provide it to probe_access_full() which already handles MMIO accesses. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Suggested-by: Peter Maydell Signed-off-by: Gregory Price Signed-off-by: Jonathan Cameron --- v2: Thanks Richard and Philippe for reviews. - Picked up tags. =20 target/i386/tcg/sysemu/excp_helper.c | 57 +++++++++++++++------------- 1 file changed, 30 insertions(+), 27 deletions(-) diff --git a/target/i386/tcg/sysemu/excp_helper.c b/target/i386/tcg/sysemu/= excp_helper.c index 5b86f439ad..b3bce020f4 100644 --- a/target/i386/tcg/sysemu/excp_helper.c +++ b/target/i386/tcg/sysemu/excp_helper.c @@ -59,14 +59,14 @@ typedef struct PTETranslate { hwaddr gaddr; } PTETranslate; =20 -static bool ptw_translate(PTETranslate *inout, hwaddr addr) +static bool ptw_translate(PTETranslate *inout, hwaddr addr, uint64_t ra) { CPUTLBEntryFull *full; int flags; =20 inout->gaddr =3D addr; flags =3D probe_access_full(inout->env, addr, 0, MMU_DATA_STORE, - inout->ptw_idx, true, &inout->haddr, &full, = 0); + inout->ptw_idx, true, &inout->haddr, &full, = ra); =20 if (unlikely(flags & TLB_INVALID_MASK)) { TranslateFault *err =3D inout->err; @@ -82,20 +82,20 @@ static bool ptw_translate(PTETranslate *inout, hwaddr a= ddr) return true; } =20 -static inline uint32_t ptw_ldl(const PTETranslate *in) +static inline uint32_t ptw_ldl(const PTETranslate *in, uint64_t ra) { if (likely(in->haddr)) { return ldl_p(in->haddr); } - return cpu_ldl_mmuidx_ra(in->env, in->gaddr, in->ptw_idx, 0); + return cpu_ldl_mmuidx_ra(in->env, in->gaddr, in->ptw_idx, ra); } =20 -static inline uint64_t ptw_ldq(const PTETranslate *in) +static inline uint64_t ptw_ldq(const PTETranslate *in, uint64_t ra) { if (likely(in->haddr)) { return ldq_p(in->haddr); } - return cpu_ldq_mmuidx_ra(in->env, in->gaddr, in->ptw_idx, 0); + return cpu_ldq_mmuidx_ra(in->env, in->gaddr, in->ptw_idx, ra); } =20 /* @@ -132,7 +132,8 @@ static inline bool ptw_setl(const PTETranslate *in, uin= t32_t old, uint32_t set) } =20 static bool mmu_translate(CPUX86State *env, const TranslateParams *in, - TranslateResult *out, TranslateFault *err) + TranslateResult *out, TranslateFault *err, + uint64_t ra) { const int32_t a20_mask =3D x86_get_a20_mask(env); const target_ulong addr =3D in->addr; @@ -166,11 +167,11 @@ static bool mmu_translate(CPUX86State *env, const Tra= nslateParams *in, */ pte_addr =3D ((in->cr3 & ~0xfff) + (((addr >> 48) & 0x1ff) << 3)) & a20_mask; - if (!ptw_translate(&pte_trans, pte_addr)) { + if (!ptw_translate(&pte_trans, pte_addr, ra)) { return false; } restart_5: - pte =3D ptw_ldq(&pte_trans); + pte =3D ptw_ldq(&pte_trans, ra); if (!(pte & PG_PRESENT_MASK)) { goto do_fault; } @@ -191,11 +192,11 @@ static bool mmu_translate(CPUX86State *env, const Tra= nslateParams *in, */ pte_addr =3D ((pte & PG_ADDRESS_MASK) + (((addr >> 39) & 0x1ff) << 3)) & a20_mask; - if (!ptw_translate(&pte_trans, pte_addr)) { + if (!ptw_translate(&pte_trans, pte_addr, ra)) { return false; } restart_4: - pte =3D ptw_ldq(&pte_trans); + pte =3D ptw_ldq(&pte_trans, ra); if (!(pte & PG_PRESENT_MASK)) { goto do_fault; } @@ -212,11 +213,11 @@ static bool mmu_translate(CPUX86State *env, const Tra= nslateParams *in, */ pte_addr =3D ((pte & PG_ADDRESS_MASK) + (((addr >> 30) & 0x1ff) << 3)) & a20_mask; - if (!ptw_translate(&pte_trans, pte_addr)) { + if (!ptw_translate(&pte_trans, pte_addr, ra)) { return false; } restart_3_lma: - pte =3D ptw_ldq(&pte_trans); + pte =3D ptw_ldq(&pte_trans, ra); if (!(pte & PG_PRESENT_MASK)) { goto do_fault; } @@ -239,12 +240,12 @@ static bool mmu_translate(CPUX86State *env, const Tra= nslateParams *in, * Page table level 3 */ pte_addr =3D ((in->cr3 & ~0x1f) + ((addr >> 27) & 0x18)) & a20= _mask; - if (!ptw_translate(&pte_trans, pte_addr)) { + if (!ptw_translate(&pte_trans, pte_addr, ra)) { return false; } rsvd_mask |=3D PG_HI_USER_MASK; restart_3_nolma: - pte =3D ptw_ldq(&pte_trans); + pte =3D ptw_ldq(&pte_trans, ra); if (!(pte & PG_PRESENT_MASK)) { goto do_fault; } @@ -262,11 +263,11 @@ static bool mmu_translate(CPUX86State *env, const Tra= nslateParams *in, */ pte_addr =3D ((pte & PG_ADDRESS_MASK) + (((addr >> 21) & 0x1ff) << 3)) & a20_mask; - if (!ptw_translate(&pte_trans, pte_addr)) { + if (!ptw_translate(&pte_trans, pte_addr, ra)) { return false; } restart_2_pae: - pte =3D ptw_ldq(&pte_trans); + pte =3D ptw_ldq(&pte_trans, ra); if (!(pte & PG_PRESENT_MASK)) { goto do_fault; } @@ -289,10 +290,10 @@ static bool mmu_translate(CPUX86State *env, const Tra= nslateParams *in, */ pte_addr =3D ((pte & PG_ADDRESS_MASK) + (((addr >> 12) & 0x1ff) << 3)) & a20_mask; - if (!ptw_translate(&pte_trans, pte_addr)) { + if (!ptw_translate(&pte_trans, pte_addr, ra)) { return false; } - pte =3D ptw_ldq(&pte_trans); + pte =3D ptw_ldq(&pte_trans, ra); if (!(pte & PG_PRESENT_MASK)) { goto do_fault; } @@ -307,11 +308,11 @@ static bool mmu_translate(CPUX86State *env, const Tra= nslateParams *in, * Page table level 2 */ pte_addr =3D ((in->cr3 & ~0xfff) + ((addr >> 20) & 0xffc)) & a20_m= ask; - if (!ptw_translate(&pte_trans, pte_addr)) { + if (!ptw_translate(&pte_trans, pte_addr, ra)) { return false; } restart_2_nopae: - pte =3D ptw_ldl(&pte_trans); + pte =3D ptw_ldl(&pte_trans, ra); if (!(pte & PG_PRESENT_MASK)) { goto do_fault; } @@ -336,10 +337,10 @@ static bool mmu_translate(CPUX86State *env, const Tra= nslateParams *in, * Page table level 1 */ pte_addr =3D ((pte & ~0xfffu) + ((addr >> 10) & 0xffc)) & a20_mask; - if (!ptw_translate(&pte_trans, pte_addr)) { + if (!ptw_translate(&pte_trans, pte_addr, ra)) { return false; } - pte =3D ptw_ldl(&pte_trans); + pte =3D ptw_ldl(&pte_trans, ra); if (!(pte & PG_PRESENT_MASK)) { goto do_fault; } @@ -529,7 +530,8 @@ static G_NORETURN void raise_stage2(CPUX86State *env, T= ranslateFault *err, =20 static bool get_physical_address(CPUX86State *env, vaddr addr, MMUAccessType access_type, int mmu_idx, - TranslateResult *out, TranslateFault *err) + TranslateResult *out, TranslateFault *err, + uint64_t ra) { TranslateParams in; bool use_stage2 =3D env->hflags2 & HF2_NPT_MASK; @@ -548,7 +550,7 @@ static bool get_physical_address(CPUX86State *env, vadd= r addr, in.mmu_idx =3D MMU_USER_IDX; in.ptw_idx =3D MMU_PHYS_IDX; =20 - if (!mmu_translate(env, &in, out, err)) { + if (!mmu_translate(env, &in, out, err, ra)) { err->stage2 =3D S2_GPA; return false; } @@ -575,7 +577,7 @@ static bool get_physical_address(CPUX86State *env, vadd= r addr, return false; } } - return mmu_translate(env, &in, out, err); + return mmu_translate(env, &in, out, err, ra); } break; } @@ -601,7 +603,8 @@ bool x86_cpu_tlb_fill(CPUState *cs, vaddr addr, int siz= e, TranslateResult out; TranslateFault err; =20 - if (get_physical_address(env, addr, access_type, mmu_idx, &out, &err))= { + if (get_physical_address(env, addr, access_type, mmu_idx, &out, &err, + retaddr)) { /* * Even if 4MB pages, we map only one 4KB page in the cache to * avoid filling it too fast. --=20 2.39.2