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Tsirkin" , Ani Sinha , Richard Henderson , Igor Mammedov , Mark Cave-Ayland , Laurent Vivier , Thomas Huth , Marcel Apfelbaum , Eduardo Habkost , Paolo Bonzini , BALATON Zoltan , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 01/14] MAINTAINERS: Add 'ICH9 South Bridge' section Date: Mon, 19 Feb 2024 17:38:41 +0100 Message-ID: <20240219163855.87326-2-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240219163855.87326-1-philmd@linaro.org> References: <20240219163855.87326-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=philmd@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1708360783367100003 Extract 'ICH9 South Bridge' from the 'PC' section. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- MAINTAINERS | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 7d61fb9319..1b210c5cc1 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1808,12 +1808,7 @@ F: include/hw/pci-host/i440fx.h F: include/hw/pci-host/q35.h F: include/hw/pci-host/pam.h F: hw/isa/piix.c -F: hw/isa/lpc_ich9.c -F: hw/i2c/smbus_ich9.c F: hw/acpi/piix4.c -F: hw/acpi/ich9*.c -F: include/hw/acpi/ich9*.h -F: include/hw/southbridge/ich9.h F: include/hw/southbridge/piix.h F: hw/isa/apm.c F: include/hw/isa/apm.h @@ -2606,6 +2601,16 @@ F: hw/display/edid* F: include/hw/display/edid.h F: qemu-edid.c =20 +ICH9 South Bridge (82801i) +M: Michael S. Tsirkin +M: Marcel Apfelbaum +S: Supported +F: hw/acpi/ich9*.c +F: hw/i2c/smbus_ich9.c +F: hw/isa/lpc_ich9.c +F: include/hw/acpi/ich9*.h +F: include/hw/southbridge/ich9.h + PIIX4 South Bridge (i82371AB) M: Herv=C3=A9 Poussineau M: Philippe Mathieu-Daud=C3=A9 --=20 2.41.0 From nobody Thu Nov 14 07:10:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1708360784; cv=none; d=zohomail.com; s=zohoarc; b=djlByI9J0kfgFgLnUXVR0ucyEVyVwyiJTqrDXjC5coD7xtwg+3WOIwy4lbbrKJ3c404q4nokdonqrUk8MJAXD1FeEFY5cDznsToEPQMHWr99Qjp7emtMg8OH+AVNkaRCfN0qMlIEzSHRNujo2hwbBZ53BcF+0pPKnI0AxMxlie4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1708360784; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=g4FCzhBMxBMDZoobHoXe86blnQI4iLx/WEkq5NXhKrY=; b=mzARvRqIPAmHuNAST3aReLiv5cL1uf0c4hYudvnn5MfOMw48DrV4THUeiIeGdpRK2QVshCJyIZuxYcCa5IetU5ovH0K+d5K2mrWWFIjw/MGWTS51AQi4SonC40avlmPX6HUmps6FQGFmadFwvg5a178gTfQurWzhko6PCd3LY7M= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1708360784878352.6026263542501; Mon, 19 Feb 2024 08:39:44 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rc6fv-0001SN-18; Mon, 19 Feb 2024 11:39:28 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rc6fs-0001RB-BK for qemu-devel@nongnu.org; Mon, 19 Feb 2024 11:39:24 -0500 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rc6fl-0002vv-Ve for qemu-devel@nongnu.org; Mon, 19 Feb 2024 11:39:23 -0500 Received: by mail-wr1-x42a.google.com with SMTP id ffacd0b85a97d-33d38c9ca5bso898234f8f.2 for ; Mon, 19 Feb 2024 08:39:16 -0800 (PST) Received: from m1x-phil.lan ([176.176.181.220]) by smtp.gmail.com with ESMTPSA id i13-20020a5d55cd000000b0033b198efbedsm10733258wrw.15.2024.02.19.08.39.11 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 19 Feb 2024 08:39:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1708360754; x=1708965554; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=g4FCzhBMxBMDZoobHoXe86blnQI4iLx/WEkq5NXhKrY=; b=JnyXsnuICmP5Jg8a/zmDVDVxQazwzX3Tv6u/RZpiIfm7eok2hFnOo5Q1kWJW0y6hxI TtjCSNJmnvfPNPTQqIk4UZvEkj6DqFoBM3AtIH+4e1rr2YUqbmJa5pO3HSsVEmwz107K oZZOuES1zVdRn2Gg5i9g7lHnY/GRy9i3b8Y8TFR0VDIHjbTNAAGLXydEkSqXUB2fuCUA jyAhuBskbiks4mOWPFmUA4W/8Ui/XAjhDem2eIo2YN0XZcSit0OWQT5OWcdAw8t4O6GL 30r9lZaOVSgoxicf+guv6jEOUg5Zsn0h79WzcKLjOVhZtMDuk1nTZnrIDqAQg1EsCQ+l ET/Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1708360754; x=1708965554; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=g4FCzhBMxBMDZoobHoXe86blnQI4iLx/WEkq5NXhKrY=; b=rfM8Z7Har5IB2BG3hgKwzjH6JiMgt/SEJHumyRtT3c6fwbPIuj6YhfjVk4huVtsc1v x+cVwWtH9wnD8U4BdZkfHPr0qJm2sKDItGu0kwwhq9vwsOG5pYOqaKXNvYg0gbhrdt8d gOyThxvUp9r3YMSYQmpS1prQcxwsbvdPCODxP6uo2J1lf2OebXd2ZQwtk/AhhOBrZZuN dZp7NbCPyjjXVx94GrAvYP2Q45QLINeG+xp1rXh2RoXfttDXLZTpOAOkodP2DjtXaQaL pw87ZEhMScNUo3QcnrUYAe0DoQghcUjgxapUonrN1bptRF49+vLu2T9JzJOYFT1cdsMl bCCg== X-Gm-Message-State: AOJu0YzSTU5wJ7I0mZwLWT/mCqvHxH0jgivpQS+3tCRvSsPowXFv21Pi bTLDterpUmCFIIRNIPDZtNxqoa8sT0EcD1+O1Xka98ksmy4fLM1xW6QXJHYtvjQ+vhZz2p2R5X/ M X-Google-Smtp-Source: AGHT+IFgBDkCLPS0L77lmL6b9/TMgs59h2x46S4M3Nc73nGqBRnmVDdlyQYzcd5a26zgtAyJ+Mv7qw== X-Received: by 2002:a5d:5248:0:b0:33d:36e0:b9eb with SMTP id k8-20020a5d5248000000b0033d36e0b9ebmr3278810wrc.50.1708360754075; Mon, 19 Feb 2024 08:39:14 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Bernhard Beschow Cc: "Michael S. Tsirkin" , Ani Sinha , Richard Henderson , Igor Mammedov , Mark Cave-Ayland , Laurent Vivier , Thomas Huth , Marcel Apfelbaum , Eduardo Habkost , Paolo Bonzini , BALATON Zoltan , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 02/14] hw/i386/q35: Add local 'lpc_obj' variable Date: Mon, 19 Feb 2024 17:38:42 +0100 Message-ID: <20240219163855.87326-3-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240219163855.87326-1-philmd@linaro.org> References: <20240219163855.87326-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=philmd@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1708360787207100011 Instead of casting OBJECT(lpc) multiple times, do it once in the new 'lpc_obj' variable. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/i386/pc_q35.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index a91f414922..621661a738 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -126,6 +126,7 @@ static void pc_q35_init(MachineState *machine) Object *phb; PCIBus *host_bus; PCIDevice *lpc; + Object *lpc_obj; DeviceState *lpc_dev; BusState *idebus[MAX_SATA_PORTS]; ISADevice *rtc_state; @@ -238,6 +239,7 @@ static void pc_q35_init(MachineState *machine) /* create ISA bus */ lpc =3D pci_new_multifunction(PCI_DEVFN(ICH9_LPC_DEV, ICH9_LPC_FUNC), TYPE_ICH9_LPC_DEVICE); + lpc_obj =3D OBJECT(lpc); lpc_dev =3D DEVICE(lpc); qdev_prop_set_bit(lpc_dev, "smm-enabled", x86_machine_is_smm_enabled(x86ms)); @@ -246,7 +248,7 @@ static void pc_q35_init(MachineState *machine) qdev_connect_gpio_out_named(lpc_dev, ICH9_GPIO_GSI, i, x86ms->gsi[= i]); } =20 - rtc_state =3D ISA_DEVICE(object_resolve_path_component(OBJECT(lpc), "r= tc")); + rtc_state =3D ISA_DEVICE(object_resolve_path_component(lpc_obj, "rtc")= ); =20 object_property_add_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP, TYPE_HOTPLUG_HANDLER, @@ -254,13 +256,13 @@ static void pc_q35_init(MachineState *machine) object_property_allow_set_link, OBJ_PROP_LINK_STRONG); object_property_set_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP, - OBJECT(lpc), &error_abort); + lpc_obj, &error_abort); =20 - acpi_pcihp =3D object_property_get_bool(OBJECT(lpc), + acpi_pcihp =3D object_property_get_bool(lpc_obj, ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, NULL); =20 - keep_pci_slot_hpc =3D object_property_get_bool(OBJECT(lpc), + keep_pci_slot_hpc =3D object_property_get_bool(lpc_obj, "x-keep-pci-slot-hpc", NULL); =20 --=20 2.41.0 From nobody Thu Nov 14 07:10:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Tsirkin" , Ani Sinha , Richard Henderson , Igor Mammedov , Mark Cave-Ayland , Laurent Vivier , Thomas Huth , Marcel Apfelbaum , Eduardo Habkost , Paolo Bonzini , BALATON Zoltan , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 03/14] hw/acpi/ich9: Restrict definitions from 'hw/southbridge/ich9.h' Date: Mon, 19 Feb 2024 17:38:43 +0100 Message-ID: <20240219163855.87326-4-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240219163855.87326-1-philmd@linaro.org> References: <20240219163855.87326-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=philmd@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1708360855488100009 Restrict ACPI definitions from "hw/southbridge/ich9.h" to the ACPI files where they are used. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/acpi/ich9.h | 15 +++++++++++++++ include/hw/southbridge/ich9.h | 18 ------------------ hw/acpi/ich9.c | 4 ++++ 3 files changed, 19 insertions(+), 18 deletions(-) diff --git a/include/hw/acpi/ich9.h b/include/hw/acpi/ich9.h index 215de3c91f..3587a35c9f 100644 --- a/include/hw/acpi/ich9.h +++ b/include/hw/acpi/ich9.h @@ -91,4 +91,19 @@ void ich9_pm_device_unplug_cb(HotplugHandler *hotplug_de= v, DeviceState *dev, bool ich9_pm_is_hotpluggable_bus(HotplugHandler *hotplug_dev, BusState *bu= s); =20 void ich9_pm_ospm_status(AcpiDeviceIf *adev, ACPIOSTInfoList ***list); + +#define ICH9_PMIO_PM1_STS 0x00 +#define ICH9_PMIO_PM1_EN 0x02 +#define ICH9_PMIO_PM1_CNT 0x04 +#define ICH9_PMIO_PM1_TMR 0x08 +#define ICH9_PMIO_GPE0_STS 0x20 +#define ICH9_PMIO_GPE0_EN 0x28 +#define ICH9_PMIO_GPE0_LEN 16 +#define ICH9_PMIO_SMI_EN 0x30 +#define ICH9_PMIO_SMI_EN_APMC_EN (1 << 5) +#define ICH9_PMIO_SMI_EN_TCO_EN (1 << 13) +#define ICH9_PMIO_SMI_STS 0x34 +#define ICH9_PMIO_TCO_RLD 0x60 +#define ICH9_PMIO_TCO_LEN 32 + #endif /* HW_ACPI_ICH9_H */ diff --git a/include/hw/southbridge/ich9.h b/include/hw/southbridge/ich9.h index fd01649d04..1ac4238f7e 100644 --- a/include/hw/southbridge/ich9.h +++ b/include/hw/southbridge/ich9.h @@ -183,24 +183,6 @@ struct ICH9LPCState { /* D31:F0 power management I/O registers offset from the address ICH9_LPC_PMBASE */ =20 -/* ICH9 LPC PM I/O registers are 128 ports and 128-aligned */ -#define ICH9_PMIO_SIZE 128 -#define ICH9_PMIO_MASK (ICH9_PMIO_SIZE - 1) - -#define ICH9_PMIO_PM1_STS 0x00 -#define ICH9_PMIO_PM1_EN 0x02 -#define ICH9_PMIO_PM1_CNT 0x04 -#define ICH9_PMIO_PM1_TMR 0x08 -#define ICH9_PMIO_GPE0_STS 0x20 -#define ICH9_PMIO_GPE0_EN 0x28 -#define ICH9_PMIO_GPE0_LEN 16 -#define ICH9_PMIO_SMI_EN 0x30 -#define ICH9_PMIO_SMI_EN_APMC_EN (1 << 5) -#define ICH9_PMIO_SMI_EN_TCO_EN (1 << 13) -#define ICH9_PMIO_SMI_STS 0x34 -#define ICH9_PMIO_TCO_RLD 0x60 -#define ICH9_PMIO_TCO_LEN 32 - /* FADT ACPI_ENABLE/ACPI_DISABLE */ #define ICH9_APM_ACPI_ENABLE 0x2 #define ICH9_APM_ACPI_DISABLE 0x3 diff --git a/hw/acpi/ich9.c b/hw/acpi/ich9.c index be375a8b9d..228ebc9a1e 100644 --- a/hw/acpi/ich9.c +++ b/hw/acpi/ich9.c @@ -49,6 +49,10 @@ do { printf("%s "fmt, __func__, ## __VA_ARGS__); } while= (0) #define ICH9_DEBUG(fmt, ...) do { } while (0) #endif =20 +/* ICH9 LPC PM I/O registers are 128 ports and 128-aligned */ +#define ICH9_PMIO_SIZE 128 +#define ICH9_PMIO_MASK (ICH9_PMIO_SIZE - 1) + static void ich9_pm_update_sci_fn(ACPIREGS *regs) { ICH9LPCPMRegs *pm =3D container_of(regs, ICH9LPCPMRegs, acpi_regs); --=20 2.41.0 From nobody Thu Nov 14 07:10:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1708360806; cv=none; d=zohomail.com; s=zohoarc; b=N7UzBgGkwosokqKf3mMjuA0Wkf5EKr4hiro4TVMQuZ84lUWGIgCI6A9+YGMQUzbyOeNwG/Hr2LIyyr9mdbZLaUjhblLz3AjUIhmPsKQw+7ndJD8r8n3YOITsmsItcpaV64x0Ai/w7exq+nmKUDkKXLNFfTb3yXWvGVcEo4yf2+0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; 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Mon, 19 Feb 2024 08:39:27 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Bernhard Beschow Cc: "Michael S. Tsirkin" , Ani Sinha , Richard Henderson , Igor Mammedov , Mark Cave-Ayland , Laurent Vivier , Thomas Huth , Marcel Apfelbaum , Eduardo Habkost , Paolo Bonzini , BALATON Zoltan , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 04/14] hw/acpi/ich9_tco: Include 'ich9' in names Date: Mon, 19 Feb 2024 17:38:44 +0100 Message-ID: <20240219163855.87326-5-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240219163855.87326-1-philmd@linaro.org> References: <20240219163855.87326-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=philmd@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1708360807259100001 Make it explicit the following are ICH9 specific: acpi_pm_tco_init() -> ich9_acpi_pm_tco_init() vmstate_tco_io_sts -> vmstate_ich9_sm_tco. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/acpi/ich9_tco.h | 5 ++--- hw/acpi/ich9.c | 4 ++-- hw/acpi/ich9_tco.c | 4 ++-- 3 files changed, 6 insertions(+), 7 deletions(-) diff --git a/include/hw/acpi/ich9_tco.h b/include/hw/acpi/ich9_tco.h index 2562a7cf39..1c99781a79 100644 --- a/include/hw/acpi/ich9_tco.h +++ b/include/hw/acpi/ich9_tco.h @@ -75,9 +75,8 @@ typedef struct TCOIORegs { MemoryRegion io; } TCOIORegs; =20 -/* tco.c */ -void acpi_pm_tco_init(TCOIORegs *tr, MemoryRegion *parent); +void ich9_acpi_pm_tco_init(TCOIORegs *tr, MemoryRegion *parent); =20 -extern const VMStateDescription vmstate_tco_io_sts; +extern const VMStateDescription vmstate_ich9_sm_tco; =20 #endif /* HW_ACPI_TCO_H */ diff --git a/hw/acpi/ich9.c b/hw/acpi/ich9.c index 228ebc9a1e..660fa6a082 100644 --- a/hw/acpi/ich9.c +++ b/hw/acpi/ich9.c @@ -186,7 +186,7 @@ static const VMStateDescription vmstate_tco_io_state = =3D { .minimum_version_id =3D 1, .needed =3D vmstate_test_use_tco, .fields =3D (const VMStateField[]) { - VMSTATE_STRUCT(tco_regs, ICH9LPCPMRegs, 1, vmstate_tco_io_sts, + VMSTATE_STRUCT(tco_regs, ICH9LPCPMRegs, 1, vmstate_ich9_sm_tco, TCOIORegs), VMSTATE_END_OF_LIST() } @@ -317,7 +317,7 @@ void ich9_pm_init(PCIDevice *lpc_pci, ICH9LPCPMRegs *pm= , qemu_irq sci_irq) memory_region_add_subregion(&pm->io, ICH9_PMIO_SMI_EN, &pm->io_smi); =20 if (pm->enable_tco) { - acpi_pm_tco_init(&pm->tco_regs, &pm->io); + ich9_acpi_pm_tco_init(&pm->tco_regs, &pm->io); } =20 if (pm->acpi_pci_hotplug.use_acpi_hotplug_bridge) { diff --git a/hw/acpi/ich9_tco.c b/hw/acpi/ich9_tco.c index 81606219f7..dd4aff82e0 100644 --- a/hw/acpi/ich9_tco.c +++ b/hw/acpi/ich9_tco.c @@ -224,7 +224,7 @@ static const MemoryRegionOps tco_io_ops =3D { .endianness =3D DEVICE_LITTLE_ENDIAN, }; =20 -void acpi_pm_tco_init(TCOIORegs *tr, MemoryRegion *parent) +void ich9_acpi_pm_tco_init(TCOIORegs *tr, MemoryRegion *parent) { *tr =3D (TCOIORegs) { .tco =3D { @@ -250,7 +250,7 @@ void acpi_pm_tco_init(TCOIORegs *tr, MemoryRegion *pare= nt) memory_region_add_subregion(parent, ICH9_PMIO_TCO_RLD, &tr->io); } =20 -const VMStateDescription vmstate_tco_io_sts =3D { +const VMStateDescription vmstate_ich9_sm_tco =3D { .name =3D "tco io device status", .version_id =3D 1, .minimum_version_id =3D 1, --=20 2.41.0 From nobody Thu Nov 14 07:10:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 19 Feb 2024 08:39:34 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Bernhard Beschow Cc: "Michael S. Tsirkin" , Ani Sinha , Richard Henderson , Igor Mammedov , Mark Cave-Ayland , Laurent Vivier , Thomas Huth , Marcel Apfelbaum , Eduardo Habkost , Paolo Bonzini , BALATON Zoltan , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 05/14] hw/acpi/ich9_tco: Restrict ich9_generate_smi() declaration Date: Mon, 19 Feb 2024 17:38:45 +0100 Message-ID: <20240219163855.87326-6-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240219163855.87326-1-philmd@linaro.org> References: <20240219163855.87326-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=philmd@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1708360825417100005 Only files including "hw/acpi/ich9_tco.h" require the ich9_generate_smi() declaration. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/acpi/ich9_tco.h | 1 + include/hw/southbridge/ich9.h | 2 -- 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/include/hw/acpi/ich9_tco.h b/include/hw/acpi/ich9_tco.h index 1c99781a79..68ee64942f 100644 --- a/include/hw/acpi/ich9_tco.h +++ b/include/hw/acpi/ich9_tco.h @@ -76,6 +76,7 @@ typedef struct TCOIORegs { } TCOIORegs; =20 void ich9_acpi_pm_tco_init(TCOIORegs *tr, MemoryRegion *parent); +void ich9_generate_smi(void); =20 extern const VMStateDescription vmstate_ich9_sm_tco; =20 diff --git a/include/hw/southbridge/ich9.h b/include/hw/southbridge/ich9.h index 1ac4238f7e..bee522a4cf 100644 --- a/include/hw/southbridge/ich9.h +++ b/include/hw/southbridge/ich9.h @@ -11,8 +11,6 @@ #include "qemu/notify.h" #include "qom/object.h" =20 -void ich9_generate_smi(void); - #define ICH9_CC_SIZE (16 * 1024) /* 16KB. Chipset configuration registers = */ =20 #define TYPE_ICH9_LPC_DEVICE "ICH9-LPC" --=20 2.41.0 From nobody Thu Nov 14 07:10:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1708360813; cv=none; d=zohomail.com; s=zohoarc; b=CbcAi8bcu2i0YxJcN5blwrngBiRwE4IR/wOI7ln6OzwTyV+9vLgURYOLybxpG4YBiRuf6e1GMyPWv4RmI6qG8VtMni7HgZoIz4yuRp49bbAMiapKc8mMto537fuVrlOv7s9Y5Z+cIy90aWX5J6KZkhjIThFEQpC0rY11SSHZcIM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1708360813; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=eHqLJIf48lUklPD2bsMO5k3sbW9zd3TEK1XtTCythow=; b=Exm3iG36KscAwy6z6vxd6JdclW/7XKXICJeR/NOR5Yiil9ARETedqeaRQDiOc1hgrJjuwrYKDQDgXjxHQ54LMgk6YsFqNk8+kbBY3i8XpFN6eGIY+293kzXO0a6Ca3FoBbo1KA0hDNyQ+bdJTkIdIrMMXBeltZpQncJAAkJ20o0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1708360813795774.9003682968957; Mon, 19 Feb 2024 08:40:13 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rc6gF-00020n-77; Mon, 19 Feb 2024 11:39:47 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rc6gD-0001vH-2f for qemu-devel@nongnu.org; Mon, 19 Feb 2024 11:39:45 -0500 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rc6gB-0002yn-8I for qemu-devel@nongnu.org; Mon, 19 Feb 2024 11:39:44 -0500 Received: by mail-wm1-x333.google.com with SMTP id 5b1f17b1804b1-41261233e61so8607315e9.0 for ; Mon, 19 Feb 2024 08:39:42 -0800 (PST) Received: from m1x-phil.lan ([176.176.181.220]) by smtp.gmail.com with ESMTPSA id 21-20020a05600c229500b0041228b2e179sm11715550wmf.39.2024.02.19.08.39.39 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 19 Feb 2024 08:39:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1708360781; x=1708965581; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=eHqLJIf48lUklPD2bsMO5k3sbW9zd3TEK1XtTCythow=; b=vbwXM9vaKtADKSqj1B4rhNH9Qtpu+Wc2qlY/gRERD7lATZ0+aR8VQLO8CYVh6+HCzI VWo07vohP2vbRpqJTrSoEviaGxHKgFHq1exot130ANqNuUAAdb4qsQS8wd09mrgL2AeX Z+t3cYGg43izAg2VBfpEBiOLqQYxORNLWxL0r7XPKfAV6FjfaUhTrXhbQYIlb5e6sW4k +k/lbodmq26Ug/ksEg9rdFT0A2r7YgFLnuYrCuWbZ5+NIfrsmBaxF48R88X5MPhLX5lh F87WGRQBRVRvQmlLoW2KuOKSqa25FtjlKUluCS4iWolVYr4htreRJo2ywDhFT1DkMqd0 1LkA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1708360781; x=1708965581; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=eHqLJIf48lUklPD2bsMO5k3sbW9zd3TEK1XtTCythow=; b=xSwkQify3752lJlU0hJYzZlqIGU1bvEds0fqbfvH3jKouVhZ51iOeOvmaQAmkyXtdN OZo603RuBUeLYadIiwxBMF+lw7CKurNLWids57M7RU6et7+P6kCn9bRagzeSM7TdUgCL 0TZDgNARgujIwJrnbSEOZGPUhoEBiadRgpjdkDxfD1d5V2HleV0u016orUdwiiDV2PSL nQfYzQW84b/wC6/1aQkhQGZAG93rppQThenT8IEtZ77cC+3m8cdezGAHMzgPA9nV0XSg 9L+keM56XgcLEW5JFYyIf/iDK2Ze+KS3owePiGR5fy//4BwyLFytNjLpJVDr2HipFp4L b6qQ== X-Gm-Message-State: AOJu0YyysRPbXP2PWs427iL4628m4zEHjddFj49YFKz58dbE9y7j2Fvb SaiUK2viqFTWAbS+gfgC+aiQsNXJWMbHlqiLJYclAh1vFRXUaCli7NFx4OR531v11lrsUCsK5Mq Y X-Google-Smtp-Source: AGHT+IEJsakYa9P4Z0qhYdzvRgFxhjP7w89K7jZtJe7VQdQ+dsVrHm+CkgwcNlnMscvuIHMsKpx9OA== X-Received: by 2002:a05:600c:518e:b0:412:6c73:a63e with SMTP id fa14-20020a05600c518e00b004126c73a63emr484118wmb.0.1708360781284; Mon, 19 Feb 2024 08:39:41 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Bernhard Beschow Cc: "Michael S. Tsirkin" , Ani Sinha , Richard Henderson , Igor Mammedov , Mark Cave-Ayland , Laurent Vivier , Thomas Huth , Marcel Apfelbaum , Eduardo Habkost , Paolo Bonzini , BALATON Zoltan , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 06/14] hw/pci-bridge: Extract QOM ICH definitions to 'ich_dmi_pci.h' Date: Mon, 19 Feb 2024 17:38:46 +0100 Message-ID: <20240219163855.87326-7-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240219163855.87326-1-philmd@linaro.org> References: <20240219163855.87326-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=philmd@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1708360815341100003 Expose TYPE_ICH_DMI_PCI_BRIDGE to the new "hw/pci-bridge/ich_dmi_pci.h" header. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- MAINTAINERS | 1 + include/hw/pci-bridge/ich_dmi_pci.h | 20 ++++++++++++++++++++ include/hw/southbridge/ich9.h | 2 -- hw/pci-bridge/i82801b11.c | 11 ++++------- 4 files changed, 25 insertions(+), 9 deletions(-) create mode 100644 include/hw/pci-bridge/ich_dmi_pci.h diff --git a/MAINTAINERS b/MAINTAINERS index 1b210c5cc1..50507c3dd6 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2609,6 +2609,7 @@ F: hw/acpi/ich9*.c F: hw/i2c/smbus_ich9.c F: hw/isa/lpc_ich9.c F: include/hw/acpi/ich9*.h +F: include/hw/pci-bridge/ich_dmi_pci.h F: include/hw/southbridge/ich9.h =20 PIIX4 South Bridge (i82371AB) diff --git a/include/hw/pci-bridge/ich_dmi_pci.h b/include/hw/pci-bridge/ic= h_dmi_pci.h new file mode 100644 index 0000000000..7623b32b8e --- /dev/null +++ b/include/hw/pci-bridge/ich_dmi_pci.h @@ -0,0 +1,20 @@ +/* + * QEMU ICH4 i82801b11 dmi-to-pci Bridge Emulation + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef HW_PCI_BRIDGE_ICH_D2P_H +#define HW_PCI_BRIDGE_ICH_D2P_H + +#include "qom/object.h" +#include "hw/pci/pci_bridge.h" + +#define TYPE_ICH_DMI_PCI_BRIDGE "i82801b11-bridge" +OBJECT_DECLARE_SIMPLE_TYPE(I82801b11Bridge, ICH_DMI_PCI_BRIDGE) + +struct I82801b11Bridge { + PCIBridge parent_obj; +}; + +#endif diff --git a/include/hw/southbridge/ich9.h b/include/hw/southbridge/ich9.h index bee522a4cf..b2abf483e0 100644 --- a/include/hw/southbridge/ich9.h +++ b/include/hw/southbridge/ich9.h @@ -114,8 +114,6 @@ struct ICH9LPCState { =20 #define ICH9_D2P_SECONDARY_DEFAULT (256 - 8) =20 -#define ICH9_D2P_A2_REVISION 0x92 - /* D31:F0 LPC Processor Interface */ #define ICH9_RST_CNT_IOPORT 0xCF9 =20 diff --git a/hw/pci-bridge/i82801b11.c b/hw/pci-bridge/i82801b11.c index c140919cbc..dd17e35b0a 100644 --- a/hw/pci-bridge/i82801b11.c +++ b/hw/pci-bridge/i82801b11.c @@ -45,7 +45,7 @@ #include "hw/pci/pci_bridge.h" #include "migration/vmstate.h" #include "qemu/module.h" -#include "hw/southbridge/ich9.h" +#include "hw/pci-bridge/ich_dmi_pci.h" =20 /*************************************************************************= ****/ /* ICH9 DMI-to-PCI bridge */ @@ -53,11 +53,8 @@ #define I82801ba_SSVID_SVID 0 #define I82801ba_SSVID_SSID 0 =20 -typedef struct I82801b11Bridge { - /*< private >*/ - PCIBridge parent_obj; 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Mon, 19 Feb 2024 08:39:48 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Bernhard Beschow Cc: "Michael S. Tsirkin" , Ani Sinha , Richard Henderson , Igor Mammedov , Mark Cave-Ayland , Laurent Vivier , Thomas Huth , Marcel Apfelbaum , Eduardo Habkost , Paolo Bonzini , BALATON Zoltan , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 07/14] hw/southbridge/ich9: Introduce TYPE_ICH9_SOUTHBRIDGE stub Date: Mon, 19 Feb 2024 17:38:47 +0100 Message-ID: <20240219163855.87326-8-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240219163855.87326-1-philmd@linaro.org> References: <20240219163855.87326-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=philmd@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1708360869535100004 Start the TYPE_ICH9_SOUTHBRIDGE stub, a kind of QOM container which will contain all the ICH9 parts. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- MAINTAINERS | 1 + include/hw/southbridge/ich9.h | 3 ++ hw/i386/pc_q35.c | 7 ++++ hw/southbridge/ich9.c | 61 +++++++++++++++++++++++++++++++++++ hw/Kconfig | 1 + hw/i386/Kconfig | 1 + hw/meson.build | 1 + hw/southbridge/Kconfig | 5 +++ hw/southbridge/meson.build | 3 ++ 9 files changed, 83 insertions(+) create mode 100644 hw/southbridge/ich9.c create mode 100644 hw/southbridge/Kconfig create mode 100644 hw/southbridge/meson.build diff --git a/MAINTAINERS b/MAINTAINERS index 50507c3dd6..d1a2eddd4c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2608,6 +2608,7 @@ S: Supported F: hw/acpi/ich9*.c F: hw/i2c/smbus_ich9.c F: hw/isa/lpc_ich9.c +F: hw/southbridge/ich9.c F: include/hw/acpi/ich9*.h F: include/hw/pci-bridge/ich_dmi_pci.h F: include/hw/southbridge/ich9.h diff --git a/include/hw/southbridge/ich9.h b/include/hw/southbridge/ich9.h index b2abf483e0..162ae3baa1 100644 --- a/include/hw/southbridge/ich9.h +++ b/include/hw/southbridge/ich9.h @@ -11,6 +11,9 @@ #include "qemu/notify.h" #include "qom/object.h" =20 +#define TYPE_ICH9_SOUTHBRIDGE "ICH9-southbridge" +OBJECT_DECLARE_SIMPLE_TYPE(ICH9State, ICH9_SOUTHBRIDGE) + #define ICH9_CC_SIZE (16 * 1024) /* 16KB. Chipset configuration registers = */ =20 #define TYPE_ICH9_LPC_DEVICE "ICH9-LPC" diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index 621661a738..311ac2be6f 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -125,6 +125,7 @@ static void pc_q35_init(MachineState *machine) X86MachineState *x86ms =3D X86_MACHINE(machine); Object *phb; PCIBus *host_bus; + DeviceState *ich9; PCIDevice *lpc; Object *lpc_obj; DeviceState *lpc_dev; @@ -233,6 +234,12 @@ static void pc_q35_init(MachineState *machine) host_bus =3D PCI_BUS(qdev_get_child_bus(DEVICE(phb), "pcie.0")); pcms->bus =3D host_bus; =20 + ich9 =3D qdev_new(TYPE_ICH9_SOUTHBRIDGE); + object_property_add_child(OBJECT(machine), "ich9", OBJECT(ich9)); + object_property_set_link(OBJECT(ich9), "mch-pcie-bus", + OBJECT(host_bus), &error_abort); + qdev_realize_and_unref(ich9, NULL, &error_fatal); + /* irq lines */ gsi_state =3D pc_gsi_create(&x86ms->gsi, true); =20 diff --git a/hw/southbridge/ich9.c b/hw/southbridge/ich9.c new file mode 100644 index 0000000000..f3a9b932ab --- /dev/null +++ b/hw/southbridge/ich9.c @@ -0,0 +1,61 @@ +/* + * QEMU Intel ICH9 south bridge emulation + * + * SPDX-FileCopyrightText: 2024 Linaro Ltd + * SPDX-FileContributor: Philippe Mathieu-Daud=C3=A9 + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "hw/qdev-properties.h" +#include "hw/southbridge/ich9.h" +#include "hw/pci/pci.h" + +struct ICH9State { + DeviceState parent_obj; + + PCIBus *pci_bus; +}; + +static Property ich9_props[] =3D { + DEFINE_PROP_LINK("mch-pcie-bus", ICH9State, pci_bus, + TYPE_PCIE_BUS, PCIBus *), + DEFINE_PROP_END_OF_LIST(), +}; + +static void ich9_init(Object *obj) +{ +} + +static void ich9_realize(DeviceState *dev, Error **errp) +{ + ICH9State *s =3D ICH9_SOUTHBRIDGE(dev); + + if (!s->pci_bus) { + error_setg(errp, "'pcie-bus' property must be set"); + return; + } +} + +static void ich9_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->realize =3D ich9_realize; + device_class_set_props(dc, ich9_props); + set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); +} + +static const TypeInfo ich9_types[] =3D { + { + .name =3D TYPE_ICH9_SOUTHBRIDGE, + .parent =3D TYPE_DEVICE, + .instance_size =3D sizeof(ICH9State), + .instance_init =3D ich9_init, + .class_init =3D ich9_class_init, + } +}; + +DEFINE_TYPES(ich9_types) diff --git a/hw/Kconfig b/hw/Kconfig index 2c00936c28..6584f2f72a 100644 --- a/hw/Kconfig +++ b/hw/Kconfig @@ -36,6 +36,7 @@ source scsi/Kconfig source sd/Kconfig source sensor/Kconfig source smbios/Kconfig +source southbridge/Kconfig source ssi/Kconfig source timer/Kconfig source tpm/Kconfig diff --git a/hw/i386/Kconfig b/hw/i386/Kconfig index a1846be6f7..d21638f4f9 100644 --- a/hw/i386/Kconfig +++ b/hw/i386/Kconfig @@ -99,6 +99,7 @@ config Q35 select PC_PCI select PC_ACPI select PCI_EXPRESS_Q35 + select ICH9 select LPC_ICH9 select AHCI_ICH9 select DIMM diff --git a/hw/meson.build b/hw/meson.build index 463d702683..7f9ae8659a 100644 --- a/hw/meson.build +++ b/hw/meson.build @@ -33,6 +33,7 @@ subdir('rtc') subdir('scsi') subdir('sd') subdir('sensor') +subdir('southbridge') subdir('smbios') subdir('ssi') subdir('timer') diff --git a/hw/southbridge/Kconfig b/hw/southbridge/Kconfig new file mode 100644 index 0000000000..852b7f346f --- /dev/null +++ b/hw/southbridge/Kconfig @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +config ICH9 + bool + depends on PCI_EXPRESS diff --git a/hw/southbridge/meson.build b/hw/southbridge/meson.build new file mode 100644 index 0000000000..70c1fa3cb2 --- /dev/null +++ b/hw/southbridge/meson.build @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +system_ss.add(when: 'CONFIG_ICH9', if_true: files('ich9.c')) --=20 2.41.0 From nobody Thu Nov 14 07:10:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 19 Feb 2024 08:39:55 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Bernhard Beschow Cc: "Michael S. Tsirkin" , Ani Sinha , Richard Henderson , Igor Mammedov , Mark Cave-Ayland , Laurent Vivier , Thomas Huth , Marcel Apfelbaum , Eduardo Habkost , Paolo Bonzini , BALATON Zoltan , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 08/14] hw/southbridge/ich9: Add the DMI-to-PCI bridge Date: Mon, 19 Feb 2024 17:38:48 +0100 Message-ID: <20240219163855.87326-9-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240219163855.87326-1-philmd@linaro.org> References: <20240219163855.87326-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=philmd@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1708360851497100003 Instantiate TYPE_ICH_DMI_PCI_BRIDGE in TYPE_ICH9_SOUTHBRIDGE. Since the Q35 machine doesn't use it, add the 'd2p-enabled' property to disable it. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/southbridge/ich9.h | 9 --------- hw/i386/pc_q35.c | 1 + hw/southbridge/ich9.c | 27 +++++++++++++++++++++++++++ hw/southbridge/Kconfig | 1 + 4 files changed, 29 insertions(+), 9 deletions(-) diff --git a/include/hw/southbridge/ich9.h b/include/hw/southbridge/ich9.h index 162ae3baa1..b9122d299d 100644 --- a/include/hw/southbridge/ich9.h +++ b/include/hw/southbridge/ich9.h @@ -108,15 +108,6 @@ struct ICH9LPCState { #define ICH9_USB_UHCI1_DEV 29 #define ICH9_USB_UHCI1_FUNC 0 =20 -/* D30:F0 DMI-to-PCI bridge */ -#define ICH9_D2P_BRIDGE "ICH9 D2P BRIDGE" -#define ICH9_D2P_BRIDGE_SAVEVM_VERSION 0 - -#define ICH9_D2P_BRIDGE_DEV 30 -#define ICH9_D2P_BRIDGE_FUNC 0 - -#define ICH9_D2P_SECONDARY_DEFAULT (256 - 8) - /* D31:F0 LPC Processor Interface */ #define ICH9_RST_CNT_IOPORT 0xCF9 =20 diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index 311ac2be6f..2f15af540f 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -238,6 +238,7 @@ static void pc_q35_init(MachineState *machine) object_property_add_child(OBJECT(machine), "ich9", OBJECT(ich9)); object_property_set_link(OBJECT(ich9), "mch-pcie-bus", OBJECT(host_bus), &error_abort); + qdev_prop_set_bit(ich9, "d2p-enabled", false); qdev_realize_and_unref(ich9, NULL, &error_fatal); =20 /* irq lines */ diff --git a/hw/southbridge/ich9.c b/hw/southbridge/ich9.c index f3a9b932ab..6df47e81fb 100644 --- a/hw/southbridge/ich9.c +++ b/hw/southbridge/ich9.c @@ -12,19 +12,42 @@ #include "hw/qdev-properties.h" #include "hw/southbridge/ich9.h" #include "hw/pci/pci.h" +#include "hw/pci-bridge/ich_dmi_pci.h" + +#define ICH9_D2P_DEVFN PCI_DEVFN(30, 0) =20 struct ICH9State { DeviceState parent_obj; =20 + I82801b11Bridge d2p; + PCIBus *pci_bus; + bool d2p_enabled; }; =20 static Property ich9_props[] =3D { DEFINE_PROP_LINK("mch-pcie-bus", ICH9State, pci_bus, TYPE_PCIE_BUS, PCIBus *), + DEFINE_PROP_BOOL("d2p-enabled", ICH9State, d2p_enabled, true), DEFINE_PROP_END_OF_LIST(), }; =20 +static bool ich9_realize_d2p(ICH9State *s, Error **errp) +{ + if (!module_object_class_by_name(TYPE_ICH_DMI_PCI_BRIDGE)) { + error_setg(errp, "DMI-to-PCI function not available in this build"= ); + return false; + } + object_initialize_child(OBJECT(s), "d2p", &s->d2p, TYPE_ICH_DMI_PCI_BR= IDGE); + qdev_prop_set_int32(DEVICE(&s->d2p), "addr", ICH9_D2P_DEVFN); + if (!qdev_realize(DEVICE(&s->d2p), BUS(s->pci_bus), errp)) { + return false; + } + object_property_add_alias(OBJECT(s), "pci.0", OBJECT(&s->d2p), "pci.0"= ); + + return true; +} + static void ich9_init(Object *obj) { } @@ -37,6 +60,10 @@ static void ich9_realize(DeviceState *dev, Error **errp) error_setg(errp, "'pcie-bus' property must be set"); return; } + + if (s->d2p_enabled && !ich9_realize_d2p(s, errp)) { + return; + } } =20 static void ich9_class_init(ObjectClass *klass, void *data) diff --git a/hw/southbridge/Kconfig b/hw/southbridge/Kconfig index 852b7f346f..db7259bf6f 100644 --- a/hw/southbridge/Kconfig +++ b/hw/southbridge/Kconfig @@ -3,3 +3,4 @@ config ICH9 bool depends on PCI_EXPRESS + imply I82801B11 --=20 2.41.0 From nobody Thu Nov 14 07:10:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 19 Feb 2024 08:40:02 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Bernhard Beschow Cc: "Michael S. Tsirkin" , Ani Sinha , Richard Henderson , Igor Mammedov , Mark Cave-Ayland , Laurent Vivier , Thomas Huth , Marcel Apfelbaum , Eduardo Habkost , Paolo Bonzini , BALATON Zoltan , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 09/14] hw/southbridge/ich9: Add a AHCI function Date: Mon, 19 Feb 2024 17:38:49 +0100 Message-ID: <20240219163855.87326-10-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240219163855.87326-1-philmd@linaro.org> References: <20240219163855.87326-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=philmd@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1708360823403100003 Instantiate TYPE_ICH9_AHCI in TYPE_ICH9_SOUTHBRIDGE. Since the PC machines can disable SATA (see the PC_MACHINE_SATA dynamic property), add the 'sata-enabled' property to disable it. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- MAINTAINERS | 2 ++ include/hw/southbridge/ich9.h | 4 ---- hw/i386/pc_q35.c | 25 ++++--------------------- hw/southbridge/ich9.c | 35 +++++++++++++++++++++++++++++++++++ hw/i386/Kconfig | 1 - hw/southbridge/Kconfig | 1 + 6 files changed, 42 insertions(+), 26 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index d1a2eddd4c..937ebb5c96 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2607,9 +2607,11 @@ M: Marcel Apfelbaum S: Supported F: hw/acpi/ich9*.c F: hw/i2c/smbus_ich9.c +F: hw/ide/ich.c F: hw/isa/lpc_ich9.c F: hw/southbridge/ich9.c F: include/hw/acpi/ich9*.h +F: include/hw/ide/ahci-pci.h F: include/hw/pci-bridge/ich_dmi_pci.h F: include/hw/southbridge/ich9.h =20 diff --git a/include/hw/southbridge/ich9.h b/include/hw/southbridge/ich9.h index b9122d299d..ac7f9f4ff5 100644 --- a/include/hw/southbridge/ich9.h +++ b/include/hw/southbridge/ich9.h @@ -166,10 +166,6 @@ struct ICH9LPCState { =20 #define ICH9_GPIO_GSI "gsi" =20 -/* D31:F2 SATA Controller #1 */ -#define ICH9_SATA1_DEV 31 -#define ICH9_SATA1_FUNC 2 - /* D31:F0 power management I/O registers offset from the address ICH9_LPC_PMBASE */ =20 diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index 2f15af540f..060358d449 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -61,9 +61,6 @@ #include "hw/acpi/acpi.h" #include "target/i386/cpu.h" =20 -/* ICH9 AHCI has 6 ports */ -#define MAX_SATA_PORTS 6 - struct ehci_companions { const char *name; int func; @@ -129,7 +126,7 @@ static void pc_q35_init(MachineState *machine) PCIDevice *lpc; Object *lpc_obj; DeviceState *lpc_dev; - BusState *idebus[MAX_SATA_PORTS]; + BusState *idebus[2] =3D { }; ISADevice *rtc_state; MemoryRegion *system_memory =3D get_system_memory(); MemoryRegion *system_io =3D get_system_io(); @@ -138,7 +135,6 @@ static void pc_q35_init(MachineState *machine) ISABus *isa_bus; int i; ram_addr_t lowmem; - DriveInfo *hd[MAX_SATA_PORTS]; MachineClass *mc =3D MACHINE_GET_CLASS(machine); bool acpi_pcihp; bool keep_pci_slot_hpc; @@ -239,6 +235,7 @@ static void pc_q35_init(MachineState *machine) object_property_set_link(OBJECT(ich9), "mch-pcie-bus", OBJECT(host_bus), &error_abort); qdev_prop_set_bit(ich9, "d2p-enabled", false); + qdev_prop_set_bit(ich9, "sata-enabled", pcms->sata_enabled); qdev_realize_and_unref(ich9, NULL, &error_fatal); =20 /* irq lines */ @@ -302,22 +299,8 @@ static void pc_q35_init(MachineState *machine) 0xff0104); =20 if (pcms->sata_enabled) { - PCIDevice *pdev; - AHCIPCIState *ich9; - - /* ahci and SATA device, for q35 1 ahci controller is built-in */ - pdev =3D pci_create_simple_multifunction(host_bus, - PCI_DEVFN(ICH9_SATA1_DEV, - ICH9_SATA1_FUNC), - "ich9-ahci"); - ich9 =3D ICH9_AHCI(pdev); - idebus[0] =3D qdev_get_child_bus(DEVICE(pdev), "ide.0"); - idebus[1] =3D qdev_get_child_bus(DEVICE(pdev), "ide.1"); - g_assert(MAX_SATA_PORTS =3D=3D ich9->ahci.ports); - ide_drive_get(hd, ich9->ahci.ports); - ahci_ide_create_devs(&ich9->ahci, hd); - } else { - idebus[0] =3D idebus[1] =3D NULL; + idebus[0] =3D qdev_get_child_bus(ich9, "ide.0"); + idebus[1] =3D qdev_get_child_bus(ich9, "ide.1"); } =20 if (machine_usb(machine)) { diff --git a/hw/southbridge/ich9.c b/hw/southbridge/ich9.c index 6df47e81fb..233dc1c5d7 100644 --- a/hw/southbridge/ich9.c +++ b/hw/southbridge/ich9.c @@ -13,22 +13,30 @@ #include "hw/southbridge/ich9.h" #include "hw/pci/pci.h" #include "hw/pci-bridge/ich_dmi_pci.h" +#include "hw/ide/ahci-pci.h" +#include "hw/ide.h" =20 #define ICH9_D2P_DEVFN PCI_DEVFN(30, 0) +#define ICH9_SATA1_DEVFN PCI_DEVFN(31, 2) + +#define SATA_PORTS 6 =20 struct ICH9State { DeviceState parent_obj; =20 I82801b11Bridge d2p; + AHCIPCIState sata0; =20 PCIBus *pci_bus; bool d2p_enabled; + bool sata_enabled; }; =20 static Property ich9_props[] =3D { DEFINE_PROP_LINK("mch-pcie-bus", ICH9State, pci_bus, TYPE_PCIE_BUS, PCIBus *), DEFINE_PROP_BOOL("d2p-enabled", ICH9State, d2p_enabled, true), + DEFINE_PROP_BOOL("sata-enabled", ICH9State, sata_enabled, true), DEFINE_PROP_END_OF_LIST(), }; =20 @@ -48,6 +56,29 @@ static bool ich9_realize_d2p(ICH9State *s, Error **errp) return true; } =20 +static bool ich9_realize_sata(ICH9State *s, Error **errp) +{ + DriveInfo *hd[SATA_PORTS]; + + object_initialize_child(OBJECT(s), "sata[0]", &s->sata0, TYPE_ICH9_AHC= I); + qdev_prop_set_int32(DEVICE(&s->sata0), "addr", ICH9_SATA1_DEVFN); + if (!qdev_realize(DEVICE(&s->sata0), BUS(s->pci_bus), errp)) { + return false; + } + for (unsigned i =3D 0; i < SATA_PORTS; i++) { + g_autofree char *portname =3D g_strdup_printf("ide.%u", i); + + object_property_add_alias(OBJECT(s), portname, + OBJECT(&s->sata0), portname); + } + + g_assert(SATA_PORTS =3D=3D s->sata0.ahci.ports); + ide_drive_get(hd, s->sata0.ahci.ports); + ahci_ide_create_devs(&s->sata0.ahci, hd); + + return true; +} + static void ich9_init(Object *obj) { } @@ -64,6 +95,10 @@ static void ich9_realize(DeviceState *dev, Error **errp) if (s->d2p_enabled && !ich9_realize_d2p(s, errp)) { return; } + + if (s->sata_enabled && !ich9_realize_sata(s, errp)) { + return; + } } =20 static void ich9_class_init(ObjectClass *klass, void *data) diff --git a/hw/i386/Kconfig b/hw/i386/Kconfig index d21638f4f9..226d7f6916 100644 --- a/hw/i386/Kconfig +++ b/hw/i386/Kconfig @@ -101,7 +101,6 @@ config Q35 select PCI_EXPRESS_Q35 select ICH9 select LPC_ICH9 - select AHCI_ICH9 select DIMM select SMBIOS select FW_CFG_DMA diff --git a/hw/southbridge/Kconfig b/hw/southbridge/Kconfig index db7259bf6f..f806033d48 100644 --- a/hw/southbridge/Kconfig +++ b/hw/southbridge/Kconfig @@ -4,3 +4,4 @@ config ICH9 bool depends on PCI_EXPRESS imply I82801B11 + select AHCI_ICH9 --=20 2.41.0 From nobody Thu Nov 14 07:10:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 19 Feb 2024 08:40:08 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Bernhard Beschow Cc: "Michael S. Tsirkin" , Ani Sinha , Richard Henderson , Igor Mammedov , Mark Cave-Ayland , Laurent Vivier , Thomas Huth , Marcel Apfelbaum , Eduardo Habkost , Paolo Bonzini , BALATON Zoltan , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 10/14] hw/i2c/smbus: Extract QOM ICH9 definitions to 'smbus_ich9.h' Date: Mon, 19 Feb 2024 17:38:50 +0100 Message-ID: <20240219163855.87326-11-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240219163855.87326-1-philmd@linaro.org> References: <20240219163855.87326-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=philmd@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1708360869506100003 Expose TYPE_ICH9_SMB_DEVICE to the new "hw/i2c/smbus_ich9.h" header. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- MAINTAINERS | 1 + include/hw/i2c/smbus_ich9.h | 25 +++++++++++++++++++++++++ hw/i2c/smbus_ich9.c | 15 ++------------- 3 files changed, 28 insertions(+), 13 deletions(-) create mode 100644 include/hw/i2c/smbus_ich9.h diff --git a/MAINTAINERS b/MAINTAINERS index 937ebb5c96..b896d953af 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2611,6 +2611,7 @@ F: hw/ide/ich.c F: hw/isa/lpc_ich9.c F: hw/southbridge/ich9.c F: include/hw/acpi/ich9*.h +F: include/hw/i2c/smbus_ich9.h F: include/hw/ide/ahci-pci.h F: include/hw/pci-bridge/ich_dmi_pci.h F: include/hw/southbridge/ich9.h diff --git a/include/hw/i2c/smbus_ich9.h b/include/hw/i2c/smbus_ich9.h new file mode 100644 index 0000000000..d716cbca33 --- /dev/null +++ b/include/hw/i2c/smbus_ich9.h @@ -0,0 +1,25 @@ +/* + * QEMU ICH9 SMBus emulation + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#ifndef HW_I2C_SMBUS_ICH9_H +#define HW_I2C_SMBUS_ICH9_H + +#include "qom/object.h" +#include "hw/pci/pci_device.h" +#include "hw/i2c/pm_smbus.h" + +#define TYPE_ICH9_SMB_DEVICE "ICH9-SMB" + +OBJECT_DECLARE_SIMPLE_TYPE(ICH9SMBState, ICH9_SMB_DEVICE) + +struct ICH9SMBState { + PCIDevice dev; + + bool irq_enabled; + + PMSMBus smb; +}; + +#endif diff --git a/hw/i2c/smbus_ich9.c b/hw/i2c/smbus_ich9.c index 208f263ac5..3980bca4c5 100644 --- a/hw/i2c/smbus_ich9.c +++ b/hw/i2c/smbus_ich9.c @@ -1,5 +1,5 @@ /* - * ACPI implementation + * QEMU ICH9 SMBus emulation * * Copyright (c) 2006 Fabrice Bellard * Copyright (c) 2009 Isaku Yamahata @@ -22,8 +22,7 @@ =20 #include "qemu/osdep.h" #include "qemu/range.h" -#include "hw/i2c/pm_smbus.h" -#include "hw/pci/pci.h" +#include "hw/i2c/smbus_ich9.h" #include "migration/vmstate.h" #include "qemu/module.h" =20 @@ -31,16 +30,6 @@ #include "qom/object.h" #include "hw/acpi/acpi_aml_interface.h" =20 -OBJECT_DECLARE_SIMPLE_TYPE(ICH9SMBState, ICH9_SMB_DEVICE) - -struct ICH9SMBState { - PCIDevice dev; - - bool irq_enabled; - - PMSMBus smb; -}; - static bool ich9_vmstate_need_smbus(void *opaque, int version_id) { return pm_smbus_vmstate_needed(); --=20 2.41.0 From nobody Thu Nov 14 07:10:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 19 Feb 2024 08:40:16 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Bernhard Beschow Cc: "Michael S. Tsirkin" , Ani Sinha , Richard Henderson , Igor Mammedov , Mark Cave-Ayland , Laurent Vivier , Thomas Huth , Marcel Apfelbaum , Eduardo Habkost , Paolo Bonzini , BALATON Zoltan , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 11/14] hw/southbridge/ich9: Add the SMBus function Date: Mon, 19 Feb 2024 17:38:51 +0100 Message-ID: <20240219163855.87326-12-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240219163855.87326-1-philmd@linaro.org> References: <20240219163855.87326-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=philmd@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1708360833431100001 Instantiate TYPE_ICH9_SMB_DEVICE in TYPE_ICH9_SOUTHBRIDGE. Since the PC machines can disable SMBus (see the PC_MACHINE_SMBUS dynamic property), add the 'smbus-enabled' property to disable it. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/southbridge/ich9.h | 32 -------------------------------- hw/i2c/smbus_ich9.c | 29 ++++++++++++++++++++++++++++- hw/i386/pc_q35.c | 10 ++-------- hw/southbridge/ich9.c | 21 +++++++++++++++++++++ hw/southbridge/Kconfig | 1 + 5 files changed, 52 insertions(+), 41 deletions(-) diff --git a/include/hw/southbridge/ich9.h b/include/hw/southbridge/ich9.h index ac7f9f4ff5..d4b299bf3c 100644 --- a/include/hw/southbridge/ich9.h +++ b/include/hw/southbridge/ich9.h @@ -173,38 +173,6 @@ struct ICH9LPCState { #define ICH9_APM_ACPI_ENABLE 0x2 #define ICH9_APM_ACPI_DISABLE 0x3 =20 - -/* D31:F3 SMBus controller */ -#define TYPE_ICH9_SMB_DEVICE "ICH9-SMB" - -#define ICH9_A2_SMB_REVISION 0x02 -#define ICH9_SMB_PI 0x00 - -#define ICH9_SMB_SMBMBAR0 0x10 -#define ICH9_SMB_SMBMBAR1 0x14 -#define ICH9_SMB_SMBM_BAR 0 -#define ICH9_SMB_SMBM_SIZE (1 << 8) -#define ICH9_SMB_SMB_BASE 0x20 -#define ICH9_SMB_SMB_BASE_BAR 4 -#define ICH9_SMB_SMB_BASE_SIZE (1 << 5) -#define ICH9_SMB_HOSTC 0x40 -#define ICH9_SMB_HOSTC_SSRESET ((uint8_t)(1 << 3)) -#define ICH9_SMB_HOSTC_I2C_EN ((uint8_t)(1 << 2)) -#define ICH9_SMB_HOSTC_SMB_SMI_EN ((uint8_t)(1 << 1)) -#define ICH9_SMB_HOSTC_HST_EN ((uint8_t)(1 << 0)) - -/* D31:F3 SMBus I/O and memory mapped I/O registers */ -#define ICH9_SMB_DEV 31 -#define ICH9_SMB_FUNC 3 - -#define ICH9_SMB_HST_STS 0x00 -#define ICH9_SMB_HST_CNT 0x02 -#define ICH9_SMB_HST_CMD 0x03 -#define ICH9_SMB_XMIT_SLVA 0x04 -#define ICH9_SMB_HST_D0 0x05 -#define ICH9_SMB_HST_D1 0x06 -#define ICH9_SMB_HOST_BLOCK_DB 0x07 - #define ICH9_LPC_SMI_NEGOTIATED_FEAT_PROP "x-smi-negotiated-features" =20 /* bit positions used in fw_cfg SMI feature negotiation */ diff --git a/hw/i2c/smbus_ich9.c b/hw/i2c/smbus_ich9.c index 3980bca4c5..2c18278090 100644 --- a/hw/i2c/smbus_ich9.c +++ b/hw/i2c/smbus_ich9.c @@ -26,10 +26,37 @@ #include "migration/vmstate.h" #include "qemu/module.h" =20 -#include "hw/southbridge/ich9.h" #include "qom/object.h" #include "hw/acpi/acpi_aml_interface.h" =20 +/* D31:F3 SMBus controller */ + +#define ICH9_A2_SMB_REVISION 0x02 +#define ICH9_SMB_PI 0x00 + +#define ICH9_SMB_SMBMBAR0 0x10 +#define ICH9_SMB_SMBMBAR1 0x14 +#define ICH9_SMB_SMBM_BAR 0 +#define ICH9_SMB_SMBM_SIZE (1 << 8) +#define ICH9_SMB_SMB_BASE 0x20 +#define ICH9_SMB_SMB_BASE_BAR 4 +#define ICH9_SMB_SMB_BASE_SIZE (1 << 5) +#define ICH9_SMB_HOSTC 0x40 +#define ICH9_SMB_HOSTC_SSRESET ((uint8_t)(1 << 3)) +#define ICH9_SMB_HOSTC_I2C_EN ((uint8_t)(1 << 2)) +#define ICH9_SMB_HOSTC_SMB_SMI_EN ((uint8_t)(1 << 1)) +#define ICH9_SMB_HOSTC_HST_EN ((uint8_t)(1 << 0)) + +/* D31:F3 SMBus I/O and memory mapped I/O registers */ + +#define ICH9_SMB_HST_STS 0x00 +#define ICH9_SMB_HST_CNT 0x02 +#define ICH9_SMB_HST_CMD 0x03 +#define ICH9_SMB_XMIT_SLVA 0x04 +#define ICH9_SMB_HST_D0 0x05 +#define ICH9_SMB_HST_D1 0x06 +#define ICH9_SMB_HOST_BLOCK_DB 0x07 + static bool ich9_vmstate_need_smbus(void *opaque, int version_id) { return pm_smbus_vmstate_needed(); diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index 060358d449..7f6ced8a6e 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -236,6 +236,7 @@ static void pc_q35_init(MachineState *machine) OBJECT(host_bus), &error_abort); qdev_prop_set_bit(ich9, "d2p-enabled", false); qdev_prop_set_bit(ich9, "sata-enabled", pcms->sata_enabled); + qdev_prop_set_bit(ich9, "smbus-enabled", pcms->smbus_enabled); qdev_realize_and_unref(ich9, NULL, &error_fatal); =20 /* irq lines */ @@ -309,15 +310,8 @@ static void pc_q35_init(MachineState *machine) } =20 if (pcms->smbus_enabled) { - PCIDevice *smb; - + pcms->smbus =3D I2C_BUS(qdev_get_child_bus(ich9, "i2c")); /* TODO: Populate SPD eeprom data. */ - smb =3D pci_create_simple_multifunction(host_bus, - PCI_DEVFN(ICH9_SMB_DEV, - ICH9_SMB_FUNC), - TYPE_ICH9_SMB_DEVICE); - pcms->smbus =3D I2C_BUS(qdev_get_child_bus(DEVICE(smb), "i2c")); - smbus_eeprom_init(pcms->smbus, 8, NULL, 0); } =20 diff --git a/hw/southbridge/ich9.c b/hw/southbridge/ich9.c index 233dc1c5d7..4d2c298666 100644 --- a/hw/southbridge/ich9.c +++ b/hw/southbridge/ich9.c @@ -15,9 +15,11 @@ #include "hw/pci-bridge/ich_dmi_pci.h" #include "hw/ide/ahci-pci.h" #include "hw/ide.h" +#include "hw/i2c/smbus_ich9.h" =20 #define ICH9_D2P_DEVFN PCI_DEVFN(30, 0) #define ICH9_SATA1_DEVFN PCI_DEVFN(31, 2) +#define ICH9_SMB_DEVFN PCI_DEVFN(31, 3) =20 #define SATA_PORTS 6 =20 @@ -26,10 +28,12 @@ struct ICH9State { =20 I82801b11Bridge d2p; AHCIPCIState sata0; + ICH9SMBState smb; =20 PCIBus *pci_bus; bool d2p_enabled; bool sata_enabled; + bool smbus_enabled; }; =20 static Property ich9_props[] =3D { @@ -37,6 +41,7 @@ static Property ich9_props[] =3D { TYPE_PCIE_BUS, PCIBus *), DEFINE_PROP_BOOL("d2p-enabled", ICH9State, d2p_enabled, true), DEFINE_PROP_BOOL("sata-enabled", ICH9State, sata_enabled, true), + DEFINE_PROP_BOOL("smbus-enabled", ICH9State, smbus_enabled, true), DEFINE_PROP_END_OF_LIST(), }; =20 @@ -79,6 +84,18 @@ static bool ich9_realize_sata(ICH9State *s, Error **errp) return true; } =20 +static bool ich9_realize_smbus(ICH9State *s, Error **errp) +{ + object_initialize_child(OBJECT(s), "smb", &s->smb, TYPE_ICH9_SMB_DEVIC= E); + qdev_prop_set_int32(DEVICE(&s->smb), "addr", ICH9_SMB_DEVFN); + if (!qdev_realize(DEVICE(&s->smb), BUS(s->pci_bus), errp)) { + return false; + } + object_property_add_alias(OBJECT(s), "i2c", OBJECT(&s->smb), "i2c"); + + return true; +} + static void ich9_init(Object *obj) { } @@ -99,6 +116,10 @@ static void ich9_realize(DeviceState *dev, Error **errp) if (s->sata_enabled && !ich9_realize_sata(s, errp)) { return; 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Mon, 19 Feb 2024 08:40:23 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Bernhard Beschow Cc: "Michael S. Tsirkin" , Ani Sinha , Richard Henderson , Igor Mammedov , Mark Cave-Ayland , Laurent Vivier , Thomas Huth , Marcel Apfelbaum , Eduardo Habkost , Paolo Bonzini , BALATON Zoltan , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 12/14] hw/southbridge/ich9: Add the USB EHCI/UHCI functions Date: Mon, 19 Feb 2024 17:38:52 +0100 Message-ID: <20240219163855.87326-13-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240219163855.87326-1-philmd@linaro.org> References: <20240219163855.87326-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=philmd@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1708360853511100005 Instantiate EHCI and UHCI in TYPE_ICH9_SOUTHBRIDGE. Since machines can disable USB, add the 'ehci-count' property. Machine can disable USB functions by setting ehci-count=3D0. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/southbridge/ich9.h | 5 --- hw/i386/pc_q35.c | 62 ++--------------------------------- hw/southbridge/ich9.c | 54 ++++++++++++++++++++++++++++++ hw/southbridge/Kconfig | 2 ++ 4 files changed, 58 insertions(+), 65 deletions(-) diff --git a/include/hw/southbridge/ich9.h b/include/hw/southbridge/ich9.h index d4b299bf3c..7e75496b0b 100644 --- a/include/hw/southbridge/ich9.h +++ b/include/hw/southbridge/ich9.h @@ -103,11 +103,6 @@ struct ICH9LPCState { #define ICH9_PCIE_DEV 28 #define ICH9_PCIE_FUNC_MAX 6 =20 - -/* D29:F0 USB UHCI Controller #1 */ -#define ICH9_USB_UHCI1_DEV 29 -#define ICH9_USB_UHCI1_FUNC 0 - /* D31:F0 LPC Processor Interface */ #define ICH9_RST_CNT_IOPORT 0xCF9 =20 diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index 7f6ced8a6e..e5f5bb0db1 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -50,8 +50,6 @@ #include "hw/ide/ahci-pci.h" #include "hw/intc/ioapic.h" #include "hw/southbridge/ich9.h" -#include "hw/usb.h" -#include "hw/usb/hcd-uhci.h" #include "qapi/error.h" #include "qemu/error-report.h" #include "sysemu/numa.h" @@ -61,59 +59,6 @@ #include "hw/acpi/acpi.h" #include "target/i386/cpu.h" =20 -struct ehci_companions { - const char *name; - int func; - int port; -}; - -static const struct ehci_companions ich9_1d[] =3D { - { .name =3D TYPE_ICH9_USB_UHCI(1), .func =3D 0, .port =3D 0 }, - { .name =3D TYPE_ICH9_USB_UHCI(2), .func =3D 1, .port =3D 2 }, - { .name =3D TYPE_ICH9_USB_UHCI(3), .func =3D 2, .port =3D 4 }, -}; - -static const struct ehci_companions ich9_1a[] =3D { - { .name =3D TYPE_ICH9_USB_UHCI(4), .func =3D 0, .port =3D 0 }, - { .name =3D TYPE_ICH9_USB_UHCI(5), .func =3D 1, .port =3D 2 }, - { .name =3D TYPE_ICH9_USB_UHCI(6), .func =3D 2, .port =3D 4 }, -}; - -static int ehci_create_ich9_with_companions(PCIBus *bus, int slot) -{ - const struct ehci_companions *comp; - PCIDevice *ehci, *uhci; - BusState *usbbus; - const char *name; - int i; - - switch (slot) { - case 0x1d: - name =3D "ich9-usb-ehci1"; - comp =3D ich9_1d; - break; - case 0x1a: - name =3D "ich9-usb-ehci2"; - comp =3D ich9_1a; - break; - default: - return -1; - } - - ehci =3D pci_new_multifunction(PCI_DEVFN(slot, 7), name); - pci_realize_and_unref(ehci, bus, &error_fatal); - usbbus =3D QLIST_FIRST(&ehci->qdev.child_bus); - - for (i =3D 0; i < 3; i++) { - uhci =3D pci_new_multifunction(PCI_DEVFN(slot, comp[i].func), - comp[i].name); - qdev_prop_set_string(&uhci->qdev, "masterbus", usbbus->name); - qdev_prop_set_uint32(&uhci->qdev, "firstport", comp[i].port); - pci_realize_and_unref(uhci, bus, &error_fatal); - } - return 0; -} - /* PC hardware initialisation */ static void pc_q35_init(MachineState *machine) { @@ -237,6 +182,8 @@ static void pc_q35_init(MachineState *machine) qdev_prop_set_bit(ich9, "d2p-enabled", false); qdev_prop_set_bit(ich9, "sata-enabled", pcms->sata_enabled); qdev_prop_set_bit(ich9, "smbus-enabled", pcms->smbus_enabled); + /* Should we create 6 UHCI according to ich9 spec? */ + qdev_prop_set_uint8(ich9, "ehci-count", machine_usb(machine) ? 1 : 0); qdev_realize_and_unref(ich9, NULL, &error_fatal); =20 /* irq lines */ @@ -304,11 +251,6 @@ static void pc_q35_init(MachineState *machine) idebus[1] =3D qdev_get_child_bus(ich9, "ide.1"); } =20 - if (machine_usb(machine)) { - /* Should we create 6 UHCI according to ich9 spec? */ - ehci_create_ich9_with_companions(host_bus, 0x1d); - } - if (pcms->smbus_enabled) { pcms->smbus =3D I2C_BUS(qdev_get_child_bus(ich9, "i2c")); /* TODO: Populate SPD eeprom data. */ diff --git a/hw/southbridge/ich9.c b/hw/southbridge/ich9.c index 4d2c298666..085d75e569 100644 --- a/hw/southbridge/ich9.c +++ b/hw/southbridge/ich9.c @@ -16,12 +16,18 @@ #include "hw/ide/ahci-pci.h" #include "hw/ide.h" #include "hw/i2c/smbus_ich9.h" +#include "hw/usb.h" +#include "hw/usb/hcd-ehci.h" +#include "hw/usb/hcd-uhci.h" =20 #define ICH9_D2P_DEVFN PCI_DEVFN(30, 0) #define ICH9_SATA1_DEVFN PCI_DEVFN(31, 2) #define ICH9_SMB_DEVFN PCI_DEVFN(31, 3) +#define ICH9_EHCI_FUNC 7 =20 #define SATA_PORTS 6 +#define EHCI_PER_FN 2 +#define UHCI_PER_FN 3 =20 struct ICH9State { DeviceState parent_obj; @@ -29,11 +35,14 @@ struct ICH9State { I82801b11Bridge d2p; AHCIPCIState sata0; ICH9SMBState smb; + EHCIPCIState ehci[EHCI_PER_FN]; + UHCIState uhci[EHCI_PER_FN * UHCI_PER_FN]; =20 PCIBus *pci_bus; bool d2p_enabled; bool sata_enabled; bool smbus_enabled; + uint8_t ehci_count; }; =20 static Property ich9_props[] =3D { @@ -42,6 +51,7 @@ static Property ich9_props[] =3D { DEFINE_PROP_BOOL("d2p-enabled", ICH9State, d2p_enabled, true), DEFINE_PROP_BOOL("sata-enabled", ICH9State, sata_enabled, true), DEFINE_PROP_BOOL("smbus-enabled", ICH9State, smbus_enabled, true), + DEFINE_PROP_UINT8("ehci-count", ICH9State, ehci_count, 2), DEFINE_PROP_END_OF_LIST(), }; =20 @@ -96,6 +106,46 @@ static bool ich9_realize_smbus(ICH9State *s, Error **er= rp) return true; } =20 +static bool ich9_realize_usb(ICH9State *s, Error **errp) +{ + if (!module_object_class_by_name(TYPE_ICH9_USB_UHCI(0)) + || !module_object_class_by_name("ich9-usb-ehci0")) { + error_setg(errp, "USB functions not available in this build"); + return false; + } + for (unsigned e =3D 0; e < s->ehci_count; e++) { + g_autofree gchar *ename =3D g_strdup_printf("ich9-usb-ehci%u", e += 1); + EHCIPCIState *ehci =3D &s->ehci[e]; + const unsigned devid =3D e ? 0x1a : 0x1d; + BusState *masterbus; + + object_initialize_child(OBJECT(s), "ehci[*]", ehci, ename); + qdev_prop_set_int32(DEVICE(ehci), "addr", PCI_DEVFN(devid, + ICH9_EHCI_FUNC= )); + if (!qdev_realize(DEVICE(ehci), BUS(s->pci_bus), errp)) { + return false; + } + masterbus =3D QLIST_FIRST(&DEVICE(ehci)->child_bus); + + for (unsigned u =3D 0; u < UHCI_PER_FN; u++) { + unsigned c =3D UHCI_PER_FN * e + u; + UHCIState *uhci =3D &s->uhci[c]; + g_autofree gchar *cname =3D g_strdup_printf("ich9-usb-uhci%u",= c + 1); + + object_initialize_child(OBJECT(s), "uhci[*]", uhci, cname); + qdev_prop_set_bit(DEVICE(uhci), "multifunction", true); + qdev_prop_set_int32(DEVICE(uhci), "addr", PCI_DEVFN(devid, u)); + qdev_prop_set_string(DEVICE(uhci), "masterbus", masterbus->nam= e); + qdev_prop_set_uint32(DEVICE(uhci), "firstport", 2 * u); + if (!qdev_realize(DEVICE(uhci), BUS(s->pci_bus), errp)) { + return false; + } + } + } + + return true; +} + static void ich9_init(Object *obj) { } @@ -120,6 +170,10 @@ static void ich9_realize(DeviceState *dev, Error **err= p) if (s->smbus_enabled && !ich9_realize_smbus(s, errp)) { return; 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Mon, 19 Feb 2024 08:40:29 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Bernhard Beschow Cc: "Michael S. Tsirkin" , Ani Sinha , Richard Henderson , Igor Mammedov , Mark Cave-Ayland , Laurent Vivier , Thomas Huth , Marcel Apfelbaum , Eduardo Habkost , Paolo Bonzini , BALATON Zoltan , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 13/14] hw/southbridge/ich9: Extract LPC definitions to 'hw/isa/ich9_lpc.h' Date: Mon, 19 Feb 2024 17:38:53 +0100 Message-ID: <20240219163855.87326-14-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240219163855.87326-1-philmd@linaro.org> References: <20240219163855.87326-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=philmd@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1708360885693100005 Restrict ICH9 LPC/ISA definitions by moving them to the "hw/isa/ich9_lpc.h" header. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- MAINTAINERS | 1 + include/hw/isa/ich9_lpc.h | 166 ++++++++++++++++++++++++++++++++++ include/hw/southbridge/ich9.h | 158 ++------------------------------ hw/acpi/ich9.c | 1 + hw/acpi/ich9_tco.c | 1 + hw/i386/acpi-build.c | 1 + hw/i386/pc_q35.c | 1 + hw/isa/lpc_ich9.c | 34 ++++++- tests/qtest/tco-test.c | 2 +- 9 files changed, 208 insertions(+), 157 deletions(-) create mode 100644 include/hw/isa/ich9_lpc.h diff --git a/MAINTAINERS b/MAINTAINERS index b896d953af..31ddbc565b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2613,6 +2613,7 @@ F: hw/southbridge/ich9.c F: include/hw/acpi/ich9*.h F: include/hw/i2c/smbus_ich9.h F: include/hw/ide/ahci-pci.h +F: include/hw/isa/ich9_lpc.h F: include/hw/pci-bridge/ich_dmi_pci.h F: include/hw/southbridge/ich9.h =20 diff --git a/include/hw/isa/ich9_lpc.h b/include/hw/isa/ich9_lpc.h new file mode 100644 index 0000000000..b64d88b395 --- /dev/null +++ b/include/hw/isa/ich9_lpc.h @@ -0,0 +1,166 @@ +/* + * QEMU ICH9 PCI-to-LPC/ISA bridge emulation + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef HW_ISA_ICH9_LPC_H +#define HW_ISA_ICH9_LPC_H + +#include "exec/memory.h" +#include "hw/isa/apm.h" +#include "hw/acpi/ich9.h" +#include "hw/intc/ioapic.h" +#include "hw/pci/pci_device.h" +#include "hw/rtc/mc146818rtc.h" +#include "qemu/notify.h" +#include "qom/object.h" + +#define TYPE_ICH9_LPC_DEVICE "ICH9-LPC" +OBJECT_DECLARE_SIMPLE_TYPE(ICH9LPCState, ICH9_LPC_DEVICE) + +#define ICH9_CC_SIZE (16 * 1024) /* 16KB. Chipset configuration registers = */ + +struct ICH9LPCState { + /* ICH9 LPC PCI to ISA bridge */ + PCIDevice d; + + /* (pci device, intx) -> pirq + * In real chipset case, the unused slots are never used + * as ICH9 supports only D25-D31 irq routing. + * On the other hand in qemu case, any slot/function can be populated + * via command line option. + * So fallback interrupt routing for any devices in any slots is neces= sary. + */ + uint8_t irr[PCI_SLOT_MAX][PCI_NUM_PINS]; + + MC146818RtcState rtc; + APMState apm; + ICH9LPCPMRegs pm; + uint32_t sci_level; /* track sci level */ + uint8_t sci_gsi; + + /* 2.24 Pin Straps */ + struct { + bool spkr_hi; + } pin_strap; + + /* 10.1 Chipset Configuration registers(Memory Space) + which is pointed by RCBA */ + uint8_t chip_config[ICH9_CC_SIZE]; + + /* + * 13.7.5 RST_CNT---Reset Control Register (LPC I/F---D31:F0) + * + * register contents and IO memory region + */ + uint8_t rst_cnt; + MemoryRegion rst_cnt_mem; + + /* SMI feature negotiation via fw_cfg */ + uint64_t smi_host_features; /* guest-invisible, host endian */ + uint8_t smi_host_features_le[8]; /* guest-visible, read-only, little + * endian uint64_t */ + uint8_t smi_guest_features_le[8]; /* guest-visible, read-write, little + * endian uint64_t */ + uint8_t smi_features_ok; /* guest-visible, read-only; selecti= ng it + * triggers feature lockdown */ + uint64_t smi_negotiated_features; /* guest-invisible, host endian */ + + MemoryRegion rcrb_mem; /* root complex register block */ + Notifier machine_ready; + + qemu_irq gsi[IOAPIC_NUM_PINS]; +}; + +#define ICH9_MASK(bit, ms_bit, ls_bit) \ +((uint##bit##_t)(((1ULL << ((ms_bit) + 1)) - 1) & ~((1ULL << ls_bit) - 1))) + +#define ICH9_CC_SIZE (16 * 1024) /* 16KB. Chipset configuration registers = */ + +/* ICH9: Chipset Configuration Registers */ +#define ICH9_CC_ADDR_MASK (ICH9_CC_SIZE - 1) + +#define ICH9_CC +#define ICH9_CC_D28IP 0x310C +#define ICH9_CC_D28IP_SHIFT 4 +#define ICH9_CC_D28IP_MASK 0xf +#define ICH9_CC_D28IP_DEFAULT 0x00214321 +#define ICH9_CC_D31IR 0x3140 +#define ICH9_CC_D30IR 0x3142 +#define ICH9_CC_D29IR 0x3144 +#define ICH9_CC_D28IR 0x3146 +#define ICH9_CC_D27IR 0x3148 +#define ICH9_CC_D26IR 0x314C +#define ICH9_CC_D25IR 0x3150 +#define ICH9_CC_DIR_DEFAULT 0x3210 +#define ICH9_CC_D30IR_DEFAULT 0x0 +#define ICH9_CC_DIR_SHIFT 4 +#define ICH9_CC_DIR_MASK 0x7 +#define ICH9_CC_OIC 0x31FF +#define ICH9_CC_OIC_AEN 0x1 +#define ICH9_CC_GCS 0x3410 +#define ICH9_CC_GCS_DEFAULT 0x00000020 +#define ICH9_CC_GCS_NO_REBOOT (1 << 5) + +/* D31:F0 LPC Processor Interface */ +#define ICH9_RST_CNT_IOPORT 0xCF9 + +/* D31:F1 LPC controller */ +#define ICH9_A2_LPC "ICH9 A2 LPC" +#define ICH9_A2_LPC_SAVEVM_VERSION 0 + +#define ICH9_A2_LPC_REVISION 0x2 +#define ICH9_LPC_NB_PIRQS 8 /* PCI A-H */ + +#define ICH9_LPC_PMBASE 0x40 +#define ICH9_LPC_PMBASE_BASE_ADDRESS_MASK ICH9_MASK(32, 15, 7) +#define ICH9_LPC_PMBASE_RTE 0x1 +#define ICH9_LPC_PMBASE_DEFAULT 0x1 + +#define ICH9_LPC_ACPI_CTRL 0x44 +#define ICH9_LPC_ACPI_CTRL_ACPI_EN 0x80 +#define ICH9_LPC_ACPI_CTRL_SCI_IRQ_SEL_MASK ICH9_MASK(8, 2, 0) +#define ICH9_LPC_ACPI_CTRL_9 0x0 +#define ICH9_LPC_ACPI_CTRL_10 0x1 +#define ICH9_LPC_ACPI_CTRL_11 0x2 +#define ICH9_LPC_ACPI_CTRL_20 0x4 +#define ICH9_LPC_ACPI_CTRL_21 0x5 +#define ICH9_LPC_ACPI_CTRL_DEFAULT 0x0 + +#define ICH9_LPC_PIRQA_ROUT 0x60 +#define ICH9_LPC_PIRQB_ROUT 0x61 +#define ICH9_LPC_PIRQC_ROUT 0x62 +#define ICH9_LPC_PIRQD_ROUT 0x63 + +#define ICH9_LPC_PIRQE_ROUT 0x68 +#define ICH9_LPC_PIRQF_ROUT 0x69 +#define ICH9_LPC_PIRQG_ROUT 0x6a +#define ICH9_LPC_PIRQH_ROUT 0x6b + +#define ICH9_LPC_PIRQ_ROUT_IRQEN 0x80 +#define ICH9_LPC_PIRQ_ROUT_MASK ICH9_MASK(8, 3, 0) +#define ICH9_LPC_PIRQ_ROUT_DEFAULT 0x80 + +#define ICH9_LPC_GEN_PMCON_1 0xa0 +#define ICH9_LPC_GEN_PMCON_1_SMI_LOCK (1 << 4) +#define ICH9_LPC_GEN_PMCON_2 0xa2 +#define ICH9_LPC_GEN_PMCON_3 0xa4 +#define ICH9_LPC_GEN_PMCON_LOCK 0xa6 + +#define ICH9_LPC_RCBA 0xf0 +#define ICH9_LPC_RCBA_BA_MASK ICH9_MASK(32, 31, 14) +#define ICH9_LPC_RCBA_EN 0x1 +#define ICH9_LPC_RCBA_DEFAULT 0x0 + +#define ICH9_LPC_PIC_NUM_PINS 16 +#define ICH9_LPC_IOAPIC_NUM_PINS 24 + +/* D31:F0 power management I/O registers + offset from the address ICH9_LPC_PMBASE */ + +/* FADT ACPI_ENABLE/ACPI_DISABLE */ +#define ICH9_APM_ACPI_ENABLE 0x2 +#define ICH9_APM_ACPI_DISABLE 0x3 + +#endif diff --git a/include/hw/southbridge/ich9.h b/include/hw/southbridge/ich9.h index 7e75496b0b..d6c3b5ece3 100644 --- a/include/hw/southbridge/ich9.h +++ b/include/hw/southbridge/ich9.h @@ -1,173 +1,27 @@ +/* + * QEMU Intel ICH9 south bridge emulation + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + #ifndef HW_SOUTHBRIDGE_ICH9_H #define HW_SOUTHBRIDGE_ICH9_H =20 -#include "hw/isa/apm.h" -#include "hw/acpi/ich9.h" -#include "hw/intc/ioapic.h" -#include "hw/pci/pci.h" -#include "hw/pci/pci_device.h" -#include "hw/rtc/mc146818rtc.h" -#include "exec/memory.h" -#include "qemu/notify.h" #include "qom/object.h" =20 #define TYPE_ICH9_SOUTHBRIDGE "ICH9-southbridge" OBJECT_DECLARE_SIMPLE_TYPE(ICH9State, ICH9_SOUTHBRIDGE) =20 -#define ICH9_CC_SIZE (16 * 1024) /* 16KB. Chipset configuration registers = */ - -#define TYPE_ICH9_LPC_DEVICE "ICH9-LPC" -OBJECT_DECLARE_SIMPLE_TYPE(ICH9LPCState, ICH9_LPC_DEVICE) - -struct ICH9LPCState { - /* ICH9 LPC PCI to ISA bridge */ - PCIDevice d; - - /* (pci device, intx) -> pirq - * In real chipset case, the unused slots are never used - * as ICH9 supports only D25-D31 irq routing. - * On the other hand in qemu case, any slot/function can be populated - * via command line option. - * So fallback interrupt routing for any devices in any slots is neces= sary. - */ - uint8_t irr[PCI_SLOT_MAX][PCI_NUM_PINS]; - - MC146818RtcState rtc; - APMState apm; - ICH9LPCPMRegs pm; - uint32_t sci_level; /* track sci level */ - uint8_t sci_gsi; - - /* 2.24 Pin Straps */ - struct { - bool spkr_hi; - } pin_strap; - - /* 10.1 Chipset Configuration registers(Memory Space) - which is pointed by RCBA */ - uint8_t chip_config[ICH9_CC_SIZE]; - - /* - * 13.7.5 RST_CNT---Reset Control Register (LPC I/F---D31:F0) - * - * register contents and IO memory region - */ - uint8_t rst_cnt; - MemoryRegion rst_cnt_mem; - - /* SMI feature negotiation via fw_cfg */ - uint64_t smi_host_features; /* guest-invisible, host endian */ - uint8_t smi_host_features_le[8]; /* guest-visible, read-only, little - * endian uint64_t */ - uint8_t smi_guest_features_le[8]; /* guest-visible, read-write, little - * endian uint64_t */ - uint8_t smi_features_ok; /* guest-visible, read-only; selecti= ng it - * triggers feature lockdown */ - uint64_t smi_negotiated_features; /* guest-invisible, host endian */ - - MemoryRegion rcrb_mem; /* root complex register block */ - Notifier machine_ready; - - qemu_irq gsi[IOAPIC_NUM_PINS]; -}; - -#define ICH9_MASK(bit, ms_bit, ls_bit) \ -((uint##bit##_t)(((1ULL << ((ms_bit) + 1)) - 1) & ~((1ULL << ls_bit) - 1))) - -/* ICH9: Chipset Configuration Registers */ -#define ICH9_CC_ADDR_MASK (ICH9_CC_SIZE - 1) - -#define ICH9_CC -#define ICH9_CC_D28IP 0x310C -#define ICH9_CC_D28IP_SHIFT 4 -#define ICH9_CC_D28IP_MASK 0xf -#define ICH9_CC_D28IP_DEFAULT 0x00214321 -#define ICH9_CC_D31IR 0x3140 -#define ICH9_CC_D30IR 0x3142 -#define ICH9_CC_D29IR 0x3144 -#define ICH9_CC_D28IR 0x3146 -#define ICH9_CC_D27IR 0x3148 -#define ICH9_CC_D26IR 0x314C -#define ICH9_CC_D25IR 0x3150 -#define ICH9_CC_DIR_DEFAULT 0x3210 -#define ICH9_CC_D30IR_DEFAULT 0x0 -#define ICH9_CC_DIR_SHIFT 4 -#define ICH9_CC_DIR_MASK 0x7 -#define ICH9_CC_OIC 0x31FF -#define ICH9_CC_OIC_AEN 0x1 -#define ICH9_CC_GCS 0x3410 -#define ICH9_CC_GCS_DEFAULT 0x00000020 -#define ICH9_CC_GCS_NO_REBOOT (1 << 5) - /* D28:F[0-5] */ #define ICH9_PCIE_DEV 28 #define ICH9_PCIE_FUNC_MAX 6 =20 -/* D31:F0 LPC Processor Interface */ -#define ICH9_RST_CNT_IOPORT 0xCF9 - /* D31:F1 LPC controller */ -#define ICH9_A2_LPC "ICH9 A2 LPC" -#define ICH9_A2_LPC_SAVEVM_VERSION 0 - #define ICH9_LPC_DEV 31 #define ICH9_LPC_FUNC 0 =20 -#define ICH9_A2_LPC_REVISION 0x2 -#define ICH9_LPC_NB_PIRQS 8 /* PCI A-H */ - -#define ICH9_LPC_PMBASE 0x40 -#define ICH9_LPC_PMBASE_BASE_ADDRESS_MASK ICH9_MASK(32, 15, 7) -#define ICH9_LPC_PMBASE_RTE 0x1 -#define ICH9_LPC_PMBASE_DEFAULT 0x1 - -#define ICH9_LPC_ACPI_CTRL 0x44 -#define ICH9_LPC_ACPI_CTRL_ACPI_EN 0x80 -#define ICH9_LPC_ACPI_CTRL_SCI_IRQ_SEL_MASK ICH9_MASK(8, 2, 0) -#define ICH9_LPC_ACPI_CTRL_9 0x0 -#define ICH9_LPC_ACPI_CTRL_10 0x1 -#define ICH9_LPC_ACPI_CTRL_11 0x2 -#define ICH9_LPC_ACPI_CTRL_20 0x4 -#define ICH9_LPC_ACPI_CTRL_21 0x5 -#define ICH9_LPC_ACPI_CTRL_DEFAULT 0x0 - -#define ICH9_LPC_PIRQA_ROUT 0x60 -#define ICH9_LPC_PIRQB_ROUT 0x61 -#define ICH9_LPC_PIRQC_ROUT 0x62 -#define ICH9_LPC_PIRQD_ROUT 0x63 - -#define ICH9_LPC_PIRQE_ROUT 0x68 -#define ICH9_LPC_PIRQF_ROUT 0x69 -#define ICH9_LPC_PIRQG_ROUT 0x6a -#define ICH9_LPC_PIRQH_ROUT 0x6b - -#define ICH9_LPC_PIRQ_ROUT_IRQEN 0x80 -#define ICH9_LPC_PIRQ_ROUT_MASK ICH9_MASK(8, 3, 0) -#define ICH9_LPC_PIRQ_ROUT_DEFAULT 0x80 - -#define ICH9_LPC_GEN_PMCON_1 0xa0 -#define ICH9_LPC_GEN_PMCON_1_SMI_LOCK (1 << 4) -#define ICH9_LPC_GEN_PMCON_2 0xa2 -#define ICH9_LPC_GEN_PMCON_3 0xa4 -#define ICH9_LPC_GEN_PMCON_LOCK 0xa6 - -#define ICH9_LPC_RCBA 0xf0 -#define ICH9_LPC_RCBA_BA_MASK ICH9_MASK(32, 31, 14) -#define ICH9_LPC_RCBA_EN 0x1 -#define ICH9_LPC_RCBA_DEFAULT 0x0 - -#define ICH9_LPC_PIC_NUM_PINS 16 -#define ICH9_LPC_IOAPIC_NUM_PINS 24 - #define ICH9_GPIO_GSI "gsi" =20 -/* D31:F0 power management I/O registers - offset from the address ICH9_LPC_PMBASE */ - -/* FADT ACPI_ENABLE/ACPI_DISABLE */ -#define ICH9_APM_ACPI_ENABLE 0x2 -#define ICH9_APM_ACPI_DISABLE 0x3 - #define ICH9_LPC_SMI_NEGOTIATED_FEAT_PROP "x-smi-negotiated-features" =20 /* bit positions used in fw_cfg SMI feature negotiation */ diff --git a/hw/acpi/ich9.c b/hw/acpi/ich9.c index 660fa6a082..5e293ffb2a 100644 --- a/hw/acpi/ich9.c +++ b/hw/acpi/ich9.c @@ -37,6 +37,7 @@ #include "hw/acpi/ich9_tco.h" #include "hw/acpi/acpi_dev_interface.h" #include "hw/southbridge/ich9.h" +#include "hw/isa/ich9_lpc.h" #include "hw/mem/pc-dimm.h" #include "hw/mem/nvdimm.h" =20 diff --git a/hw/acpi/ich9_tco.c b/hw/acpi/ich9_tco.c index dd4aff82e0..7499ec17db 100644 --- a/hw/acpi/ich9_tco.c +++ b/hw/acpi/ich9_tco.c @@ -13,6 +13,7 @@ #include "migration/vmstate.h" =20 #include "hw/acpi/ich9_tco.h" +#include "hw/isa/ich9_lpc.h" #include "trace.h" =20 enum { diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index d3ce96dd9f..34f3f03949 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -56,6 +56,7 @@ =20 /* Supported chipsets: */ #include "hw/southbridge/ich9.h" +#include "hw/isa/ich9_lpc.h" #include "hw/acpi/pcihp.h" #include "hw/i386/fw_cfg.h" #include "hw/i386/pc.h" diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index e5f5bb0db1..573a5a0bc0 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -50,6 +50,7 @@ #include "hw/ide/ahci-pci.h" #include "hw/intc/ioapic.h" #include "hw/southbridge/ich9.h" +#include "hw/isa/ich9_lpc.h" #include "qapi/error.h" #include "qemu/error-report.h" #include "sysemu/numa.h" diff --git a/hw/isa/lpc_ich9.c b/hw/isa/lpc_ich9.c index 70c6e8a093..685ac38c72 100644 --- a/hw/isa/lpc_ich9.c +++ b/hw/isa/lpc_ich9.c @@ -1,5 +1,5 @@ /* - * QEMU ICH9 Emulation + * QEMU ICH9 LPC PCI-to-ISA bridge Emulation * * Copyright (c) 2006 Fabrice Bellard * Copyright (c) 2009, 2010, 2011 @@ -42,6 +42,7 @@ #include "hw/pci/pci.h" #include "hw/southbridge/ich9.h" #include "hw/i386/pc.h" +#include "hw/isa/ich9_lpc.h" #include "hw/acpi/acpi.h" #include "hw/acpi/ich9.h" #include "hw/pci/pci_bus.h" @@ -54,10 +55,35 @@ #include "hw/acpi/acpi_aml_interface.h" #include "trace.h" =20 -/*************************************************************************= ****/ -/* ICH9 LPC PCI to ISA bridge */ +#define ICH9_A2_LPC_REVISION 0x2 +#define ICH9_LPC_NB_PIRQS 8 /* PCI A-H */ =20 -/* chipset configuration register +/* ICH9: Chipset Configuration Registers */ +#define ICH9_CC_ADDR_MASK (ICH9_CC_SIZE - 1) + +#define ICH9_CC +#define ICH9_CC_D28IP 0x310C +#define ICH9_CC_D28IP_SHIFT 4 +#define ICH9_CC_D28IP_MASK 0xf +#define ICH9_CC_D28IP_DEFAULT 0x00214321 +#define ICH9_CC_D31IR 0x3140 +#define ICH9_CC_D30IR 0x3142 +#define ICH9_CC_D29IR 0x3144 +#define ICH9_CC_D28IR 0x3146 +#define ICH9_CC_D27IR 0x3148 +#define ICH9_CC_D26IR 0x314C +#define ICH9_CC_D25IR 0x3150 +#define ICH9_CC_DIR_DEFAULT 0x3210 +#define ICH9_CC_D30IR_DEFAULT 0x0 +#define ICH9_CC_DIR_SHIFT 4 +#define ICH9_CC_DIR_MASK 0x7 +#define ICH9_CC_OIC 0x31FF +#define ICH9_CC_OIC_AEN 0x1 +#define ICH9_CC_GCS 0x3410 +#define ICH9_CC_GCS_DEFAULT 0x00000020 +#define ICH9_CC_GCS_NO_REBOOT (1 << 5) + +/* * to access chipset configuration registers, pci_[sg]et_{byte, word, long} * are used. * Although it's not pci configuration space, it's little endian as Intel. diff --git a/tests/qtest/tco-test.c b/tests/qtest/tco-test.c index 0547d41173..c5974e72bd 100644 --- a/tests/qtest/tco-test.c +++ b/tests/qtest/tco-test.c @@ -14,7 +14,7 @@ #include "libqos/pci-pc.h" #include "qapi/qmp/qdict.h" #include "hw/pci/pci_regs.h" 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Tsirkin" , Ani Sinha , Richard Henderson , Igor Mammedov , Mark Cave-Ayland , Laurent Vivier , Thomas Huth , Marcel Apfelbaum , Eduardo Habkost , Paolo Bonzini , BALATON Zoltan , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 14/14] hw/southbridge/ich9: Add the LPC / ISA bridge function Date: Mon, 19 Feb 2024 17:38:54 +0100 Message-ID: <20240219163855.87326-15-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240219163855.87326-1-philmd@linaro.org> References: <20240219163855.87326-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::229; envelope-from=philmd@linaro.org; helo=mail-lj1-x229.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1708360877616100001 Instantiate TYPE_ICH9_LPC_DEVICE in TYPE_ICH9_SOUTHBRIDGE. Expose the SMM property so the Q35 machine can disable it (depending on the accelerator used). Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/southbridge/ich9.h | 4 ---- hw/i386/pc_q35.c | 12 +++--------- hw/isa/lpc_ich9.c | 3 +++ hw/southbridge/ich9.c | 14 ++++++++++++++ hw/i386/Kconfig | 1 - hw/southbridge/Kconfig | 1 + 6 files changed, 21 insertions(+), 14 deletions(-) diff --git a/include/hw/southbridge/ich9.h b/include/hw/southbridge/ich9.h index d6c3b5ece3..a8da4a8665 100644 --- a/include/hw/southbridge/ich9.h +++ b/include/hw/southbridge/ich9.h @@ -16,10 +16,6 @@ OBJECT_DECLARE_SIMPLE_TYPE(ICH9State, ICH9_SOUTHBRIDGE) #define ICH9_PCIE_DEV 28 #define ICH9_PCIE_FUNC_MAX 6 =20 -/* D31:F1 LPC controller */ -#define ICH9_LPC_DEV 31 -#define ICH9_LPC_FUNC 0 - #define ICH9_GPIO_GSI "gsi" =20 #define ICH9_LPC_SMI_NEGOTIATED_FEAT_PROP "x-smi-negotiated-features" diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index 573a5a0bc0..0fe43e8e2d 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -50,7 +50,6 @@ #include "hw/ide/ahci-pci.h" #include "hw/intc/ioapic.h" #include "hw/southbridge/ich9.h" -#include "hw/isa/ich9_lpc.h" #include "qapi/error.h" #include "qemu/error-report.h" #include "sysemu/numa.h" @@ -69,7 +68,6 @@ static void pc_q35_init(MachineState *machine) Object *phb; PCIBus *host_bus; DeviceState *ich9; - PCIDevice *lpc; Object *lpc_obj; DeviceState *lpc_dev; BusState *idebus[2] =3D { }; @@ -181,6 +179,7 @@ static void pc_q35_init(MachineState *machine) object_property_set_link(OBJECT(ich9), "mch-pcie-bus", OBJECT(host_bus), &error_abort); qdev_prop_set_bit(ich9, "d2p-enabled", false); + qdev_prop_set_bit(ich9, "smm-enabled", x86_machine_is_smm_enabled(x86m= s)); qdev_prop_set_bit(ich9, "sata-enabled", pcms->sata_enabled); qdev_prop_set_bit(ich9, "smbus-enabled", pcms->smbus_enabled); /* Should we create 6 UHCI according to ich9 spec? */ @@ -191,13 +190,8 @@ static void pc_q35_init(MachineState *machine) gsi_state =3D pc_gsi_create(&x86ms->gsi, true); =20 /* create ISA bus */ - lpc =3D pci_new_multifunction(PCI_DEVFN(ICH9_LPC_DEV, ICH9_LPC_FUNC), - TYPE_ICH9_LPC_DEVICE); - lpc_obj =3D OBJECT(lpc); - lpc_dev =3D DEVICE(lpc); - qdev_prop_set_bit(lpc_dev, "smm-enabled", - x86_machine_is_smm_enabled(x86ms)); - pci_realize_and_unref(lpc, host_bus, &error_fatal); + lpc_obj =3D object_resolve_path_component(OBJECT(ich9), "lpc"); + lpc_dev =3D DEVICE(lpc_obj); for (i =3D 0; i < IOAPIC_NUM_PINS; i++) { qdev_connect_gpio_out_named(lpc_dev, ICH9_GPIO_GSI, i, x86ms->gsi[= i]); } diff --git a/hw/isa/lpc_ich9.c b/hw/isa/lpc_ich9.c index 685ac38c72..4d7b5c0c64 100644 --- a/hw/isa/lpc_ich9.c +++ b/hw/isa/lpc_ich9.c @@ -55,6 +55,9 @@ #include "hw/acpi/acpi_aml_interface.h" #include "trace.h" =20 +#define ICH9_LPC_DEV 31 +#define ICH9_LPC_FUNC 0 + #define ICH9_A2_LPC_REVISION 0x2 #define ICH9_LPC_NB_PIRQS 8 /* PCI A-H */ =20 diff --git a/hw/southbridge/ich9.c b/hw/southbridge/ich9.c index 085d75e569..57a05b35e1 100644 --- a/hw/southbridge/ich9.c +++ b/hw/southbridge/ich9.c @@ -13,6 +13,7 @@ #include "hw/southbridge/ich9.h" #include "hw/pci/pci.h" #include "hw/pci-bridge/ich_dmi_pci.h" +#include "hw/isa/ich9_lpc.h" #include "hw/ide/ahci-pci.h" #include "hw/ide.h" #include "hw/i2c/smbus_ich9.h" @@ -21,6 +22,7 @@ #include "hw/usb/hcd-uhci.h" =20 #define ICH9_D2P_DEVFN PCI_DEVFN(30, 0) +#define ICH9_LPC_DEVFN PCI_DEVFN(31, 0) #define ICH9_SATA1_DEVFN PCI_DEVFN(31, 2) #define ICH9_SMB_DEVFN PCI_DEVFN(31, 3) #define ICH9_EHCI_FUNC 7 @@ -34,6 +36,7 @@ struct ICH9State { =20 I82801b11Bridge d2p; AHCIPCIState sata0; + ICH9LPCState lpc; ICH9SMBState smb; EHCIPCIState ehci[EHCI_PER_FN]; UHCIState uhci[EHCI_PER_FN * UHCI_PER_FN]; @@ -148,6 +151,13 @@ static bool ich9_realize_usb(ICH9State *s, Error **err= p) =20 static void ich9_init(Object *obj) { + ICH9State *s =3D ICH9_SOUTHBRIDGE(obj); + + object_initialize_child(obj, "lpc", &s->lpc, TYPE_ICH9_LPC_DEVICE); + qdev_prop_set_int32(DEVICE(&s->lpc), "addr", ICH9_LPC_DEVFN); + qdev_prop_set_bit(DEVICE(&s->lpc), "multifunction", true); + object_property_add_alias(obj, "smm-enabled", + OBJECT(&s->lpc), "smm-enabled"); } =20 static void ich9_realize(DeviceState *dev, Error **errp) @@ -163,6 +173,10 @@ static void ich9_realize(DeviceState *dev, Error **err= p) return; } =20 + if (!qdev_realize(DEVICE(&s->lpc), BUS(s->pci_bus), errp)) { + return; + } + if (s->sata_enabled && !ich9_realize_sata(s, errp)) { return; } diff --git a/hw/i386/Kconfig b/hw/i386/Kconfig index 226d7f6916..eccc834e49 100644 --- a/hw/i386/Kconfig +++ b/hw/i386/Kconfig @@ -100,7 +100,6 @@ config Q35 select PC_ACPI select PCI_EXPRESS_Q35 select ICH9 - select LPC_ICH9 select DIMM select SMBIOS select FW_CFG_DMA diff --git a/hw/southbridge/Kconfig b/hw/southbridge/Kconfig index 31eb125bf7..8ce62b703c 100644 --- a/hw/southbridge/Kconfig +++ b/hw/southbridge/Kconfig @@ -8,3 +8,4 @@ config ICH9 select ACPI_ICH9 imply USB_EHCI_PCI imply USB_UHCI + select LPC_ICH9 --=20 2.41.0