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Mon, 19 Feb 2024 00:33:34 -0800 (PST) From: Nicholas Piggin To: qemu-devel@nongnu.org Cc: Nicholas Piggin , qemu-ppc@nongnu.org, Daniel Henrique Barboza , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Harsh Prateek Bora , BALATON Zoltan Subject: [PULL 49/49] target/ppc: optimise ppcemb_tlb_t flushing Date: Mon, 19 Feb 2024 18:29:38 +1000 Message-ID: <20240219082938.238302-50-npiggin@gmail.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20240219082938.238302-1-npiggin@gmail.com> References: <20240219082938.238302-1-npiggin@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=npiggin@gmail.com; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1708331882336100001 Filter TLB flushing by PID and mmuidx. Zoltan reports that, together with the previous TLB flush changes, performance of a sam460ex machine running 'lame' to convert a wav to mp3 is improved nearly 10%: CPU time TLB partial flushes TLB elided flushes Before 37s 508238 7680722 After 34s 73 1143 Tested-by: BALATON Zoltan Acked-by: C=C3=A9dric Le Goater Signed-off-by: Nicholas Piggin --- target/ppc/mmu_helper.c | 43 +++++++++++++++++++++++++++++++++++------ 1 file changed, 37 insertions(+), 6 deletions(-) diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c index ba965f1779..c071b4d5e2 100644 --- a/target/ppc/mmu_helper.c +++ b/target/ppc/mmu_helper.c @@ -751,11 +751,20 @@ target_ulong helper_4xx_tlbre_lo(CPUPPCState *env, ta= rget_ulong entry) =20 static void ppcemb_tlb_flush(CPUState *cs, ppcemb_tlb_t *tlb) { - target_ulong ea; + unsigned mmu_idx =3D 0; =20 - for (ea =3D tlb->EPN; ea < tlb->EPN + tlb->size; ea +=3D TARGET_PAGE_S= IZE) { - tlb_flush_page(cs, ea); + if (tlb->prot & 0xf) { + mmu_idx |=3D 0x1; } + if ((tlb->prot >> 4) & 0xf) { + mmu_idx |=3D 0x2; + } + if (tlb->attr & 1) { + mmu_idx <<=3D 2; + } + + tlb_flush_range_by_mmuidx(cs, tlb->EPN, tlb->size, mmu_idx, + TARGET_LONG_BITS); } =20 void helper_4xx_tlbwe_hi(CPUPPCState *env, target_ulong entry, @@ -770,7 +779,7 @@ void helper_4xx_tlbwe_hi(CPUPPCState *env, target_ulong= entry, entry &=3D PPC4XX_TLB_ENTRY_MASK; tlb =3D &env->tlb.tlbe[entry]; /* Invalidate previous TLB (if it's valid) */ - if (tlb->prot & PAGE_VALID) { + if ((tlb->prot & PAGE_VALID) && tlb->PID =3D=3D env->spr[SPR_40x_PID])= { qemu_log_mask(CPU_LOG_MMU, "%s: invalidate old TLB %d start " TARGET_FMT_lx " end " TARGET_FMT_lx "\n", __func__, (int)entry, tlb->EPN, tlb->EPN + tlb->size); @@ -821,7 +830,7 @@ void helper_4xx_tlbwe_lo(CPUPPCState *env, target_ulong= entry, entry &=3D PPC4XX_TLB_ENTRY_MASK; tlb =3D &env->tlb.tlbe[entry]; /* Invalidate previous TLB (if it's valid) */ - if (tlb->prot & PAGE_VALID) { + if ((tlb->prot & PAGE_VALID) && tlb->PID =3D=3D env->spr[SPR_40x_PID])= { qemu_log_mask(CPU_LOG_MMU, "%s: invalidate old TLB %d start " TARGET_FMT_lx " end " TARGET_FMT_lx "\n", __func__, (int)entry, tlb->EPN, tlb->EPN + tlb->size); @@ -851,6 +860,25 @@ target_ulong helper_4xx_tlbsx(CPUPPCState *env, target= _ulong address) return ppcemb_tlb_search(env, address, env->spr[SPR_40x_PID]); } =20 +static bool mmubooke_pid_match(CPUPPCState *env, ppcemb_tlb_t *tlb) +{ + if (tlb->PID =3D=3D env->spr[SPR_BOOKE_PID]) { + return true; + } + if (!env->nb_pids) { + return false; + } + + if (env->spr[SPR_BOOKE_PID1] && tlb->PID =3D=3D env->spr[SPR_BOOKE_PID= 1]) { + return true; + } + if (env->spr[SPR_BOOKE_PID2] && tlb->PID =3D=3D env->spr[SPR_BOOKE_PID= 2]) { + return true; + } + + return false; +} + /* PowerPC 440 TLB management */ void helper_440_tlbwe(CPUPPCState *env, uint32_t word, target_ulong entry, target_ulong value) @@ -863,7 +891,10 @@ void helper_440_tlbwe(CPUPPCState *env, uint32_t word,= target_ulong entry, tlb =3D &env->tlb.tlbe[entry]; =20 /* Invalidate previous TLB (if it's valid) */ - if (tlb->prot & PAGE_VALID) { + if ((tlb->prot & PAGE_VALID) && mmubooke_pid_match(env, tlb)) { + qemu_log_mask(CPU_LOG_MMU, "%s: invalidate old TLB %d start " + TARGET_FMT_lx " end " TARGET_FMT_lx "\n", __func__, + (int)entry, tlb->EPN, tlb->EPN + tlb->size); ppcemb_tlb_flush(env_cpu(env), tlb); } =20 --=20 2.42.0